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Poonam Aggrwale394ceb2012-12-23 19:22:33 +00001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Roy Zang <tie-fei.zang@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwale394ceb2012-12-23 19:22:33 +00006 */
7#include <common.h>
8#include <phy.h>
9#include <fm_eth.h>
10#include <asm/io.h>
11#include <asm/immap_85xx.h>
12#include <asm/fsl_serdes.h>
Suresh Guptae2544e72014-11-13 11:28:09 +080013#include <hwconfig.h>
Poonam Aggrwale394ceb2012-12-23 19:22:33 +000014
15u32 port_to_devdisr[] = {
16 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
17 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
18 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
19 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
20 [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
21 [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
22 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
23 [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
24};
25
26static int is_device_disabled(enum fm_port port)
27{
28 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
29 u32 devdisr2 = in_be32(&gur->devdisr2);
30
31 return port_to_devdisr[port] & devdisr2;
32}
33
34void fman_disable_port(enum fm_port port)
35{
36 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
37
38 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
39}
40
Valentin Longchampf51d3b72013-10-18 11:47:21 +020041void fman_enable_port(enum fm_port port)
42{
43 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
44
45 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
46}
47
Poonam Aggrwale394ceb2012-12-23 19:22:33 +000048phy_interface_t fman_port_enet_if(enum fm_port port)
49{
Suresh Guptae2544e72014-11-13 11:28:09 +080050#if defined(CONFIG_B4860QDS)
51 u32 serdes2_prtcl;
52 char buffer[HWCONFIG_BUFFER_SIZE];
53 char *buf = NULL;
54 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
55#endif
56
Poonam Aggrwale394ceb2012-12-23 19:22:33 +000057 if (is_device_disabled(port))
58 return PHY_INTERFACE_MODE_NONE;
59
Suresh Gupta16d88f42013-03-25 07:40:13 +000060 /*B4860 has two 10Gig Mac*/
61 if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
62 ((is_serdes_configured(XAUI_FM1_MAC9)) ||
Suresh Guptae2544e72014-11-13 11:28:09 +080063 #if !defined(CONFIG_B4860QDS)
Shaohui Xie89b94d82014-11-13 11:26:19 +080064 (is_serdes_configured(XFI_FM1_MAC9)) ||
Suresh Guptae2544e72014-11-13 11:28:09 +080065 (is_serdes_configured(XFI_FM1_MAC10)) ||
66 #endif
67 (is_serdes_configured(XAUI_FM1_MAC10))
68 ))
Poonam Aggrwale394ceb2012-12-23 19:22:33 +000069 return PHY_INTERFACE_MODE_XGMII;
70
Suresh Guptae2544e72014-11-13 11:28:09 +080071#if defined(CONFIG_B4860QDS)
72 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
73 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
74
75 if (serdes2_prtcl) {
76 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
77 switch (serdes2_prtcl) {
78 case 0x80:
79 case 0x81:
80 case 0x82:
81 case 0x83:
82 case 0x84:
83 case 0x85:
84 case 0x86:
85 case 0x87:
86 case 0x88:
87 case 0x89:
88 case 0x8a:
89 case 0x8b:
90 case 0x8c:
91 case 0x8d:
92 case 0x8e:
93 case 0xb1:
94 case 0xb2:
95 /*
96 * Extract hwconfig from environment since environment
97 * is not setup yet
98 */
99 getenv_f("hwconfig", buffer, sizeof(buffer));
100 buf = buffer;
101
102 /* check if XFI interface enable in hwconfig for 10g */
103 if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
104 "sfp_amc", "sfp", buf)) {
105 if ((port == FM1_10GEC1 ||
106 port == FM1_10GEC2) &&
107 ((is_serdes_configured(XFI_FM1_MAC9)) ||
108 (is_serdes_configured(XFI_FM1_MAC10))))
109 return PHY_INTERFACE_MODE_XGMII;
110 else if ((port == FM1_DTSEC1) ||
111 (port == FM1_DTSEC2) ||
112 (port == FM1_DTSEC3) ||
113 (port == FM1_DTSEC4))
114 return PHY_INTERFACE_MODE_NONE;
115 }
116 }
117 }
118#endif
119
Poonam Aggrwale394ceb2012-12-23 19:22:33 +0000120 /* Fix me need to handle RGMII here first */
121
122 switch (port) {
123 case FM1_DTSEC1:
124 case FM1_DTSEC2:
125 case FM1_DTSEC3:
126 case FM1_DTSEC4:
127 case FM1_DTSEC5:
128 case FM1_DTSEC6:
129 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
130 return PHY_INTERFACE_MODE_SGMII;
131 break;
132 default:
133 return PHY_INTERFACE_MODE_NONE;
134 }
135
136 return PHY_INTERFACE_MODE_NONE;
137}