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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
Stefan Roese46f37382008-04-08 10:31:00 +02002 * (C) Copyright 2006-2008
Stefan Roese887e2ec2006-09-07 11:51:23 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
22#include <nand.h>
Stefan Roesec568f772008-01-05 16:49:37 +010023#include <asm/io.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020024
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#define CONFIG_SYS_NAND_READ_DELAY \
Stefan Roese887e2ec2006-09-07 11:51:23 +020026 { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
27
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
Stefan Roese887e2ec2006-09-07 11:51:23 +020029
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
Stefan Roese46f37382008-04-08 10:31:00 +020031/*
32 * NAND command for small page NAND devices (512)
33 */
Stefan Roese42be56f2007-06-01 15:23:04 +020034static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
Stefan Roese887e2ec2006-09-07 11:51:23 +020035{
Wolfgang Denk511d0c72006-10-09 00:42:01 +020036 struct nand_chip *this = mtd->priv;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
Stefan Roese42be56f2007-06-01 15:23:04 +020038
39 if (this->dev_ready)
Stefan Roesec568f772008-01-05 16:49:37 +010040 while (!this->dev_ready(mtd))
41 ;
Stefan Roese42be56f2007-06-01 15:23:04 +020042 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 CONFIG_SYS_NAND_READ_DELAY;
Stefan Roese887e2ec2006-09-07 11:51:23 +020044
45 /* Begin command latch cycle */
Scott Wood4f32d772008-08-05 11:15:59 -050046 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Stefan Roese887e2ec2006-09-07 11:51:23 +020047 /* Set ALE and clear CLE to start address cycle */
Stefan Roese887e2ec2006-09-07 11:51:23 +020048 /* Column address */
Scott Wood4f32d772008-08-05 11:15:59 -050049 this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
Scott Wood1dac3a52009-06-24 17:23:49 -050050 this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
51 this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
52 NAND_CTRL_ALE); /* A[24:17] */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
Stefan Roese887e2ec2006-09-07 11:51:23 +020054 /* One more address cycle for devices > 32MiB */
Scott Wood1dac3a52009-06-24 17:23:49 -050055 this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
56 NAND_CTRL_ALE); /* A[28:25] */
Stefan Roese887e2ec2006-09-07 11:51:23 +020057#endif
58 /* Latch in address */
Stefan Roesec568f772008-01-05 16:49:37 +010059 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Stefan Roese887e2ec2006-09-07 11:51:23 +020060
61 /*
62 * Wait a while for the data to be ready
63 */
64 if (this->dev_ready)
Stefan Roesec568f772008-01-05 16:49:37 +010065 while (!this->dev_ready(mtd))
66 ;
Stefan Roese887e2ec2006-09-07 11:51:23 +020067 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068 CONFIG_SYS_NAND_READ_DELAY;
Stefan Roese887e2ec2006-09-07 11:51:23 +020069
Stefan Roese42be56f2007-06-01 15:23:04 +020070 return 0;
71}
Stefan Roese46f37382008-04-08 10:31:00 +020072#else
73/*
74 * NAND command for large page NAND devices (2k)
75 */
76static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
77{
78 struct nand_chip *this = mtd->priv;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
Stefan Roese46f37382008-04-08 10:31:00 +020080
81 if (this->dev_ready)
Scott Wood4f32d772008-08-05 11:15:59 -050082 while (!this->dev_ready(mtd))
83 ;
Stefan Roese46f37382008-04-08 10:31:00 +020084 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 CONFIG_SYS_NAND_READ_DELAY;
Stefan Roese46f37382008-04-08 10:31:00 +020086
87 /* Emulate NAND_CMD_READOOB */
88 if (cmd == NAND_CMD_READOOB) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 offs += CONFIG_SYS_NAND_PAGE_SIZE;
Stefan Roese46f37382008-04-08 10:31:00 +020090 cmd = NAND_CMD_READ0;
91 }
92
93 /* Begin command latch cycle */
Scott Wood4f32d772008-08-05 11:15:59 -050094 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Stefan Roese46f37382008-04-08 10:31:00 +020095 /* Set ALE and clear CLE to start address cycle */
Stefan Roese46f37382008-04-08 10:31:00 +020096 /* Column address */
Scott Wood4f32d772008-08-05 11:15:59 -050097 this->cmd_ctrl(mtd, offs & 0xff,
Wolfgang Denk4b070802008-08-14 14:41:06 +020098 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
Scott Wood1dac3a52009-06-24 17:23:49 -050099 this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
Stefan Roese46f37382008-04-08 10:31:00 +0200100 /* Row address */
Scott Wood1dac3a52009-06-24 17:23:49 -0500101 this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
102 this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
103 NAND_CTRL_ALE); /* A[27:20] */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
Stefan Roese46f37382008-04-08 10:31:00 +0200105 /* One more address cycle for devices > 128MiB */
Scott Wood1dac3a52009-06-24 17:23:49 -0500106 this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
107 NAND_CTRL_ALE); /* A[31:28] */
Stefan Roese46f37382008-04-08 10:31:00 +0200108#endif
109 /* Latch in address */
Scott Wood4f32d772008-08-05 11:15:59 -0500110 this->cmd_ctrl(mtd, NAND_CMD_READSTART,
Wolfgang Denk4b070802008-08-14 14:41:06 +0200111 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
Scott Wood4f32d772008-08-05 11:15:59 -0500112 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
Stefan Roese46f37382008-04-08 10:31:00 +0200113
114 /*
115 * Wait a while for the data to be ready
116 */
117 if (this->dev_ready)
Scott Wood4f32d772008-08-05 11:15:59 -0500118 while (!this->dev_ready(mtd))
119 ;
Stefan Roese46f37382008-04-08 10:31:00 +0200120 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 CONFIG_SYS_NAND_READ_DELAY;
Stefan Roese46f37382008-04-08 10:31:00 +0200122
123 return 0;
124}
125#endif
Stefan Roese42be56f2007-06-01 15:23:04 +0200126
127static int nand_is_bad_block(struct mtd_info *mtd, int block)
128{
129 struct nand_chip *this = mtd->priv;
130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
Stefan Roese42be56f2007-06-01 15:23:04 +0200132
Stefan Roese887e2ec2006-09-07 11:51:23 +0200133 /*
Marcel Ziswiler10c73822007-12-30 03:30:56 +0100134 * Read one byte
Stefan Roese887e2ec2006-09-07 11:51:23 +0200135 */
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200136 if (readb(this->IO_ADDR_R) != 0xff)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200137 return 1;
138
139 return 0;
140}
141
142static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
143{
Wolfgang Denk511d0c72006-10-09 00:42:01 +0200144 struct nand_chip *this = mtd->priv;
Stefan Roese42be56f2007-06-01 15:23:04 +0200145 u_char *ecc_calc;
146 u_char *ecc_code;
147 u_char *oob_data;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200148 int i;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
150 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
151 int eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
Stefan Roese42be56f2007-06-01 15:23:04 +0200152 uint8_t *p = dst;
153 int stat;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200154
Stefan Roese42be56f2007-06-01 15:23:04 +0200155 nand_command(mtd, block, page, 0, NAND_CMD_READ0);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200156
Stefan Roese42be56f2007-06-01 15:23:04 +0200157 /* No malloc available for now, just use some temporary locations
158 * in SDRAM
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE + 0x10000);
Stefan Roese42be56f2007-06-01 15:23:04 +0200161 ecc_code = ecc_calc + 0x100;
162 oob_data = ecc_calc + 0x200;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200163
Stefan Roese42be56f2007-06-01 15:23:04 +0200164 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
Stefan Roesec568f772008-01-05 16:49:37 +0100165 this->ecc.hwctl(mtd, NAND_ECC_READ);
Stefan Roese42be56f2007-06-01 15:23:04 +0200166 this->read_buf(mtd, p, eccsize);
Stefan Roesec568f772008-01-05 16:49:37 +0100167 this->ecc.calculate(mtd, p, &ecc_calc[i]);
Stefan Roese42be56f2007-06-01 15:23:04 +0200168 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
Stefan Roese42be56f2007-06-01 15:23:04 +0200170
171 /* Pick the ECC bytes out of the oob data */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 for (i = 0; i < CONFIG_SYS_NAND_ECCTOTAL; i++)
Stefan Roese42be56f2007-06-01 15:23:04 +0200173 ecc_code[i] = oob_data[nand_ecc_pos[i]];
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 eccsteps = CONFIG_SYS_NAND_ECCSTEPS;
Stefan Roese42be56f2007-06-01 15:23:04 +0200176 p = dst;
177
178 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
179 /* No chance to do something with the possible error message
180 * from correct_data(). We just hope that all possible errors
181 * are corrected by this routine.
182 */
Stefan Roesec568f772008-01-05 16:49:37 +0100183 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Stefan Roese42be56f2007-06-01 15:23:04 +0200184 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200185
186 return 0;
187}
188
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200189static int nand_load(struct mtd_info *mtd, unsigned int offs,
Wolfgang Denk4b070802008-08-14 14:41:06 +0200190 unsigned int uboot_size, uchar *dst)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200191{
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200192 unsigned int block, lastblock;
193 unsigned int page;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200194
195 /*
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200196 * offs has to be aligned to a page address!
Stefan Roese887e2ec2006-09-07 11:51:23 +0200197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
199 lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
200 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200201
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200202 while (block <= lastblock) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200203 if (!nand_is_bad_block(mtd, block)) {
204 /*
205 * Skip bad blocks
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
Stefan Roese887e2ec2006-09-07 11:51:23 +0200208 nand_read_page(mtd, block, page, dst);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209 dst += CONFIG_SYS_NAND_PAGE_SIZE;
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200210 page++;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200211 }
212
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200213 page = 0;
214 } else {
215 lastblock++;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200216 }
217
218 block++;
219 }
220
221 return 0;
222}
223
Stefan Roese64852d02008-06-02 14:35:44 +0200224/*
225 * The main entry for NAND booting. It's necessary that SDRAM is already
226 * configured and available since this code loads the main U-Boot image
227 * from NAND into SDRAM and starts it from there.
228 */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200229void nand_boot(void)
230{
Stefan Roese887e2ec2006-09-07 11:51:23 +0200231 struct nand_chip nand_chip;
232 nand_info_t nand_info;
233 int ret;
Scott Woode4c09502008-06-30 14:13:28 -0500234 __attribute__((noreturn)) void (*uboot)(void);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200235
236 /*
Stefan Roese887e2ec2006-09-07 11:51:23 +0200237 * Init board specific nand support
238 */
239 nand_info.priv = &nand_chip;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200241 nand_chip.dev_ready = NULL; /* preset to NULL */
242 board_nand_init(&nand_chip);
243
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200244 if (nand_chip.select_chip)
245 nand_chip.select_chip(&nand_info, 0);
246
Stefan Roese887e2ec2006-09-07 11:51:23 +0200247 /*
248 * Load U-Boot image from NAND into RAM
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250 ret = nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
251 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200252
Guennadi Liakhovetskib74ab732009-05-18 16:07:22 +0200253#ifdef CONFIG_NAND_ENV_DST
254 nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
255 (uchar *)CONFIG_NAND_ENV_DST);
256
257#ifdef CONFIG_ENV_OFFSET_REDUND
258 nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
259 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
260#endif
261#endif
262
Guennadi Liakhovetskiaa646642008-08-06 21:42:07 +0200263 if (nand_chip.select_chip)
264 nand_chip.select_chip(&nand_info, -1);
265
Stefan Roese887e2ec2006-09-07 11:51:23 +0200266 /*
267 * Jump to U-Boot image
268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200270 (*uboot)();
271}