blob: 4291e496fa7fc3ddceee1f9c56cc114fc2000e5a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren4e5ae092011-06-17 06:27:28 +00002/*
Allen Martin00a27492012-08-31 08:30:00 +00003 * NVIDIA Tegra20 GPIO handling.
Stephen Warrenfe828572015-09-25 10:44:08 -06004 * (C) Copyright 2010-2012,2015
Tom Warren4e5ae092011-06-17 06:27:28 +00005 * NVIDIA Corporation <www.nvidia.com>
Tom Warren4e5ae092011-06-17 06:27:28 +00006 */
7
8/*
9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
10 * Tom Warren (twarren@nvidia.com)
11 */
12
13#include <common.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060014#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060015#include <log.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060016#include <malloc.h>
17#include <errno.h>
18#include <fdtdec.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000019#include <asm/io.h>
20#include <asm/bitops.h>
Tom Warren150c2492012-09-19 15:50:56 -070021#include <asm/arch/tegra.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000022#include <asm/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060023#include <dm/device-internal.h>
Simon Glass838aa5c2015-01-05 20:05:33 -070024#include <dt-bindings/gpio/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060025
Simon Glass80a48762021-08-08 12:20:23 -060026static const int CFG_SFIO = 0;
27static const int CFG_GPIO = 1;
Stephen Warrenfe828572015-09-25 10:44:08 -060028static const int DIRECTION_INPUT = 0;
29static const int DIRECTION_OUTPUT = 1;
30
Simon Glass8a8d24b2020-12-03 16:55:23 -070031struct tegra_gpio_plat {
Simon Glass2fccd2d2014-09-03 17:37:03 -060032 struct gpio_ctlr_bank *bank;
33 const char *port_name; /* Name of port, e.g. "B" */
34 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
35};
Tom Warren4e5ae092011-06-17 06:27:28 +000036
Simon Glass2fccd2d2014-09-03 17:37:03 -060037/* Information about each port at run-time */
38struct tegra_port_info {
Simon Glass2fccd2d2014-09-03 17:37:03 -060039 struct gpio_ctlr_bank *bank;
40 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
41};
Tom Warren4e5ae092011-06-17 06:27:28 +000042
Stephen Warrenfe828572015-09-25 10:44:08 -060043/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
Joe Hershberger365d6072011-11-11 15:55:36 -060044static int get_config(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000045{
Joe Hershberger365d6072011-11-11 15:55:36 -060046 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
47 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000048 u32 u;
49 int type;
50
Joe Hershberger365d6072011-11-11 15:55:36 -060051 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -060052 type = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000053
54 debug("get_config: port = %d, bit = %d is %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060055 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000056
Simon Glass80a48762021-08-08 12:20:23 -060057 return type ? CFG_GPIO : CFG_SFIO;
Tom Warren4e5ae092011-06-17 06:27:28 +000058}
59
Stephen Warrenfe828572015-09-25 10:44:08 -060060/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
Joe Hershberger365d6072011-11-11 15:55:36 -060061static void set_config(unsigned gpio, int type)
Tom Warren4e5ae092011-06-17 06:27:28 +000062{
Joe Hershberger365d6072011-11-11 15:55:36 -060063 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
64 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000065 u32 u;
66
67 debug("set_config: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060068 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000069
Joe Hershberger365d6072011-11-11 15:55:36 -060070 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Simon Glass80a48762021-08-08 12:20:23 -060071 if (type != CFG_SFIO)
Joe Hershberger365d6072011-11-11 15:55:36 -060072 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +000073 else
Joe Hershberger365d6072011-11-11 15:55:36 -060074 u &= ~(1 << GPIO_BIT(gpio));
75 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +000076}
77
Joe Hershberger365d6072011-11-11 15:55:36 -060078/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
79static int get_direction(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000080{
Joe Hershberger365d6072011-11-11 15:55:36 -060081 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
82 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000083 u32 u;
84 int dir;
85
Joe Hershberger365d6072011-11-11 15:55:36 -060086 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
87 dir = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000088
89 debug("get_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060090 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +000091
Stephen Warrenfe828572015-09-25 10:44:08 -060092 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +000093}
94
Joe Hershberger365d6072011-11-11 15:55:36 -060095/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
96static void set_direction(unsigned gpio, int output)
Tom Warren4e5ae092011-06-17 06:27:28 +000097{
Joe Hershberger365d6072011-11-11 15:55:36 -060098 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
99 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000100 u32 u;
101
102 debug("set_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600103 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +0000104
Joe Hershberger365d6072011-11-11 15:55:36 -0600105 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -0600106 if (output != DIRECTION_INPUT)
Joe Hershberger365d6072011-11-11 15:55:36 -0600107 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000108 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600109 u &= ~(1 << GPIO_BIT(gpio));
110 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000111}
112
Joe Hershberger365d6072011-11-11 15:55:36 -0600113/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
114static void set_level(unsigned gpio, int high)
Tom Warren4e5ae092011-06-17 06:27:28 +0000115{
Joe Hershberger365d6072011-11-11 15:55:36 -0600116 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
117 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000118 u32 u;
119
120 debug("set_level: port = %d, bit %d == %d\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600121 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
Tom Warren4e5ae092011-06-17 06:27:28 +0000122
Joe Hershberger365d6072011-11-11 15:55:36 -0600123 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000124 if (high)
Joe Hershberger365d6072011-11-11 15:55:36 -0600125 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000126 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600127 u &= ~(1 << GPIO_BIT(gpio));
128 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000129}
130
131/*
132 * Generic_GPIO primitives.
133 */
134
Joe Hershberger365d6072011-11-11 15:55:36 -0600135/* set GPIO pin 'gpio' as an input */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600136static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000137{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600138 struct tegra_port_info *state = dev_get_priv(dev);
Tom Warren4e5ae092011-06-17 06:27:28 +0000139
140 /* Configure GPIO direction as input. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600141 set_direction(state->base_gpio + offset, DIRECTION_INPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000142
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600143 /* Enable the pin as a GPIO */
144 set_config(state->base_gpio + offset, 1);
145
Tom Warren4e5ae092011-06-17 06:27:28 +0000146 return 0;
147}
148
Joe Hershberger365d6072011-11-11 15:55:36 -0600149/* set GPIO pin 'gpio' as an output, with polarity 'value' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600150static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
151 int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000152{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600153 struct tegra_port_info *state = dev_get_priv(dev);
154 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000155
156 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600157 set_level(gpio, value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000158
159 /* Configure GPIO direction as output. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600160 set_direction(gpio, DIRECTION_OUTPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000161
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600162 /* Enable the pin as a GPIO */
163 set_config(state->base_gpio + offset, 1);
164
Tom Warren4e5ae092011-06-17 06:27:28 +0000165 return 0;
166}
167
Joe Hershberger365d6072011-11-11 15:55:36 -0600168/* read GPIO IN value of pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600169static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000170{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600171 struct tegra_port_info *state = dev_get_priv(dev);
172 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000173 int val;
174
Simon Glass2fccd2d2014-09-03 17:37:03 -0600175 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
176 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
177
Simon Glass651827c2016-01-30 16:37:45 -0700178 if (get_direction(gpio) == DIRECTION_INPUT)
179 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
180 else
181 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000182
Joe Hershberger365d6072011-11-11 15:55:36 -0600183 return (val >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +0000184}
185
Joe Hershberger365d6072011-11-11 15:55:36 -0600186/* write GPIO OUT value to pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600187static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000188{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600189 struct tegra_port_info *state = dev_get_priv(dev);
190 int gpio = state->base_gpio + offset;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600191
Tom Warren4e5ae092011-06-17 06:27:28 +0000192 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
Simon Glass2fccd2d2014-09-03 17:37:03 -0600193 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000194
195 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600196 set_level(gpio, value);
197
198 return 0;
Tom Warren4e5ae092011-06-17 06:27:28 +0000199}
200
Stephen Warreneceb3f22014-04-22 14:37:53 -0600201void gpio_config_table(const struct tegra_gpio_config *config, int len)
202{
203 int i;
204
205 for (i = 0; i < len; i++) {
206 switch (config[i].init) {
207 case TEGRA_GPIO_INIT_IN:
Stephen Warrenfe828572015-09-25 10:44:08 -0600208 set_direction(config[i].gpio, DIRECTION_INPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600209 break;
210 case TEGRA_GPIO_INIT_OUT0:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600211 set_level(config[i].gpio, 0);
Stephen Warrenfe828572015-09-25 10:44:08 -0600212 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600213 break;
214 case TEGRA_GPIO_INIT_OUT1:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600215 set_level(config[i].gpio, 1);
Stephen Warrenfe828572015-09-25 10:44:08 -0600216 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600217 break;
218 }
Simon Glass80a48762021-08-08 12:20:23 -0600219 set_config(config[i].gpio, CFG_GPIO);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600220 }
221}
222
Simon Glass2fccd2d2014-09-03 17:37:03 -0600223static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000224{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600225 struct tegra_port_info *state = dev_get_priv(dev);
226 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000227
Simon Glass2fccd2d2014-09-03 17:37:03 -0600228 if (!get_config(gpio))
229 return GPIOF_FUNC;
230 else if (get_direction(gpio))
231 return GPIOF_OUTPUT;
232 else
233 return GPIOF_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +0000234}
Simon Glass2fccd2d2014-09-03 17:37:03 -0600235
Simon Glass838aa5c2015-01-05 20:05:33 -0700236static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
Simon Glass3a571232017-05-18 20:09:18 -0600237 struct ofnode_phandle_args *args)
Simon Glass838aa5c2015-01-05 20:05:33 -0700238{
239 int gpio, port, ret;
240
241 gpio = args->args[0];
242 port = gpio / TEGRA_GPIOS_PER_PORT;
243 ret = device_get_child(dev, port, &desc->dev);
244 if (ret)
245 return ret;
246 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
247 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
248
249 return 0;
250}
251
Simon Glass2fccd2d2014-09-03 17:37:03 -0600252static const struct dm_gpio_ops gpio_tegra_ops = {
Simon Glass2fccd2d2014-09-03 17:37:03 -0600253 .direction_input = tegra_gpio_direction_input,
254 .direction_output = tegra_gpio_direction_output,
255 .get_value = tegra_gpio_get_value,
256 .set_value = tegra_gpio_set_value,
257 .get_function = tegra_gpio_get_function,
Simon Glass838aa5c2015-01-05 20:05:33 -0700258 .xlate = tegra_gpio_xlate,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600259};
260
261/**
262 * Returns the name of a GPIO port
263 *
264 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
265 *
266 * @base_port: Base port number (0, 1..n-1)
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100267 * Return: allocated string containing the name
Simon Glass2fccd2d2014-09-03 17:37:03 -0600268 */
269static char *gpio_port_name(int base_port)
270{
271 char *name, *s;
272
273 name = malloc(3);
274 if (name) {
275 s = name;
276 *s++ = 'A' + (base_port % 26);
277 if (base_port >= 26)
278 *s++ = *name;
279 *s = '\0';
280 }
281
282 return name;
283}
284
285static const struct udevice_id tegra_gpio_ids[] = {
286 { .compatible = "nvidia,tegra30-gpio" },
287 { .compatible = "nvidia,tegra20-gpio" },
288 { }
289};
290
291static int gpio_tegra_probe(struct udevice *dev)
292{
Simon Glasse564f052015-03-05 12:25:20 -0700293 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass0fd3d912020-12-22 19:30:28 -0700294 struct tegra_port_info *priv = dev_get_priv(dev);
295 struct tegra_gpio_plat *plat = dev_get_plat(dev);
Simon Glass2fccd2d2014-09-03 17:37:03 -0600296
297 /* Only child devices have ports */
298 if (!plat)
299 return 0;
300
301 priv->bank = plat->bank;
302 priv->base_gpio = plat->base_gpio;
303
304 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
305 uc_priv->bank_name = plat->port_name;
306
307 return 0;
308}
309
310/**
311 * We have a top-level GPIO device with no actual GPIOs. It has a child
312 * device for each Tegra port.
313 */
314static int gpio_tegra_bind(struct udevice *parent)
315{
Simon Glass0fd3d912020-12-22 19:30:28 -0700316 struct tegra_gpio_plat *plat = dev_get_plat(parent);
Simon Glass2fccd2d2014-09-03 17:37:03 -0600317 struct gpio_ctlr *ctlr;
318 int bank_count;
319 int bank;
320 int ret;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600321
322 /* If this is a child device, there is nothing to do here */
323 if (plat)
324 return 0;
325
Simon Glassbdfb3412015-03-03 08:02:59 -0700326 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
327#ifdef CONFIG_SPL_BUILD
328 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
329 bank_count = TEGRA_GPIO_BANKS;
330#else
331 {
332 int len;
333
Simon Glass2fccd2d2014-09-03 17:37:03 -0600334 /*
335 * This driver does not make use of interrupts, other than to figure
336 * out the number of GPIO banks
337 */
Simon Glass56f5c402017-07-25 08:30:03 -0600338 len = dev_read_size(parent, "interrupts");
339 if (len < 0)
340 return len;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600341 bank_count = len / 3 / sizeof(u32);
Simon Glass56f5c402017-07-25 08:30:03 -0600342 ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
343 if ((ulong)ctlr == FDT_ADDR_T_NONE)
344 return -EINVAL;
Simon Glassbdfb3412015-03-03 08:02:59 -0700345 }
346#endif
Simon Glass2fccd2d2014-09-03 17:37:03 -0600347 for (bank = 0; bank < bank_count; bank++) {
348 int port;
349
350 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
Simon Glass8a8d24b2020-12-03 16:55:23 -0700351 struct tegra_gpio_plat *plat;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600352 struct udevice *dev;
353 int base_port;
354
355 plat = calloc(1, sizeof(*plat));
356 if (!plat)
357 return -ENOMEM;
358 plat->bank = &ctlr->gpio_bank[bank];
359 base_port = bank * TEGRA_PORTS_PER_BANK + port;
360 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
361 plat->port_name = gpio_port_name(base_port);
362
Simon Glassa2703ce2020-11-28 17:50:03 -0700363 ret = device_bind(parent, parent->driver,
Simon Glass20da4e02020-11-28 17:50:04 -0700364 plat->port_name, plat,
365 dev_ofnode(parent), &dev);
Simon Glass2fccd2d2014-09-03 17:37:03 -0600366 if (ret)
367 return ret;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600368 }
369 }
370
371 return 0;
372}
373
374U_BOOT_DRIVER(gpio_tegra) = {
375 .name = "gpio_tegra",
376 .id = UCLASS_GPIO,
377 .of_match = tegra_gpio_ids,
378 .bind = gpio_tegra_bind,
379 .probe = gpio_tegra_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700380 .priv_auto = sizeof(struct tegra_port_info),
Simon Glass2fccd2d2014-09-03 17:37:03 -0600381 .ops = &gpio_tegra_ops,
382};