blob: e7f01d00d1d7663879944dde01a69f1b477e6e2f [file] [log] [blame]
Jon Loeliger9553df82007-10-16 15:26:51 -05001/*
Timur Tabiba8e76b2011-04-11 14:18:22 -05002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Jon Loeliger9553df82007-10-16 15:26:51 -05003 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Jon Loeliger9553df82007-10-16 15:26:51 -05005 */
6
7/*
8 * MPC8610HPCD board configuration file
Jon Loeliger9553df82007-10-16 15:26:51 -05009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun9ae14ca2015-08-18 12:35:52 -070014#define CONFIG_DISPLAY_BOARDINFO
15
Jon Loeliger9553df82007-10-16 15:26:51 -050016/* High Level Configuration Options */
Jon Loeliger9553df82007-10-16 15:26:51 -050017#define CONFIG_MPC8610 1 /* MPC8610 specific */
18#define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */
Jon Loeliger9553df82007-10-16 15:26:51 -050019#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xfff00000
22
York Sun070ba562007-10-31 14:59:04 -050023/* video */
Timur Tabiba8e76b2011-04-11 14:18:22 -050024#define CONFIG_FSL_DIU_FB
25
Timur Tabi7d3053f2011-02-15 17:09:19 -060026#ifdef CONFIG_FSL_DIU_FB
27#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
28#define CONFIG_VIDEO
Timur Tabie69e5202010-08-31 19:56:43 -050029#define CONFIG_CMD_BMP
York Sun070ba562007-10-31 14:59:04 -050030#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -060031#define CONFIG_VIDEO_SW_CURSOR
York Sun070ba562007-10-31 14:59:04 -050032#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabie69e5202010-08-31 19:56:43 -050033#define CONFIG_VIDEO_LOGO
34#define CONFIG_VIDEO_BMP_LOGO
York Sun070ba562007-10-31 14:59:04 -050035#endif
36
Jon Loeliger9553df82007-10-16 15:26:51 -050037#ifdef RUN_DIAG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_DIAG_ADDR 0xff800000
Jon Loeliger9553df82007-10-16 15:26:51 -050039#endif
40
Becky Bruce1266df82008-11-03 15:44:01 -060041/*
42 * virtual address to be used for temporary mappings. There
43 * should be 128k free at this VA.
44 */
45#define CONFIG_SYS_SCRATCH_VA 0xc0000000
46
Jon Loeliger9553df82007-10-16 15:26:51 -050047#define CONFIG_PCI 1 /* Enable PCI/PCIE*/
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040048#define CONFIG_PCI1 1 /* PCI controller 1 */
Jon Loeliger9553df82007-10-16 15:26:51 -050049#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
50#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
51#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000052#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ba93f62008-10-21 18:06:15 -050053#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce031976f2008-01-23 16:31:02 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Jon Loeliger9553df82007-10-16 15:26:51 -050055
56#define CONFIG_ENV_OVERWRITE
Jon Loeliger9553df82007-10-16 15:26:51 -050057#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
58
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050059#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050060#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
Jon Loeliger9553df82007-10-16 15:26:51 -050061#define CONFIG_ALTIVEC 1
62
63/*
64 * L2CR setup -- make sure this is right for your board!
65 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_L2
Jon Loeliger9553df82007-10-16 15:26:51 -050067#define L2_INIT 0
York Suna8778802007-10-29 13:58:39 -050068#define L2_ENABLE (L2CR_L2E |0x00100000 )
Jon Loeliger9553df82007-10-16 15:26:51 -050069
70#ifndef CONFIG_SYS_CLK_FREQ
71#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
72#endif
73
74#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
York Suna8778802007-10-29 13:58:39 -050075#define CONFIG_MISC_INIT_R 1
Jon Loeliger9553df82007-10-16 15:26:51 -050076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
78#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeliger9553df82007-10-16 15:26:51 -050079
80/*
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
86#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeliger9553df82007-10-16 15:26:51 -050087
Jon Loeligerf6987382008-11-20 14:02:56 -060088#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
89#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
Kumar Galaad19e7a2009-08-05 07:59:35 -050090#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
Jon Loeligerf6987382008-11-20 14:02:56 -060091
Jon Loeliger39aa1a72008-08-26 15:01:36 -050092/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070093#define CONFIG_SYS_FSL_DDR2
Jon Loeliger39aa1a72008-08-26 15:01:36 -050094#undef CONFIG_FSL_DDR_INTERACTIVE
95#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
96#define CONFIG_DDR_SPD
97
98#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
99#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600103#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500104#define CONFIG_VERY_BIG_RAM
105
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500106#define CONFIG_NUM_DDR_CONTROLLERS 1
107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeliger9553df82007-10-16 15:26:51 -0500109
Kumar Galac39f44d2011-01-31 22:18:47 -0600110#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500111
112/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jon Loeliger9553df82007-10-16 15:26:51 -0500114
115#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
117#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
118#define CONFIG_SYS_DDR_TIMING_3 0x00000000
119#define CONFIG_SYS_DDR_TIMING_0 0x00260802
120#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
121#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
122#define CONFIG_SYS_DDR_MODE_1 0x00480432
123#define CONFIG_SYS_DDR_MODE_2 0x00000000
124#define CONFIG_SYS_DDR_INTERVAL 0x06180100
125#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
126#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
127#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
128#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
129#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
130#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Jon Loeliger9553df82007-10-16 15:26:51 -0500131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
133#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
134#define CONFIG_SYS_DDR_SBE 0x000f0000
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500135
Jon Loeliger9553df82007-10-16 15:26:51 -0500136#endif
Jon Loeliger39aa1a72008-08-26 15:01:36 -0500137
Jon Loeligerad8f8682008-01-15 13:42:41 -0600138#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200140#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
142#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
145#define CONFIG_SYS_FLASH_BASE2 0xf8000000
Jon Loeliger9553df82007-10-16 15:26:51 -0500146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
Jon Loeliger9553df82007-10-16 15:26:51 -0500148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */
150#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */
153#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */
Jon Loeliger9553df82007-10-16 15:26:51 -0500154#if 0 /* TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BR2_PRELIM 0xf0000000
156#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500157#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */
159#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500160
Jason Jin761421c2007-10-29 19:26:21 +0800161#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger9553df82007-10-16 15:26:51 -0500162#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
163#define PIXIS_ID 0x0 /* Board ID at offset 0 */
164#define PIXIS_VER 0x1 /* Board version at offset 1 */
165#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
166#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
167#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
168#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
York Suna8778802007-10-29 13:58:39 -0500169#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500170#define PIXIS_VCTL 0x10 /* VELA Control Register */
171#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
172#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
173#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
174#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
175#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
176#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
177#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500178#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */
Jon Loeliger9553df82007-10-16 15:26:51 -0500179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
181#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jon Loeliger9553df82007-10-16 15:26:51 -0500182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#undef CONFIG_SYS_FLASH_CHECKSUM
184#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
185#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200186#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600187#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500188
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200189#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_CFI
191#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
194#define CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500195#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#undef CONFIG_SYS_RAMBOOT
Jon Loeliger9553df82007-10-16 15:26:51 -0500197#endif
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger9553df82007-10-16 15:26:51 -0500200#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeliger9553df82007-10-16 15:26:51 -0500202#endif
203
204#undef CONFIG_CLOCKS_IN_MHZ
205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_INIT_RAM_LOCK 1
207#ifndef CONFIG_SYS_INIT_RAM_LOCK
208#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500209#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500211#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200212#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeliger9553df82007-10-16 15:26:51 -0500213
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200214#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger9553df82007-10-16 15:26:51 -0500216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
218#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
Jon Loeliger9553df82007-10-16 15:26:51 -0500219
220/* Serial Port */
221#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550_SERIAL
223#define CONFIG_SYS_NS16550_REG_SIZE 1
224#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger9553df82007-10-16 15:26:51 -0500225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger9553df82007-10-16 15:26:51 -0500227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
230#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger9553df82007-10-16 15:26:51 -0500231
Jon Loeliger9553df82007-10-16 15:26:51 -0500232/* maximum size of the flat tree (8K) */
233#define OF_FLAT_TREE_MAX_SIZE 8192
234
Jon Loeliger9553df82007-10-16 15:26:51 -0500235/*
236 * I2C
237 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200238#define CONFIG_SYS_I2C
239#define CONFIG_SYS_I2C_FSL
240#define CONFIG_SYS_FSL_I2C_SPEED 400000
241#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
242#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
243#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeliger9553df82007-10-16 15:26:51 -0500244
245/*
246 * General PCI
247 * Addresses are mapped 1-1.
248 */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600249#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
250#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
251#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600253#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600255#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500257
Jon Loeliger9553df82007-10-16 15:26:51 -0500258/* controller 1, Base address 0xa000 */
Kumar Galab8526212010-12-17 10:42:33 -0600259#define CONFIG_SYS_PCIE1_NAME "ULI"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600260#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
261#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600263#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
265#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500266
267/* controller 2, Base Address 0x9000 */
Kumar Galab8526212010-12-17 10:42:33 -0600268#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600269#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
270#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600272#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
274#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger9553df82007-10-16 15:26:51 -0500275
Jon Loeliger9553df82007-10-16 15:26:51 -0500276#if defined(CONFIG_PCI)
277
278#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
279
Jon Loeliger9553df82007-10-16 15:26:51 -0500280#define CONFIG_PCI_PNP /* do pci plug-and-play */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600281#define CONFIG_CMD_REGINFO
Jon Loeliger9553df82007-10-16 15:26:51 -0500282
Roy Zang7c2221e2008-01-15 16:38:38 +0800283#define CONFIG_ULI526X
284#ifdef CONFIG_ULI526X
Roy Zang1d8a49e2007-09-13 18:52:28 +0800285#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500286
Jon Loeliger9553df82007-10-16 15:26:51 -0500287/************************************************************
288 * USB support
289 ************************************************************/
York Sun070ba562007-10-31 14:59:04 -0500290#define CONFIG_PCI_OHCI 1
291#define CONFIG_USB_OHCI_NEW 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500292#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200293#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_USB_EVENT_POLL 1
295#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
296#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
297#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Jon Loeliger9553df82007-10-16 15:26:51 -0500298
299#if !defined(CONFIG_PCI_PNP)
300#define PCI_ENET0_IOADDR 0xe0000000
301#define PCI_ENET0_MEMADDR 0xe0000000
302#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
303#endif
304
305#define CONFIG_DOS_PARTITION
306#define CONFIG_SCSI_AHCI
307
308#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500309#define CONFIG_LIBATA
Jon Loeliger9553df82007-10-16 15:26:51 -0500310#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
312#define CONFIG_SYS_SCSI_MAX_LUN 1
313#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
314#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger9553df82007-10-16 15:26:51 -0500315#endif
316
317#endif /* CONFIG_PCI */
318
319/*
320 * BAT0 2G Cacheable, non-guarded
321 * 0x0000_0000 2G DDR
322 */
Timur Tabi9ff32d82010-03-29 12:51:07 -0500323#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
324#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
Jon Loeliger9553df82007-10-16 15:26:51 -0500325
326/*
327 * BAT1 1G Cache-inhibited, guarded
328 * 0x8000_0000 256M PCI-1 Memory
329 * 0xa000_0000 256M PCI-Express 1 Memory
330 * 0x9000_0000 256M PCI-Express 2 Memory
331 */
332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500334 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600335#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
337#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Jon Loeliger9553df82007-10-16 15:26:51 -0500338
339/*
Jason Jinf3bceaa2007-10-26 18:31:59 +0800340 * BAT2 16M Cache-inhibited, guarded
Jon Loeliger9553df82007-10-16 15:26:51 -0500341 * 0xe100_0000 1M PCI-1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500342 */
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500345 | BATL_GUARDEDSTORAGE)
Becky Bruce3e3fffe2008-12-03 22:36:44 -0600346#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
348#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Jon Loeliger9553df82007-10-16 15:26:51 -0500349
350/*
Becky Bruce104992f2008-11-02 18:19:32 -0600351 * BAT3 4M Cache-inhibited, guarded
352 * 0xe000_0000 4M CCSR
353 */
354
355#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
356 | BATL_GUARDEDSTORAGE)
357#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
358#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
359#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
360
Jon Loeligerf6987382008-11-20 14:02:56 -0600361#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
362#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
363 | BATL_PP_RW | BATL_CACHEINHIBIT \
364 | BATL_GUARDEDSTORAGE)
365#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
366 | BATU_BL_1M | BATU_VS | BATU_VP)
367#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
368 | BATL_PP_RW | BATL_CACHEINHIBIT)
369#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
370#endif
371
Becky Bruce104992f2008-11-02 18:19:32 -0600372/*
373 * BAT4 32M Cache-inhibited, guarded
Jason Jinf3bceaa2007-10-26 18:31:59 +0800374 * 0xe200_0000 1M PCI-Express 2 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500375 * 0xe300_0000 1M PCI-Express 1 I/O
Jon Loeliger9553df82007-10-16 15:26:51 -0500376 */
377
Becky Bruce104992f2008-11-02 18:19:32 -0600378#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500379 | BATL_GUARDEDSTORAGE)
Becky Bruce104992f2008-11-02 18:19:32 -0600380#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
381#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeliger9553df82007-10-16 15:26:51 -0500383
384/*
385 * BAT5 128K Cacheable, non-guarded
386 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory)
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
389#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
390#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
391#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeliger9553df82007-10-16 15:26:51 -0500392
393/*
394 * BAT6 256M Cache-inhibited, guarded
395 * 0xf000_0000 256M FLASH
396 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500398 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
400#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
401#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeliger9553df82007-10-16 15:26:51 -0500402
Becky Brucebf9a8c32008-11-05 14:55:35 -0600403/* Map the last 1M of flash where we're running from reset */
404#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
405 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200406#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600407#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
408 | BATL_MEMCOHERENCE)
409#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
410
Jon Loeliger9553df82007-10-16 15:26:51 -0500411/*
412 * BAT7 4M Cache-inhibited, guarded
413 * 0xe800_0000 4M PIXIS
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
Jon Loeliger9553df82007-10-16 15:26:51 -0500416 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
418#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
419#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
Jon Loeliger9553df82007-10-16 15:26:51 -0500420
Jon Loeliger9553df82007-10-16 15:26:51 -0500421/*
422 * Environment
423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200425#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200427#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
428#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500429#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200430#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200432#define CONFIG_ENV_SIZE 0x2000
Jon Loeliger9553df82007-10-16 15:26:51 -0500433#endif
434
435#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger9553df82007-10-16 15:26:51 -0500437
Jon Loeliger9553df82007-10-16 15:26:51 -0500438/*
439 * BOOTP options
440 */
441#define CONFIG_BOOTP_BOOTFILESIZE
442#define CONFIG_BOOTP_BOOTPATH
443#define CONFIG_BOOTP_GATEWAY
444#define CONFIG_BOOTP_HOSTNAME
445
Jon Loeliger9553df82007-10-16 15:26:51 -0500446/*
447 * Command line configuration.
448 */
Jon Loeliger9553df82007-10-16 15:26:51 -0500449
Jon Loeliger9553df82007-10-16 15:26:51 -0500450#if defined(CONFIG_PCI)
451#define CONFIG_CMD_PCI
452#define CONFIG_CMD_SCSI
Jon Loeliger9553df82007-10-16 15:26:51 -0500453#endif
454
Jason Jin3473ab72008-05-13 11:50:36 +0800455#define CONFIG_WATCHDOG /* watchdog enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
Jon Loeliger9553df82007-10-16 15:26:51 -0500457
458/*
459 * Miscellaneous configurable options
460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_LONGHELP /* undef to save memory */
Timur Tabi6bee7642008-01-16 15:48:12 -0600462#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger9553df82007-10-16 15:26:51 -0500464
465#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500467#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500469#endif
470
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
472#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
473#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger9553df82007-10-16 15:26:51 -0500474
475/*
476 * For booting Linux, the board info and command line data
477 * have to be in the first 8 MB of memory, since this is
478 * the maximum mapped by the Linux kernel during initialization.
479 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeliger9553df82007-10-16 15:26:51 -0500481
Jon Loeliger9553df82007-10-16 15:26:51 -0500482#if defined(CONFIG_CMD_KGDB)
483#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger9553df82007-10-16 15:26:51 -0500484#endif
485
486/*
487 * Environment Configuration
488 */
489#define CONFIG_IPADDR 192.168.1.100
490
491#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000492#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000493#define CONFIG_BOOTFILE "uImage"
Jon Loeliger9553df82007-10-16 15:26:51 -0500494#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
495
496#define CONFIG_SERVERIP 192.168.1.1
497#define CONFIG_GATEWAYIP 192.168.1.1
498#define CONFIG_NETMASK 255.255.255.0
499
500/* default location for tftp and bootm */
501#define CONFIG_LOADADDR 1000000
502
503#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
504#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
505
506#define CONFIG_BAUDRATE 115200
507
508#if defined(CONFIG_PCI1)
509#define PCI_ENV \
510 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
511 "echo e;md ${a}e00 9\0" \
512 "pci1regs=setenv a e0008; run pcireg\0" \
513 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
514 "pci d.w $b.0 56 1\0" \
515 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
516 "pci w.w $b.0 56 ffff\0" \
517 "pci1err=setenv a e0008; run pcierr\0" \
518 "pci1errc=setenv a e0008; run pcierrc\0"
519#else
520#define PCI_ENV ""
521#endif
522
523#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
524#define PCIE_ENV \
525 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
526 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
527 "pcie1regs=setenv a e000a; run pciereg\0" \
528 "pcie2regs=setenv a e0009; run pciereg\0" \
529 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
530 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
531 "pci d $b.0 130 1\0" \
532 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
533 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
534 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
535 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
536 "pcie1err=setenv a e000a; run pcieerr\0" \
537 "pcie2err=setenv a e0009; run pcieerr\0" \
538 "pcie1errc=setenv a e000a; run pcieerrc\0" \
539 "pcie2errc=setenv a e0009; run pcieerrc\0"
540#else
541#define PCIE_ENV ""
542#endif
543
544#define DMA_ENV \
545 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
546 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
547 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
548 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
549 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
550 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
551 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
552 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
553
York Sun18153382007-10-29 13:57:53 -0500554#ifdef ENV_DEBUG
Jon Loeliger9553df82007-10-16 15:26:51 -0500555#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200556"netdev=eth0\0" \
557"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
558"tftpflash=tftpboot $loadaddr $uboot; " \
559 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
560 " +$filesize; " \
561 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
562 " +$filesize; " \
563 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
564 " $filesize; " \
565 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
566 " +$filesize; " \
567 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
568 " $filesize\0" \
569"consoledev=ttyS0\0" \
570"ramdiskaddr=2000000\0" \
571"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
572"fdtaddr=c00000\0" \
573"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
574"bdev=sda3\0" \
575"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
576"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
577"maxcpus=1" \
578"eoi=mw e00400b0 0\0" \
579"iack=md e00400a0 1\0" \
580"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500581 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
582 "md ${a}f00 5\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200583"ddr1regs=setenv a e0002; run ddrreg\0" \
584"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500585 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
586 "md ${a}e60 1; md ${a}ef0 1d\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200587"guregs=setenv a e00e0; run gureg\0" \
588"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
589"mcmregs=setenv a e0001; run mcmreg\0" \
590"diuregs=md e002c000 1d\0" \
591"dium=mw e002c01c\0" \
592"diuerr=md e002c014 1\0" \
593"pmregs=md e00e1000 2b\0" \
594"lawregs=md e0000c08 4b\0" \
595"lbcregs=md e0005000 36\0" \
596"dma0regs=md e0021100 12\0" \
597"dma1regs=md e0021180 12\0" \
598"dma2regs=md e0021200 12\0" \
599"dma3regs=md e0021280 12\0" \
Jon Loeliger9553df82007-10-16 15:26:51 -0500600 PCI_ENV \
601 PCIE_ENV \
602 DMA_ENV
York Sun18153382007-10-29 13:57:53 -0500603#else
Marek Vasut5368c552012-09-23 17:41:24 +0200604#define CONFIG_EXTRA_ENV_SETTINGS \
605 "netdev=eth0\0" \
606 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
607 "consoledev=ttyS0\0" \
608 "ramdiskaddr=2000000\0" \
609 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
610 "fdtaddr=c00000\0" \
611 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
612 "bdev=sda3\0"
York Sun18153382007-10-29 13:57:53 -0500613#endif
Jon Loeliger9553df82007-10-16 15:26:51 -0500614
615#define CONFIG_NFSBOOTCOMMAND \
616 "setenv bootargs root=/dev/nfs rw " \
617 "nfsroot=$serverip:$rootpath " \
618 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600621 "tftp $fdtaddr $fdtfile;" \
622 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500623
624#define CONFIG_RAMBOOTCOMMAND \
625 "setenv bootargs root=/dev/ram rw " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $ramdiskaddr $ramdiskfile;" \
628 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600629 "tftp $fdtaddr $fdtfile;" \
630 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500631
632#define CONFIG_BOOTCOMMAND \
633 "setenv bootargs root=/dev/$bdev rw " \
634 "console=$consoledev,$baudrate $othbootargs;" \
635 "tftp $loadaddr $bootfile;" \
Jon Loeliger1df170f2008-01-04 12:07:27 -0600636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr - $fdtaddr"
Jon Loeliger9553df82007-10-16 15:26:51 -0500638
639#endif /* __CONFIG_H */