blob: ac78d481d68ce2980b652fc2b8ee3e00837e40e4 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8560ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000022#define CONFIG_BOOKE 1 /* BOOKE */
23#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050024#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000025#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050026#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028/*
29 * default CCARBAR is at 0xff700000
30 * assume U-Boot is less than 0.5MB
31 */
32#define CONFIG_SYS_TEXT_BASE 0xfff80000
33
wdenk0ac6f8b2004-07-09 23:27:13 +000034#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000035#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050036#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050038#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000039#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060040#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyser004eca02009-09-16 22:03:08 -050041#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000042
wdenk0ac6f8b2004-07-09 23:27:13 +000043/*
44 * sysclk for MPC85xx
45 *
46 * Two valid values are:
47 * 33000000
48 * 66000000
49 *
50 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000051 * is likely the desired value here, so that is now the default.
52 * The board, however, can run at 66MHz. In any event, this value
53 * must match the settings of some switches. Details can be found
54 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000055 */
56
wdenk9aea9532004-08-01 23:02:45 +000057#ifndef CONFIG_SYS_CLK_FREQ
58#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000059#endif
60
wdenk9aea9532004-08-01 23:02:45 +000061
wdenk0ac6f8b2004-07-09 23:27:13 +000062/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
65#define CONFIG_L2_CACHE /* toggle L2 cache */
66#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
71#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000072
Timur Tabie46fedf2011-08-04 18:03:41 -050073#define CONFIG_SYS_CCSRBAR 0xe0000000
74#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000075
Jon Loeliger8b625112008-03-18 11:12:44 -050076/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070077#define CONFIG_SYS_FSL_DDR1
Jon Loeliger8b625112008-03-18 11:12:44 -050078#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
79#define CONFIG_DDR_SPD
80#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000081
Jon Loeliger8b625112008-03-18 11:12:44 -050082#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
85#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000086
Jon Loeliger8b625112008-03-18 11:12:44 -050087#define CONFIG_NUM_DDR_CONTROLLERS 1
88#define CONFIG_DIMM_SLOTS_PER_CTLR 1
89#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000090
Jon Loeliger8b625112008-03-18 11:12:44 -050091/* I2C addresses of SPD EEPROMs */
92#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000093
Jon Loeliger8b625112008-03-18 11:12:44 -050094/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
96#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
97#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
98#define CONFIG_SYS_DDR_TIMING_1 0x37344321
99#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
100#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
101#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
102#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000103
wdenk0ac6f8b2004-07-09 23:27:13 +0000104/*
105 * SDRAM on the Local Bus
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
108#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
111#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
114#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
115#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
116#undef CONFIG_SYS_FLASH_CHECKSUM
117#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
118#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000119
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200120#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
123#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000124#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000126#endif
127
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200128#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_CFI
130#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000131
132#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000133
wdenk42d1f032003-10-15 23:53:47 +0000134
wdenk0ac6f8b2004-07-09 23:27:13 +0000135/*
136 * Local Bus Definitions
137 */
138
139/*
140 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000142 *
143 * For BR2, need:
144 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
145 * port-size = 32-bits = BR2[19:20] = 11
146 * no parity checking = BR2[21:22] = 00
147 * SDRAM for MSEL = BR2[24:26] = 011
148 * Valid = BR[31] = 1
149 *
150 * 0 4 8 12 16 20 24 28
151 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
152 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000154 * FIXME: the top 17 bits of BR2.
155 */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000158
159/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000161 *
162 * For OR2, need:
163 * 64MB mask for AM, OR2[0:7] = 1111 1100
164 * XAM, OR2[17:18] = 11
165 * 9 columns OR2[19-21] = 010
166 * 13 rows OR2[23-25] = 100
167 * EAD set for extra time OR[31] = 1
168 *
169 * 0 4 8 12 16 20 24 28
170 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
171 */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
176#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
177#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
178#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000179
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500180#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
181 | LSDMR_RFCR5 \
182 | LSDMR_PRETOACT3 \
183 | LSDMR_ACTTORW3 \
184 | LSDMR_BL8 \
185 | LSDMR_WRC2 \
186 | LSDMR_CL3 \
187 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000188 )
189
190/*
191 * SDRAM Controller configuration sequence.
192 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500193#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
194#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
195#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
196#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
197#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000198
wdenk42d1f032003-10-15 23:53:47 +0000199
wdenk9aea9532004-08-01 23:02:45 +0000200/*
201 * 32KB, 8-bit wide for ADS config reg
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_BR4_PRELIM 0xf8000801
204#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
205#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_RAM_LOCK 1
208#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200209#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000210
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200211#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
215#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000216
217/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000218#define CONFIG_CONS_ON_SCC /* define if console on SCC */
219#undef CONFIG_CONS_NONE /* define if console on something else */
220#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000221
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200222#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
226
227/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_HUSH_PARSER
229#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000230#endif
231
Matthew McClintock0e163872006-06-28 10:43:36 -0500232/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600233#define CONFIG_OF_LIBFDT 1
234#define CONFIG_OF_BOARD_SETUP 1
235#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500236
Jon Loeliger20476722006-10-20 15:50:15 -0500237/*
238 * I2C
239 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200240#define CONFIG_SYS_I2C
241#define CONFIG_SYS_I2C_FSL
242#define CONFIG_SYS_FSL_I2C_SPEED 400000
243#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
244#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
245#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000246
wdenk0ac6f8b2004-07-09 23:27:13 +0000247/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600248#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600249#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600250#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000252
wdenk0ac6f8b2004-07-09 23:27:13 +0000253/*
254 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300255 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000256 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600257#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600258#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600261#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600262#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
264#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000265
266#if defined(CONFIG_PCI)
267
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200268#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000269
270#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000271#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000272
273#if !defined(CONFIG_PCI_PNP)
274 #define PCI_ENET0_IOADDR 0xe0000000
275 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200276 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000277#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000278
279#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000281
282#endif /* CONFIG_PCI */
283
284
Andy Flemingccc091a2007-05-08 17:27:43 -0500285#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000286
Andy Flemingccc091a2007-05-08 17:27:43 -0500287#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000288#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500289#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500290#define CONFIG_TSEC1 1
291#define CONFIG_TSEC1_NAME "TSEC0"
292#define CONFIG_TSEC2 1
293#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000294#define TSEC1_PHY_ADDR 0
295#define TSEC2_PHY_ADDR 1
296#define TSEC1_PHYIDX 0
297#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500298#define TSEC1_FLAGS TSEC_GIGABIT
299#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500300
301/* Options are: TSEC[0-1] */
302#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000303
Andy Flemingccc091a2007-05-08 17:27:43 -0500304#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000305
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200306#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500307
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200308#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000309#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
310
311#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000312 /*
313 * - Rx-CLK is CLK13
314 * - Tx-CLK is CLK14
315 * - Select bus for bd/buffers
316 * - Full duplex
317 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000318 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
319 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
321 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000322 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000323#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000324 /* need more definitions here for FE3 */
325 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200326#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000327
Andy Flemingccc091a2007-05-08 17:27:43 -0500328#ifndef CONFIG_MII
329#define CONFIG_MII 1 /* MII PHY management */
330#endif
331
wdenk0ac6f8b2004-07-09 23:27:13 +0000332#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
333
wdenk42d1f032003-10-15 23:53:47 +0000334/*
335 * GPIO pins used for bit-banged MII communications
336 */
337#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200338#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
339 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
340#define MDC_DECLARE MDIO_DECLARE
341
wdenk42d1f032003-10-15 23:53:47 +0000342#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
343#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
344#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
345
346#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
347 else iop->pdat &= ~0x00400000
348
349#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
350 else iop->pdat &= ~0x00200000
351
352#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000353
wdenk42d1f032003-10-15 23:53:47 +0000354#endif
355
wdenk0ac6f8b2004-07-09 23:27:13 +0000356
357/*
358 * Environment
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200361 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200363 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
364 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000365#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200367 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200369 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000370#endif
371
wdenk0ac6f8b2004-07-09 23:27:13 +0000372#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000374
Jon Loeliger2835e512007-06-13 13:22:08 -0500375/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500376 * BOOTP options
377 */
378#define CONFIG_BOOTP_BOOTFILESIZE
379#define CONFIG_BOOTP_BOOTPATH
380#define CONFIG_BOOTP_GATEWAY
381#define CONFIG_BOOTP_HOSTNAME
382
383
384/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500385 * Command line configuration.
386 */
387#include <config_cmd_default.h>
388
389#define CONFIG_CMD_PING
390#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600391#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500392#define CONFIG_CMD_IRQ
393#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500394#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500395
396#if defined(CONFIG_PCI)
397 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000398#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000399
Jon Loeliger2835e512007-06-13 13:22:08 -0500400#if defined(CONFIG_ETHER_ON_FCC)
401 #define CONFIG_CMD_MII
402#endif
403
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500405 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500406 #undef CONFIG_CMD_LOADS
407#endif
408
wdenk42d1f032003-10-15 23:53:47 +0000409
wdenk0ac6f8b2004-07-09 23:27:13 +0000410#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000411
412/*
413 * Miscellaneous configurable options
414 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500416#define CONFIG_CMDLINE_EDITING /* Command-line editing */
417#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000419
Jon Loeliger2835e512007-06-13 13:22:08 -0500420#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000422#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000424#endif
425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
427#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
428#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000429
430/*
431 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500432 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000433 * the maximum mapped by the Linux kernel during initialization.
434 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500435#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
436#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000437
Jon Loeliger2835e512007-06-13 13:22:08 -0500438#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000439#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk42d1f032003-10-15 23:53:47 +0000440#endif
441
wdenk9aea9532004-08-01 23:02:45 +0000442
443/*
444 * Environment Configuration
445 */
446
wdenk0ac6f8b2004-07-09 23:27:13 +0000447/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000448#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500449#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000450#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000451#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000452#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000453#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000454#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Gala5ce71582007-11-28 22:40:31 -0600455#define CONFIG_HAS_ETH3
456#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk42d1f032003-10-15 23:53:47 +0000457#endif
458
wdenk0ac6f8b2004-07-09 23:27:13 +0000459#define CONFIG_IPADDR 192.168.1.253
460
461#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000462#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000463#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000464
465#define CONFIG_SERVERIP 192.168.1.1
466#define CONFIG_GATEWAYIP 192.168.1.1
467#define CONFIG_NETMASK 255.255.255.0
468
469#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
470
wdenk9aea9532004-08-01 23:02:45 +0000471#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000472#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
473
474#define CONFIG_BAUDRATE 115200
475
wdenk9aea9532004-08-01 23:02:45 +0000476#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500477 "netdev=eth0\0" \
478 "consoledev=ttyCPM\0" \
479 "ramdiskaddr=1000000\0" \
480 "ramdiskfile=your.ramdisk.u-boot\0" \
481 "fdtaddr=400000\0" \
482 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000483
wdenk9aea9532004-08-01 23:02:45 +0000484#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500485 "setenv bootargs root=/dev/nfs rw " \
486 "nfsroot=$serverip:$rootpath " \
487 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
488 "console=$consoledev,$baudrate $othbootargs;" \
489 "tftp $loadaddr $bootfile;" \
490 "tftp $fdtaddr $fdtfile;" \
491 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000492
493#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500494 "setenv bootargs root=/dev/ram rw " \
495 "console=$consoledev,$baudrate $othbootargs;" \
496 "tftp $ramdiskaddr $ramdiskfile;" \
497 "tftp $loadaddr $bootfile;" \
498 "tftp $fdtaddr $fdtfile;" \
499 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000500
501#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000502
503#endif /* __CONFIG_H */