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wdenk0db5bca2003-03-31 17:27:09 +00001/*
2 * (C) Copyright 2003
3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
wdenk8bde7f72003-06-27 21:31:46 +000020 * Foundation,
wdenk0db5bca2003-03-31 17:27:09 +000021 */
22
23/*
24 * File: cmi_mpc5xx.h
wdenk8bde7f72003-06-27 21:31:46 +000025 *
26 * Discription: Config header file for cmi
wdenk0db5bca2003-03-31 17:27:09 +000027 * board using an MPC5xx CPU
28 *
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 */
37
38#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
39#define CONFIG_CMI 1 /* Using the customized cmi board */
40
41/* Serial Console Configuration */
42#define CONFIG_5xx_CONS_SCI1
43#undef CONFIG_5xx_CONS_SCI2
44
45#define CONFIG_BAUDRATE 57600
46
wdenk0db5bca2003-03-31 17:27:09 +000047
Jon Loeligerb730cda2007-07-04 22:31:35 -050048/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050049 * BOOTP options
50 */
51#define CONFIG_BOOTP_BOOTFILESIZE
52#define CONFIG_BOOTP_BOOTPATH
53#define CONFIG_BOOTP_GATEWAY
54#define CONFIG_BOOTP_HOSTNAME
55
56
57/*
Jon Loeligerb730cda2007-07-04 22:31:35 -050058 * Command line configuration.
59 */
60#include <config_cmd_default.h>
61
Wolfgang Denk2d1f23a2007-08-29 13:35:03 +020062#undef CONFIG_CMD_NET /* disabeled - causes compile errors */
63
Jon Loeligerb730cda2007-07-04 22:31:35 -050064#define CONFIG_CMD_MEMORY
65#define CONFIG_CMD_LOADB
66#define CONFIG_CMD_REGINFO
67#define CONFIG_CMD_FLASH
68#define CONFIG_CMD_LOADS
69#define CONFIG_CMD_ASKENV
70#define CONFIG_CMD_BDI
71#define CONFIG_CMD_CONSOLE
72#define CONFIG_CMD_ENV
73#define CONFIG_CMD_RUN
74#define CONFIG_CMD_IMI
75
wdenk0db5bca2003-03-31 17:27:09 +000076
77#if 0
78#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
79#else
80#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
81#endif
82#define CONFIG_BOOTCOMMAND "go 02034004" /* autoboot command */
83
84#define CONFIG_BOOTARGS "" /* Assuming OS Image in 4 flash sector at offset 4004 */
85
86#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
87
wdenk8bde7f72003-06-27 21:31:46 +000088#define CONFIG_STATUS_LED 1 /* Enable status led */
wdenk0db5bca2003-03-31 17:27:09 +000089
90#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
91
92/*
wdenk8bde7f72003-06-27 21:31:46 +000093 * Miscellaneous configurable options
wdenk0db5bca2003-03-31 17:27:09 +000094 */
95
96#define CFG_LONGHELP /* undef to save memory */
97#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerb730cda2007-07-04 22:31:35 -050098#if defined(CONFIG_CMD_KGDB)
wdenk0db5bca2003-03-31 17:27:09 +000099#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
100#else
101#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
102#endif
103#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
104#define CFG_MAXARGS 16 /* max number of command args */
105#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
106
107#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
108#define CFG_MEMTEST_END 0x000fa000 /* 1 MB in SRAM */
109
110#define CFG_LOAD_ADDR 0x100000 /* default load address */
111
112#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
113
114#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
115
116
117/*
118 * Low Level Configuration Settings
119 */
120
121/*
122 * Internal Memory Mapped (This is not the IMMR content)
123 */
124#define CFG_IMMR 0x01000000 /* Physical start adress of internal memory map */
125
126/*
127 * Definitions for initial stack pointer and data area
128 */
wdenk8bde7f72003-06-27 21:31:46 +0000129#define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
wdenk0db5bca2003-03-31 17:27:09 +0000130#define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
131#define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
132#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset from the beginning of ram */
133#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
134
135/*
136 * Start addresses for the final memory configuration
137 * Please note that CFG_SDRAM_BASE _must_ start at 0
138 */
139#define CFG_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
140#define CFG_FLASH_BASE 0x02000000 /* External flash */
141#define PLD_BASE 0x03000000 /* PLD */
142#define ANYBUS_BASE 0x03010000 /* Anybus Module */
143
144#define CFG_RESET_ADRESS 0x01000000 /* Adress which causes reset */
145#define CFG_MONITOR_BASE CFG_FLASH_BASE /* TEXT_BASE is defined in the board config.mk file. */
146 /* This adress is given to the linker with -Ttext to */
147 /* locate the text section at this adress. */
148#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
149#define CFG_MALLOC_LEN (64 << 10) /* Reserve 128 kB for malloc() */
150
151/*
152 * For booting Linux, the board info and command line data
153 * have to be in the first 8 MB of memory, since this is
154 * the maximum mapped by the Linux kernel during initialization.
155 */
156#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
157
158
159/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000160 * FLASH organization
wdenk0db5bca2003-03-31 17:27:09 +0000161 *-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000162 *
wdenk0db5bca2003-03-31 17:27:09 +0000163 */
164
165#define CFG_MAX_FLASH_BANKS 1 /* Max number of memory banks */
166#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors on one chip */
167#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
168#define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
169#define CFG_FLASH_PROTECTION 1 /* Physically section protection on */
170
171#define CFG_ENV_IS_IN_FLASH 1
172
173#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk67c31032007-09-16 17:10:04 +0200174#define CFG_ENV_OFFSET 0x00020000 /* Environment starts at this adress */
175#define CFG_ENV_SIZE 0x00010000 /* Set whole sector as env */
176#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk0db5bca2003-03-31 17:27:09 +0000177#endif
178
179/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000180 * SYPCR - System Protection Control
wdenk0db5bca2003-03-31 17:27:09 +0000181 * SYPCR can only be written once after reset!
182 *-----------------------------------------------------------------------
183 * SW Watchdog freeze
184 */
185#if defined(CONFIG_WATCHDOG)
186#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
187 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
188#else
189#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000190 SYPCR_SWP)
wdenk0db5bca2003-03-31 17:27:09 +0000191#endif /* CONFIG_WATCHDOG */
192
193/*-----------------------------------------------------------------------
194 * TBSCR - Time Base Status and Control
195 *-----------------------------------------------------------------------
196 * Clear Reference Interrupt Status, Timebase freezing enabled
197 */
198#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
199
200/*-----------------------------------------------------------------------
201 * PISCR - Periodic Interrupt Status and Control
202 *-----------------------------------------------------------------------
203 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
204 */
205#define CFG_PISCR (PISCR_PITF)
206
207/*-----------------------------------------------------------------------
208 * SCCR - System Clock and reset Control Register
209 *-----------------------------------------------------------------------
210 * Set clock output, timebase and RTC source and divider,
211 * power management and some other internal clocks
212 */
213#define SCCR_MASK SCCR_EBDF00
214#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
215 SCCR_COM00 | SCCR_DFNL000 | SCCR_DFNH000)
216
217/*-----------------------------------------------------------------------
218 * SIUMCR - SIU Module Configuration
219 *-----------------------------------------------------------------------
220 * Data show cycle
221 */
222#define CFG_SIUMCR (SIUMCR_DBGC00) /* Disable data show cycle */
223
224/*-----------------------------------------------------------------------
225 * PLPRCR - PLL, Low-Power, and Reset Control Register
226 *-----------------------------------------------------------------------
227 * Set all bits to 40 Mhz
wdenk8bde7f72003-06-27 21:31:46 +0000228 *
wdenk0db5bca2003-03-31 17:27:09 +0000229 */
230#define CFG_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
231#define CFG_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
wdenk8bde7f72003-06-27 21:31:46 +0000232
wdenk0db5bca2003-03-31 17:27:09 +0000233
234/*-----------------------------------------------------------------------
235 * UMCR - UIMB Module Configuration Register
236 *-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000237 *
wdenk0db5bca2003-03-31 17:27:09 +0000238 */
239#define CFG_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
240
241/*-----------------------------------------------------------------------
242 * ICTRL - I-Bus Support Control Register
243 */
wdenk8bde7f72003-06-27 21:31:46 +0000244#define CFG_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
wdenk0db5bca2003-03-31 17:27:09 +0000245
246/*-----------------------------------------------------------------------
247 * USIU - Memory Controller Register
wdenk8bde7f72003-06-27 21:31:46 +0000248 *-----------------------------------------------------------------------
wdenk0db5bca2003-03-31 17:27:09 +0000249 */
250
wdenk8bde7f72003-06-27 21:31:46 +0000251#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
wdenk0db5bca2003-03-31 17:27:09 +0000252#define CFG_OR0_PRELIM (OR_ADDR_MK_FF | OR_SCY_3)
253#define CFG_BR1_PRELIM (ANYBUS_BASE)
254#define CFG_OR1_PRELIM (OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
255#define CFG_BR2_PRELIM (CFG_SDRAM_BASE | BR_V | BR_PS_32)
256#define CFG_OR2_PRELIM (OR_ADDR_MK_FF)
257#define CFG_BR3_PRELIM (PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
258#define CFG_OR3_PRELIM (OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
259 OR_ACS_10 | OR_ETHR | OR_CSNT)
260
261#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* We don't realign the flash */
262
263/*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000264 * DER - Timer Decrementer
wdenk0db5bca2003-03-31 17:27:09 +0000265 *-----------------------------------------------------------------------
266 * Initialise to zero
267 */
268#define CFG_DER 0x00000000
269
270
271/*
272 * Internal Definitions
273 *
274 * Boot Flags
275 */
276#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
277#define BOOTFLAG_WARM 0x02 /* Software reboot */
278
279#endif /* __CONFIG_H */