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wdenk2d5b5612003-10-14 19:43:55 +00001/*
2 * (C) Copyright 2003
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * Configuation settings for the IXDP425 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
34#define CONFIG_IXDP425 1 /* on an IXDP425 Board */
35
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020036#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
37#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
38
wdenk2d5b5612003-10-14 19:43:55 +000039/***************************************************************
40 * U-boot generic defines start here.
41 ***************************************************************/
42
wdenk2d5b5612003-10-14 19:43:55 +000043#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45/*
46 * Size of malloc() pool
47 */
48#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenkf6e20fc2004-02-08 19:38:38 +000049#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk2d5b5612003-10-14 19:43:55 +000050
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53
54#define CONFIG_BAUDRATE 115200
55
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050056
57/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050058 * BOOTP options
59 */
60#define CONFIG_BOOTP_BOOTFILESIZE
61#define CONFIG_BOOTP_BOOTPATH
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64
65
66/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050067 * Command line configuration.
68 */
69#include <config_cmd_default.h>
70
71#define CONFIG_CMD_ELF
72#define CONFIG_CMD_PCI
73
wdenk2d5b5612003-10-14 19:43:55 +000074
wdenka1191902005-01-09 17:12:27 +000075#define CONFIG_PCI
76#define CONFIG_NET_MULTI
77#define CONFIG_EEPRO100
wdenk2d5b5612003-10-14 19:43:55 +000078
79#define CONFIG_BOOTDELAY 3
wdenka1191902005-01-09 17:12:27 +000080/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/
81#define CONFIG_NETMASK 255.255.255.0
wdenk2d5b5612003-10-14 19:43:55 +000082#define CONFIG_IPADDR 192.168.0.21
wdenka1191902005-01-09 17:12:27 +000083#define CONFIG_SERVERIP 192.168.0.148
wdenk2d5b5612003-10-14 19:43:55 +000084#define CONFIG_BOOTCOMMAND "bootm 50040000"
85#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
wdenk42d1f032003-10-15 23:53:47 +000086#define CONFIG_CMDLINE_TAG
wdenk2d5b5612003-10-14 19:43:55 +000087
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050088#if defined(CONFIG_CMD_KGDB)
wdenk2d5b5612003-10-14 19:43:55 +000089#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
90#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
91#endif
92
93/*
94 * Miscellaneous configurable options
95 */
96#define CFG_LONGHELP /* undef to save memory */
97#define CFG_PROMPT "=> " /* Monitor Command Prompt */
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
100#define CFG_MAXARGS 16 /* max number of command args */
101#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
102
103#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
104#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
105
106#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
107
108#define CFG_LOAD_ADDR 0x00010000 /* default load address */
109
110#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */
wdenk42d1f032003-10-15 23:53:47 +0000111 /* valid baudrates */
wdenk2d5b5612003-10-14 19:43:55 +0000112#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
113
114/*
115 * Stack sizes
116 *
117 * The stack sizes are set up in start.S using the settings below
118 */
119#define CONFIG_STACKSIZE (128*1024) /* regular stack */
120#ifdef CONFIG_USE_IRQ
121#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
122#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
123#endif
124
125/***************************************************************
126 * Platform/Board specific defines start here.
127 ***************************************************************/
128
129/*
130 * Hardware drivers
131 */
132
133
134/*
135 * select serial console configuration
136 */
137#define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
138
139/*
140 * Physical Memory Map
141 */
142#define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */
143#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
144#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
145
146#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
147#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
148#define PHYS_FLASH_BANK_SIZE 0x00800000 /* 8 MB Banks */
149#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
150
151#define CFG_DRAM_BASE 0x00000000
152#define CFG_DRAM_SIZE 0x01000000
153
154#define CFG_FLASH_BASE PHYS_FLASH_1
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200155#define CFG_MONITOR_BASE CFG_FLASH_BASE
156#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk2d5b5612003-10-14 19:43:55 +0000157
158/*
159 * Expansion bus settings
160 */
161#define CFG_EXP_CS0 0xbcd23c42
162
163/*
164 * SDRAM settings
165 */
wdenka1191902005-01-09 17:12:27 +0000166#define CFG_SDR_CONFIG 0xd
167#define CFG_SDR_MODE_CONFIG 0x1
wdenk2d5b5612003-10-14 19:43:55 +0000168#define CFG_SDRAM_REFRESH_CNT 0x81a
169
170/*
171 * GPIO settings
172 */
173
174/*
175 * FLASH and environment organization
176 */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200177/*
178 * FLASH and environment organization
179 */
wdenk2d5b5612003-10-14 19:43:55 +0000180#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200181#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenk2d5b5612003-10-14 19:43:55 +0000182
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200183#define CFG_FLASH_CFI /* The flash is CFI compatible */
184#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
185#define CFG_ENV_IS_IN_FLASH 1
wdenk2d5b5612003-10-14 19:43:55 +0000186
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200187#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
188
189#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
190
191#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
192#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
193
194#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
195
196#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
197#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000)
198#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
wdenk2d5b5612003-10-14 19:43:55 +0000199
200#endif /* __CONFIG_H */