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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkad5bb452007-03-06 18:08:43 +01005 */
6
7#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Simon Glass401d1c42020-10-30 21:38:53 -06009#include <asm/global_data.h>
Wolfgang Denkad5bb452007-03-06 18:08:43 +010010
11/* Memory test
12 *
13 * General observations:
14 * o The recommended test sequence is to test the data lines: if they are
15 * broken, nothing else will work properly. Then test the address
16 * lines. Finally, test the cells in the memory now that the test
17 * program knows that the address and data lines work properly.
18 * This sequence also helps isolate and identify what is faulty.
19 *
20 * o For the address line test, it is a good idea to use the base
21 * address of the lowest memory location, which causes a '1' bit to
22 * walk through a field of zeros on the address lines and the highest
23 * memory location, which causes a '0' bit to walk through a field of
24 * '1's on the address line.
25 *
26 * o Floating buses can fool memory tests if the test routine writes
27 * a value and then reads it back immediately. The problem is, the
28 * write will charge the residual capacitance on the data bus so the
29 * bus retains its state briefely. When the test program reads the
30 * value back immediately, the capacitance of the bus can allow it
31 * to read back what was written, even though the memory circuitry
32 * is broken. To avoid this, the test program should write a test
33 * pattern to the target location, write a different pattern elsewhere
34 * to charge the residual capacitance in a differnt manner, then read
35 * the target location back.
36 *
37 * o Always read the target location EXACTLY ONCE and save it in a local
38 * variable. The problem with reading the target location more than
39 * once is that the second and subsequent reads may work properly,
40 * resulting in a failed test that tells the poor technician that
41 * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which
42 * doesn't help him one bit and causes puzzled phone calls. Been there,
43 * done that.
44 *
45 * Data line test:
46 * ---------------
47 * This tests data lines for shorts and opens by forcing adjacent data
48 * to opposite states. Because the data lines could be routed in an
49 * arbitrary manner the must ensure test patterns ensure that every case
50 * is tested. By using the following series of binary patterns every
51 * combination of adjacent bits is test regardless of routing.
52 *
53 * ...101010101010101010101010
54 * ...110011001100110011001100
55 * ...111100001111000011110000
56 * ...111111110000000011111111
57 *
58 * Carrying this out, gives us six hex patterns as follows:
59 *
60 * 0xaaaaaaaaaaaaaaaa
61 * 0xcccccccccccccccc
62 * 0xf0f0f0f0f0f0f0f0
63 * 0xff00ff00ff00ff00
64 * 0xffff0000ffff0000
65 * 0xffffffff00000000
66 *
67 * To test for short and opens to other signals on our boards, we
68 * simply test with the 1's complemnt of the paterns as well, resulting
69 * in twelve patterns total.
70 *
71 * After writing a test pattern. a special pattern 0x0123456789ABCDEF is
72 * written to a different address in case the data lines are floating.
73 * Thus, if a byte lane fails, you will see part of the special
74 * pattern in that byte lane when the test runs. For example, if the
75 * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa
76 * (for the 'a' test pattern).
77 *
78 * Address line test:
79 * ------------------
80 * This function performs a test to verify that all the address lines
81 * hooked up to the RAM work properly. If there is an address line
82 * fault, it usually shows up as two different locations in the address
83 * map (related by the faulty address line) mapping to one physical
84 * memory storage location. The artifact that shows up is writing to
85 * the first location "changes" the second location.
86 *
87 * To test all address lines, we start with the given base address and
88 * xor the address with a '1' bit to flip one address line. For each
89 * test, we shift the '1' bit left to test the next address line.
90 *
91 * In the actual code, we start with address sizeof(ulong) since our
92 * test pattern we use is a ulong and thus, if we tried to test lower
93 * order address bits, it wouldn't work because our pattern would
94 * overwrite itself.
95 *
96 * Example for a 4 bit address space with the base at 0000:
97 * 0000 <- base
98 * 0001 <- test 1
99 * 0010 <- test 2
100 * 0100 <- test 3
101 * 1000 <- test 4
102 * Example for a 4 bit address space with the base at 0010:
103 * 0010 <- base
104 * 0011 <- test 1
105 * 0000 <- (below the base address, skipped)
106 * 0110 <- test 2
107 * 1010 <- test 3
108 *
109 * The test locations are successively tested to make sure that they are
110 * not "mirrored" onto the base address due to a faulty address line.
111 * Note that the base and each test location are related by one address
112 * line flipped. Note that the base address need not be all zeros.
113 *
114 * Memory tests 1-4:
115 * -----------------
116 * These tests verify RAM using sequential writes and reads
117 * to/from RAM. There are several test cases that use different patterns to
118 * verify RAM. Each test case fills a region of RAM with one pattern and
119 * then reads the region back and compares its contents with the pattern.
120 * The following patterns are used:
121 *
122 * 1a) zero pattern (0x00000000)
123 * 1b) negative pattern (0xffffffff)
124 * 1c) checkerboard pattern (0x55555555)
125 * 1d) checkerboard pattern (0xaaaaaaaa)
126 * 2) bit-flip pattern ((1 << (offset % 32))
127 * 3) address pattern (offset)
128 * 4) address pattern (~offset)
129 *
130 * Being run in normal mode, the test verifies only small 4Kb
131 * regions of RAM around each 1Mb boundary. For example, for 64Mb
132 * RAM the following areas are verified: 0x00000000-0x00000800,
133 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
134 * 0x04000000. If the test is run in slow-test mode, it verifies
135 * the whole RAM.
136 */
137
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100138#include <post.h>
139#include <watchdog.h>
140
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000141#if CONFIG_POST & (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_MEM_REGIONS)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100142
143DECLARE_GLOBAL_DATA_PTR;
144
145/*
146 * Define INJECT_*_ERRORS for testing error detection in the presence of
147 * _good_ hardware.
148 */
149#undef INJECT_DATA_ERRORS
150#undef INJECT_ADDRESS_ERRORS
151
152#ifdef INJECT_DATA_ERRORS
153#warning "Injecting data line errors for testing purposes"
154#endif
155
156#ifdef INJECT_ADDRESS_ERRORS
157#warning "Injecting address line errors for testing purposes"
158#endif
159
160
161/*
162 * This function performs a double word move from the data at
163 * the source pointer to the location at the destination pointer.
164 * This is helpful for testing memory on processors which have a 64 bit
165 * wide data bus.
166 *
167 * On those PowerPC with FPU, use assembly and a floating point move:
168 * this does a 64 bit move.
169 *
170 * For other processors, let the compiler generate the best code it can.
171 */
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100172static void move64(const unsigned long long *src, unsigned long long *dest)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100173{
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100174 *dest = *src;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100175}
176
177/*
178 * This is 64 bit wide test patterns. Note that they reside in ROM
179 * (which presumably works) and the tests write them to RAM which may
180 * not work.
181 *
182 * The "otherpattern" is written to drive the data bus to values other
183 * than the test pattern. This is for detecting floating bus lines.
184 *
185 */
186const static unsigned long long pattern[] = {
187 0xaaaaaaaaaaaaaaaaULL,
188 0xccccccccccccccccULL,
189 0xf0f0f0f0f0f0f0f0ULL,
190 0xff00ff00ff00ff00ULL,
191 0xffff0000ffff0000ULL,
192 0xffffffff00000000ULL,
193 0x00000000ffffffffULL,
194 0x0000ffff0000ffffULL,
195 0x00ff00ff00ff00ffULL,
196 0x0f0f0f0f0f0f0f0fULL,
197 0x3333333333333333ULL,
198 0x5555555555555555ULL
199};
200const unsigned long long otherpattern = 0x0123456789abcdefULL;
201
202
203static int memory_post_dataline(unsigned long long * pmem)
204{
205 unsigned long long temp64 = 0;
Mike Frysingerd2397812011-05-10 07:28:35 +0000206 int num_patterns = ARRAY_SIZE(pattern);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100207 int i;
208 unsigned int hi, lo, pathi, patlo;
209 int ret = 0;
210
211 for ( i = 0; i < num_patterns; i++) {
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100212 move64(&(pattern[i]), pmem++);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100213 /*
214 * Put a different pattern on the data lines: otherwise they
215 * may float long enough to read back what we wrote.
216 */
Anatolij Gustschin44b4dbe2008-02-25 23:53:07 +0100217 move64(&otherpattern, pmem--);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100218 move64(pmem, &temp64);
219
220#ifdef INJECT_DATA_ERRORS
221 temp64 ^= 0x00008000;
222#endif
223
224 if (temp64 != pattern[i]){
225 pathi = (pattern[i]>>32) & 0xffffffff;
226 patlo = pattern[i] & 0xffffffff;
227
228 hi = (temp64>>32) & 0xffffffff;
229 lo = temp64 & 0xffffffff;
230
Niko Maunoe2ee3012016-11-23 14:52:32 +0200231 post_log("Memory (data line) error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100232 "wrote %08x%08x, read %08x%08x !\n",
233 pmem, pathi, patlo, hi, lo);
234 ret = -1;
235 }
236 }
237 return ret;
238}
239
240static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size)
241{
242 ulong *target;
243 ulong *end;
244 ulong readback;
245 ulong xor;
246 int ret = 0;
247
248 end = (ulong *)((ulong)base + size); /* pointer arith! */
249 xor = 0;
250 for(xor = sizeof(ulong); xor > 0; xor <<= 1) {
251 target = (ulong *)((ulong)testaddr ^ xor);
252 if((target >= base) && (target < end)) {
253 *testaddr = ~*target;
254 readback = *target;
255
256#ifdef INJECT_ADDRESS_ERRORS
257 if(xor == 0x00008000) {
258 readback = *testaddr;
259 }
260#endif
261 if(readback == *testaddr) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000262 post_log("Memory (address line) error at %08x<->%08x, "
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200263 "XOR value %08x !\n",
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100264 testaddr, target, xor);
265 ret = -1;
266 }
267 }
268 }
269 return ret;
270}
271
Valentin Longchampca51d052011-08-03 02:37:03 +0000272static int memory_post_test1(unsigned long start,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100273 unsigned long size,
274 unsigned long val)
275{
276 unsigned long i;
277 ulong *mem = (ulong *) start;
278 ulong readback;
279 int ret = 0;
280
281 for (i = 0; i < size / sizeof (ulong); i++) {
282 mem[i] = val;
283 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000284 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100285 }
286
Valentin Longchampca51d052011-08-03 02:37:03 +0000287 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100288 readback = mem[i];
289 if (readback != val) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000290 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100291 "wrote %08x, read %08x !\n",
292 mem + i, val, readback);
293
294 ret = -1;
295 break;
296 }
297 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000298 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100299 }
300
301 return ret;
302}
303
Valentin Longchampca51d052011-08-03 02:37:03 +0000304static int memory_post_test2(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100305{
306 unsigned long i;
307 ulong *mem = (ulong *) start;
308 ulong readback;
309 int ret = 0;
310
311 for (i = 0; i < size / sizeof (ulong); i++) {
312 mem[i] = 1 << (i % 32);
313 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000314 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100315 }
316
Valentin Longchampca51d052011-08-03 02:37:03 +0000317 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100318 readback = mem[i];
319 if (readback != (1 << (i % 32))) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000320 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100321 "wrote %08x, read %08x !\n",
322 mem + i, 1 << (i % 32), readback);
323
324 ret = -1;
325 break;
326 }
327 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000328 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100329 }
330
331 return ret;
332}
333
Valentin Longchampca51d052011-08-03 02:37:03 +0000334static int memory_post_test3(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100335{
336 unsigned long i;
337 ulong *mem = (ulong *) start;
338 ulong readback;
339 int ret = 0;
340
341 for (i = 0; i < size / sizeof (ulong); i++) {
342 mem[i] = i;
343 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000344 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100345 }
346
Valentin Longchampca51d052011-08-03 02:37:03 +0000347 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100348 readback = mem[i];
349 if (readback != i) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000350 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100351 "wrote %08x, read %08x !\n",
352 mem + i, i, readback);
353
354 ret = -1;
355 break;
356 }
357 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000358 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100359 }
360
361 return ret;
362}
363
Valentin Longchampca51d052011-08-03 02:37:03 +0000364static int memory_post_test4(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100365{
366 unsigned long i;
367 ulong *mem = (ulong *) start;
368 ulong readback;
369 int ret = 0;
370
371 for (i = 0; i < size / sizeof (ulong); i++) {
372 mem[i] = ~i;
373 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000374 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100375 }
376
Valentin Longchampca51d052011-08-03 02:37:03 +0000377 for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100378 readback = mem[i];
379 if (readback != ~i) {
Valentin Longchampca51d052011-08-03 02:37:03 +0000380 post_log("Memory error at %08x, "
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100381 "wrote %08x, read %08x !\n",
382 mem + i, ~i, readback);
383
384 ret = -1;
385 break;
386 }
387 if (i % 1024 == 0)
Valentin Longchampca51d052011-08-03 02:37:03 +0000388 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100389 }
390
391 return ret;
392}
393
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000394static int memory_post_test_lines(unsigned long start, unsigned long size)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100395{
396 int ret = 0;
397
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000398 ret = memory_post_dataline((unsigned long long *)start);
Valentin Longchampca51d052011-08-03 02:37:03 +0000399 WATCHDOG_RESET();
400 if (!ret)
401 ret = memory_post_addrline((ulong *)start, (ulong *)start,
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000402 size);
Valentin Longchampca51d052011-08-03 02:37:03 +0000403 WATCHDOG_RESET();
404 if (!ret)
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000405 ret = memory_post_addrline((ulong *)(start+size-8),
406 (ulong *)start, size);
Valentin Longchampca51d052011-08-03 02:37:03 +0000407 WATCHDOG_RESET();
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000408
409 return ret;
410}
411
412static int memory_post_test_patterns(unsigned long start, unsigned long size)
413{
414 int ret = 0;
415
416 ret = memory_post_test1(start, size, 0x00000000);
Valentin Longchampca51d052011-08-03 02:37:03 +0000417 WATCHDOG_RESET();
418 if (!ret)
419 ret = memory_post_test1(start, size, 0xffffffff);
420 WATCHDOG_RESET();
421 if (!ret)
422 ret = memory_post_test1(start, size, 0x55555555);
423 WATCHDOG_RESET();
424 if (!ret)
425 ret = memory_post_test1(start, size, 0xaaaaaaaa);
426 WATCHDOG_RESET();
427 if (!ret)
428 ret = memory_post_test2(start, size);
429 WATCHDOG_RESET();
430 if (!ret)
431 ret = memory_post_test3(start, size);
432 WATCHDOG_RESET();
433 if (!ret)
434 ret = memory_post_test4(start, size);
435 WATCHDOG_RESET();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100436
437 return ret;
438}
439
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000440static int memory_post_test_regions(unsigned long start, unsigned long size)
441{
442 unsigned long i;
443 int ret = 0;
444
445 for (i = 0; i < (size >> 20) && (!ret); i++) {
446 if (!ret)
Heiko Schocher7b5d61b2011-10-06 20:40:00 +0000447 ret = memory_post_test_patterns(start + (i << 20),
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000448 0x800);
Heiko Schocher7b5d61b2011-10-06 20:40:00 +0000449 if (!ret)
450 ret = memory_post_test_patterns(start + (i << 20) +
451 0xff800, 0x800);
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000452 }
453
454 return ret;
455}
456
457static int memory_post_tests(unsigned long start, unsigned long size)
458{
459 int ret = 0;
460
461 ret = memory_post_test_lines(start, size);
462 if (!ret)
463 ret = memory_post_test_patterns(start, size);
464
465 return ret;
466}
467
Heiko Schocher42042982011-06-02 19:38:24 +0000468/*
469 * !! this is only valid, if you have contiguous memory banks !!
470 */
York Sun28417032010-09-28 15:20:31 -0700471__attribute__((weak))
472int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100473{
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900474 struct bd_info *bd = gd->bd;
Heiko Schocher42042982011-06-02 19:38:24 +0000475
York Sun28417032010-09-28 15:20:31 -0700476 *vstart = CONFIG_SYS_SDRAM_BASE;
Heiko Schocher42042982011-06-02 19:38:24 +0000477 *size = (gd->ram_size >= 256 << 20 ?
478 256 << 20 : gd->ram_size) - (1 << 20);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100479
Yuri Tikhonov9c02def2007-08-25 05:07:16 +0200480 /* Limit area to be tested with the board info struct */
York Sun28417032010-09-28 15:20:31 -0700481 if ((*vstart) + (*size) > (ulong)bd)
482 *size = (ulong)bd - *vstart;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100483
York Sun28417032010-09-28 15:20:31 -0700484 return 0;
485}
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100486
York Sun28417032010-09-28 15:20:31 -0700487__attribute__((weak))
488int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
489{
490 return 1;
491}
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100492
York Sun28417032010-09-28 15:20:31 -0700493__attribute__((weak))
494int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
495{
496 return 0;
497}
498
499__attribute__((weak))
500void arch_memory_failure_handle(void)
501{
502 return;
503}
504
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000505int memory_regions_post_test(int flags)
506{
507 int ret = 0;
508 phys_addr_t phys_offset = 0;
509 u32 memsize, vstart;
510
511 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
512
513 ret = memory_post_test_lines(vstart, memsize);
514 if (!ret)
515 ret = memory_post_test_regions(vstart, memsize);
516
517 return ret;
518}
519
York Sun28417032010-09-28 15:20:31 -0700520int memory_post_test(int flags)
521{
522 int ret = 0;
523 phys_addr_t phys_offset = 0;
524 u32 memsize, vstart;
525
526 arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
527
528 do {
529 if (flags & POST_SLOWTEST) {
530 ret = memory_post_tests(vstart, memsize);
531 } else { /* POST_NORMAL */
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000532 ret = memory_post_test_regions(vstart, memsize);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100533 }
York Sun28417032010-09-28 15:20:31 -0700534 } while (!ret &&
535 !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
536
537 arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
538 if (ret)
539 arch_memory_failure_handle();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100540
541 return ret;
542}
543
Valentin Longchamp8d3fcb52011-09-12 04:18:40 +0000544#endif /* CONFIG_POST&(CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) */