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Stefan Roese4745aca2007-02-20 10:57:08 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
27 * katmai.h - configuration for AMCC Katmai (440SPe)
28 ***********************************************************************/
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020032
Stefan Roese4745aca2007-02-20 10:57:08 +010033/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36#define CONFIG_KATMAI 1 /* Board is Katmai */
37#define CONFIG_4xx 1 /* ... PPC4xx family */
38#define CONFIG_440 1 /* ... PPC440 family */
39#define CONFIG_440SPE 1 /* Specifc SPe support */
40#undef CFG_DRAM_TEST /* Disable-takes long time */
41#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42
43#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
44#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
Stefan Roese4745aca2007-02-20 10:57:08 +010045#undef CONFIG_SHOW_BOOT_PROGRESS
46
47/*-----------------------------------------------------------------------
48 * Base addresses -- Note these are effective addresses where the
49 * actual resources get mapped (not physical addresses)
50 *----------------------------------------------------------------------*/
51#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
52#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
53
54#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
55#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
56#define CFG_MONITOR_BASE TEXT_BASE
57#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
58#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
59
60#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
61#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
62#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
63
64#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
Stefan Roese4dbee8a2007-10-05 07:57:20 +020065#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
Stefan Roese4745aca2007-02-20 10:57:08 +010066#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
67
68#define CFG_PCIE0_CFGBASE 0xc0000000
Grzegorz Bernacki7f191392007-09-07 18:20:23 +020069#define CFG_PCIE1_CFGBASE 0xc1000000
70#define CFG_PCIE2_CFGBASE 0xc2000000
71#define CFG_PCIE0_XCFGBASE 0xc3000000
72#define CFG_PCIE1_XCFGBASE 0xc3001000
73#define CFG_PCIE2_XCFGBASE 0xc3002000
Stefan Roese4745aca2007-02-20 10:57:08 +010074
Stefan Roese97923772007-10-05 09:18:23 +020075/* base address of inbound PCIe window */
Stefan Roesec36c6812007-10-18 07:42:27 +020076#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese97923772007-10-05 09:18:23 +020077
Stefan Roese4745aca2007-02-20 10:57:08 +010078/* System RAM mapped to PCI space */
79#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
80#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
81#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
82
Stefan Roesea65c5762007-04-02 10:09:30 +020083#define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
Stefan Roese4745aca2007-02-20 10:57:08 +010084
85/*-----------------------------------------------------------------------
86 * Initial RAM & stack pointer (placed in internal SRAM)
87 *----------------------------------------------------------------------*/
88#define CFG_TEMP_STACK_OCM 1
89#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
90#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
91#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
92#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
93
94#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
95#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
96#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
97
98/*-----------------------------------------------------------------------
99 * Serial Port
100 *----------------------------------------------------------------------*/
101#define CONFIG_SERIAL_MULTI 1
102#undef CONFIG_UART1_CONSOLE
103#undef CFG_EXT_SERIAL_CLOCK
104#define CONFIG_BAUDRATE 115200
105#define CFG_BAUDRATE_TABLE \
106 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
107
108/*-----------------------------------------------------------------------
109 * DDR SDRAM
110 *----------------------------------------------------------------------*/
111#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100112#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
Stefan Roese2721a682007-03-08 10:07:18 +0100113#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese845c6c92008-01-05 09:12:41 +0100114#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
Stefan Roese4745aca2007-02-20 10:57:08 +0100115#undef CONFIG_STRESS
Stefan Roese4745aca2007-02-20 10:57:08 +0100116
117/*-----------------------------------------------------------------------
118 * I2C
119 *----------------------------------------------------------------------*/
120#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
121#undef CONFIG_SOFT_I2C /* I2C bit-banged */
122#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
123#define CFG_I2C_SLAVE 0x7F
124
125#define CONFIG_I2C_MULTI_BUS
126#define CONFIG_I2C_CMD_TREE
127#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
128
129#define IIC0_BOOTPROM_ADDR 0x50
130#define IIC0_ALT_BOOTPROM_ADDR 0x54
131
132#define CFG_I2C_MULTI_EEPROMS
133#define CFG_I2C_EEPROM_ADDR (0x50)
134#define CFG_I2C_EEPROM_ADDR_LEN 1
135#define CFG_EEPROM_PAGE_WRITE_ENABLE
136#define CFG_EEPROM_PAGE_WRITE_BITS 3
137#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
138
139/* I2C RTC */
140#define CONFIG_RTC_M41T11 1
141#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
142#define CFG_I2C_RTC_ADDR 0x68
143#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
144
145/* I2C DTT */
146#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
147#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
148/*
149 * standard dtt sensor configuration - bottom bit will determine local or
150 * remote sensor of the ADM1021, the rest determines index into
151 * CFG_DTT_ADM1021 array below.
152 */
153#define CONFIG_DTT_SENSORS { 0, 1 }
154
155/*
156 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
157 * there will be one entry in this array for each two (dummy) sensors in
158 * CONFIG_DTT_SENSORS.
159 *
160 * For Katmai board:
161 * - only one ADM1021
162 * - i2c addr 0x18
163 * - conversion rate 0x02 = 0.25 conversions/second
164 * - ALERT ouput disabled
165 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
166 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
167 */
168#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
169
170/*-----------------------------------------------------------------------
171 * Environment
172 *----------------------------------------------------------------------*/
173#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
174
175#define CONFIG_PREBOOT "echo;" \
176 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
177 "echo"
178
179#undef CONFIG_BOOTARGS
180
181#define CONFIG_EXTRA_ENV_SETTINGS \
182 "netdev=eth0\0" \
183 "hostname=katmai\0" \
184 "nfsargs=setenv bootargs root=/dev/nfs rw " \
185 "nfsroot=${serverip}:${rootpath}\0" \
186 "ramargs=setenv bootargs root=/dev/ram rw\0" \
187 "addip=setenv bootargs ${bootargs} " \
188 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
189 ":${hostname}:${netdev}:off panic=1\0" \
190 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
191 "flash_nfs=run nfsargs addip addtty;" \
192 "bootm ${kernel_addr}\0" \
193 "flash_self=run ramargs addip addtty;" \
194 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
195 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
196 "bootm\0" \
Stefan Roesebf8324e2007-12-19 09:05:40 +0100197 "net_nfs_fdt=tftp 200000 ${bootfile};" \
198 "tftp ${fdt_addr} ${fdt_file};" \
199 "run nfsargs addip addtty;" \
200 "bootm 200000 - ${fdt_addr}\0" \
201 "rootpath=/opt/eldk/ppc_4xx\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100202 "bootfile=katmai/uImage\0" \
Stefan Roesebf8324e2007-12-19 09:05:40 +0100203 "fdt_file=katmai/katmai.dtb\0" \
204 "fdt_addr=400000\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100205 "kernel_addr=fff10000\0" \
206 "ramdisk_addr=fff20000\0" \
207 "initrd_high=30000000\0" \
208 "load=tftp 200000 katmai/u-boot.bin\0" \
209 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
210 "cp.b ${fileaddr} fffc0000 ${filesize};" \
211 "setenv filesize;saveenv\0" \
212 "upd=run load;run update\0" \
213 "kozio=bootm ffc60000\0" \
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200214 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200215 "pcie_mode=RP:RP:RP\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100216 ""
217#define CONFIG_BOOTCOMMAND "run flash_self"
218
219#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
220
221#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
222#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
223
Stefan Roese4745aca2007-02-20 10:57:08 +0100224
Jon Loeligerbc234c12007-07-04 22:32:51 -0500225/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500226 * BOOTP options
227 */
228#define CONFIG_BOOTP_BOOTFILESIZE
229#define CONFIG_BOOTP_BOOTPATH
230#define CONFIG_BOOTP_GATEWAY
231#define CONFIG_BOOTP_HOSTNAME
232
233
234/*
Jon Loeligerbc234c12007-07-04 22:32:51 -0500235 * Command line configuration.
236 */
237#include <config_cmd_default.h>
238
239#define CONFIG_CMD_ASKENV
240#define CONFIG_CMD_EEPROM
241#define CONFIG_CMD_DATE
242#define CONFIG_CMD_DHCP
243#define CONFIG_CMD_DIAG
244#define CONFIG_CMD_DTT
245#define CONFIG_CMD_ELF
246#define CONFIG_CMD_EXT2
247#define CONFIG_CMD_FAT
248#define CONFIG_CMD_I2C
249#define CONFIG_CMD_IRQ
250#define CONFIG_CMD_MII
251#define CONFIG_CMD_NET
252#define CONFIG_CMD_NFS
253#define CONFIG_CMD_PCI
254#define CONFIG_CMD_PING
255#define CONFIG_CMD_REGINFO
256#define CONFIG_CMD_SDRAM
Stefan Roeseafe9fa52007-10-22 16:24:44 +0200257#define CONFIG_CMD_SNTP
Stefan Roese4745aca2007-02-20 10:57:08 +0100258
259#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
260#define CONFIG_MII 1 /* MII PHY management */
261#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
262#define CONFIG_HAS_ETH0
263#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
264#define CONFIG_PHY_RESET_DELAY 1000
265#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
266#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
267#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
268
269#define CONFIG_NETCONSOLE /* include NetConsole support */
270#define CONFIG_NET_MULTI /* needed for NetConsole */
271
272#undef CONFIG_WATCHDOG /* watchdog disabled */
273
274/*
275 * Miscellaneous configurable options
276 */
277#define CFG_LONGHELP /* undef to save memory */
278#define CFG_PROMPT "=> " /* Monitor Command Prompt */
279
Jon Loeligerbc234c12007-07-04 22:32:51 -0500280#if defined(CONFIG_CMD_KGDB)
Stefan Roese4745aca2007-02-20 10:57:08 +0100281#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
282#else
283#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
284#endif
285#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
286#define CFG_MAXARGS 16 /* max number of command args */
287#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
288
289#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
290#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
291
292#define CFG_LOAD_ADDR 0x100000 /* default load address */
293#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
294
295#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
296
297#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
298#define CONFIG_LOOPW 1 /* enable loopw command */
299#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
300#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
301#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
302
303#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
304
305/*-----------------------------------------------------------------------
306 * FLASH related
307 *----------------------------------------------------------------------*/
308#define CFG_FLASH_CFI
309#define CFG_FLASH_CFI_DRIVER
310#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
311#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
312
313#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
314#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
315#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
316
317#undef CFG_FLASH_CHECKSUM
318#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
319#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
320
321#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
322#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
323#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
324
325/* Address and size of Redundant Environment Sector */
326#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
327#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
328
329/*-----------------------------------------------------------------------
330 * PCI stuff
331 *-----------------------------------------------------------------------
332 */
333/* General PCI */
334#define CONFIG_PCI /* include pci support */
335#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
336#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200337#define CONFIG_PCI_CONFIG_HOST_BRIDGE
Stefan Roese4745aca2007-02-20 10:57:08 +0100338
339/* Board-specific PCI */
Stefan Roese4745aca2007-02-20 10:57:08 +0100340#define CFG_PCI_TARGET_INIT /* let board init pci target */
341#undef CFG_PCI_MASTER_INIT
342
343#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
344#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
345/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
346
347/*
348 * NETWORK Support (PCI):
349 */
350/* Support for Intel 82557/82559/82559ER chips. */
351#define CONFIG_EEPRO100
352
353/*-----------------------------------------------------------------------
354 * Xilinx System ACE support
355 *----------------------------------------------------------------------*/
356#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
357#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
358#define CFG_SYSTEMACE_BASE CFG_ACE_BASE
359#define CONFIG_DOS_PARTITION 1
360
361/*-----------------------------------------------------------------------
362 * External Bus Controller (EBC) Setup
363 *----------------------------------------------------------------------*/
364
365/* Memory Bank 0 (Flash) initialization */
366#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
367 EBC_BXAP_TWT_ENCODE(7) | \
368 EBC_BXAP_BCE_DISABLE | \
369 EBC_BXAP_BCT_2TRANS | \
370 EBC_BXAP_CSN_ENCODE(0) | \
371 EBC_BXAP_OEN_ENCODE(0) | \
372 EBC_BXAP_WBN_ENCODE(0) | \
373 EBC_BXAP_WBF_ENCODE(0) | \
374 EBC_BXAP_TH_ENCODE(0) | \
375 EBC_BXAP_RE_DISABLED | \
376 EBC_BXAP_SOR_DELAYED | \
377 EBC_BXAP_BEM_WRITEONLY | \
378 EBC_BXAP_PEN_DISABLED)
379#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
380 EBC_BXCR_BS_16MB | \
381 EBC_BXCR_BU_RW | \
382 EBC_BXCR_BW_16BIT)
383
384/* Memory Bank 1 (Xilinx System ACE controller) initialization */
Stefan Roesed2168622007-04-19 09:53:52 +0200385#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
386 EBC_BXAP_TWT_ENCODE(4) | \
387 EBC_BXAP_BCE_DISABLE | \
388 EBC_BXAP_BCT_2TRANS | \
389 EBC_BXAP_CSN_ENCODE(0) | \
390 EBC_BXAP_OEN_ENCODE(0) | \
391 EBC_BXAP_WBN_ENCODE(0) | \
392 EBC_BXAP_WBF_ENCODE(0) | \
393 EBC_BXAP_TH_ENCODE(0) | \
394 EBC_BXAP_RE_DISABLED | \
395 EBC_BXAP_SOR_NONDELAYED | \
396 EBC_BXAP_BEM_WRITEONLY | \
397 EBC_BXAP_PEN_DISABLED)
Stefan Roese4745aca2007-02-20 10:57:08 +0100398#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
399 EBC_BXCR_BS_1MB | \
400 EBC_BXCR_BU_RW | \
401 EBC_BXCR_BW_16BIT)
402
403/*-------------------------------------------------------------------------
404 * Initialize EBC CONFIG -
405 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
406 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
407 *-------------------------------------------------------------------------*/
408#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
409 EBC_CFG_PTD_ENABLE | \
410 EBC_CFG_RTC_16PERCLK | \
411 EBC_CFG_ATC_PREVIOUS | \
412 EBC_CFG_DTC_PREVIOUS | \
413 EBC_CFG_CTC_PREVIOUS | \
414 EBC_CFG_OEO_PREVIOUS | \
415 EBC_CFG_EMC_DEFAULT | \
416 EBC_CFG_PME_DISABLE | \
417 EBC_CFG_PR_16)
418
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100419/*-----------------------------------------------------------------------
420 * GPIO Setup
421 *----------------------------------------------------------------------*/
422#define CFG_GPIO_PCIE_PRESENT0 17
423#define CFG_GPIO_PCIE_PRESENT1 21
424#define CFG_GPIO_PCIE_PRESENT2 23
425#define CFG_GPIO_RS232_FORCEOFF 30
426
427#define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \
428 GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \
429 GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \
430 GPIO_VAL(CFG_GPIO_RS232_FORCEOFF))
431#define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
432#define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)
433#define CFG_GPIO_ODR 0
434
Stefan Roese4745aca2007-02-20 10:57:08 +0100435/*
436 * For booting Linux, the board info and command line data
437 * have to be in the first 8 MB of memory, since this is
438 * the maximum mapped by the Linux kernel during initialization.
439 */
440#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
Stefan Roese4745aca2007-02-20 10:57:08 +0100441
442/*
443 * Internal Definitions
444 *
445 * Boot Flags
446 */
447#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
448#define BOOTFLAG_WARM 0x02 /* Software reboot */
449
Jon Loeligerbc234c12007-07-04 22:32:51 -0500450#if defined(CONFIG_CMD_KGDB)
Stefan Roese4745aca2007-02-20 10:57:08 +0100451#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
452#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
453#endif
454
Stefan Roesebf8324e2007-12-19 09:05:40 +0100455/* pass open firmware flat tree */
456#define CONFIG_OF_LIBFDT 1
457#define CONFIG_OF_BOARD_SETUP 1
458
Stefan Roese4745aca2007-02-20 10:57:08 +0100459#endif /* __CONFIG_H */