blob: e501907b53514c56471867cdf22d892fcfea7ce7 [file] [log] [blame]
Sam Shihac57e2b2020-01-10 16:30:26 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <common.h>
8#include <fdtdec.h>
Simon Glass691d7192020-05-10 11:40:02 -06009#include <init.h>
Sam Shihac57e2b2020-01-10 16:30:26 +080010#include <asm/armv8/mmu.h>
Simon Glass90526e92020-05-10 11:39:56 -060011#include <asm/cache.h>
Sam Shihac57e2b2020-01-10 16:30:26 +080012
13int print_cpuinfo(void)
14{
15 printf("CPU: MediaTek MT7622\n");
16 return 0;
17}
18
19int dram_init(void)
20{
21 int ret;
22
23 ret = fdtdec_setup_memory_banksize();
24 if (ret)
25 return ret;
26 return fdtdec_setup_mem_size_base();
27
28}
29
Harald Seiler35b65dd2020-12-15 16:47:52 +010030void reset_cpu(void)
Sam Shihac57e2b2020-01-10 16:30:26 +080031{
32 psci_system_reset();
33}
34
35static struct mm_region mt7622_mem_map[] = {
36 {
37 /* DDR */
38 .virt = 0x40000000UL,
39 .phys = 0x40000000UL,
40 .size = 0x40000000UL,
41 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
42 }, {
43 .virt = 0x00000000UL,
44 .phys = 0x00000000UL,
45 .size = 0x40000000UL,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 PTE_BLOCK_NON_SHARE |
48 PTE_BLOCK_PXN | PTE_BLOCK_UXN
49 }, {
50 0,
51 }
52};
53struct mm_region *mem_map = mt7622_mem_map;