arch/arm/dts/uniphier-common32.dtsi

/*
 * Device Tree Source commonly used by UniPhier ARM SoCs
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+	X11
 */

/include/ "skeleton.dtsi"

/ {
	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;
		u-boot,dm-pre-reloc;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mioctrl@59810000 {
			compatible = "socionext,uniphier-mioctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;
			u-boot,dm-pre-reloc;

			mio_clk: clock {
				#clock-cells = <1>;
			};

			mio_rst: reset {
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				#clock-cells = <1>;
			};

			peri_rst: reset {
				#reset-cells = <1>;
			};
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0x104>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0x104>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;
			u-boot,dm-pre-reloc;

			pinctrl: pinctrl {
				/* specify compatible in each SoC DTSI */
				u-boot,dm-pre-reloc;
			};
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x4000>;

			sys_clk: clock {
				#clock-cells = <1>;
			};

			sys_rst: reset {
				#reset-cells = <1>;
			};
		};

		nand: nand@68000000 {
			compatible = "denali,denali-nand-dt";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"