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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2003 ETC s.r.o.
3 *
4 * This code was inspired by Marius Groeger and Kyle Harris code
5 * available in other board ports for U-Boot
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Written by Peter Figuli <peposh@etc.sk>, 2003.
26 *
27 */
28
29#include <common.h>
30#include "intel.h"
31
32
33/*
34 * This code should handle CFI FLASH memory device. This code is very
35 * minimalistic approach without many essential error handling code as well.
36 * Because U-Boot actually is missing smart handling of FLASH device,
37 * we just set flash_id to anything else to FLASH_UNKNOW, so common code
38 * can call us without any restrictions.
39 * TODO: Add CFI Query, to be able to determine FLASH device.
40 * TODO: Add error handling code
41 * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
42 * hopefully may work with other configurations.
43 */
44
45#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
46# define FLASH_BUS vu_char
Jean-Christophe PLAGNIOL-VILLARDdb695b72008-03-09 10:44:01 +010047# define FLASH_BUS_RET u_char
wdenk281e00a2004-08-01 22:48:16 +000048# if ( SCB9328_FLASH_INTERLEAVE == 1 )
49# define FLASH_CMD( x ) x
50# else
51# error "With 8bit bus only one chip is allowed"
52# endif
53
54
55#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
56# define FLASH_BUS vu_short
Jean-Christophe PLAGNIOL-VILLARDdb695b72008-03-09 10:44:01 +010057# define FLASH_BUS_RET u_short
wdenk281e00a2004-08-01 22:48:16 +000058# if ( SCB9328_FLASH_INTERLEAVE == 1 )
59# define FLASH_CMD( x ) x
60# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
61# define FLASH_CMD( x ) (( x << 8 )| x )
62# else
63# error "With 16bit bus only 1 or 2 chip(s) are allowed"
64# endif
65
66
67#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
68# define FLASH_BUS vu_long
Jean-Christophe PLAGNIOL-VILLARDdb695b72008-03-09 10:44:01 +010069# define FLASH_BUS_RET u_long
wdenk281e00a2004-08-01 22:48:16 +000070# if ( SCB9328_FLASH_INTERLEAVE == 1 )
71# define FLASH_CMD( x ) x
72# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
73# define FLASH_CMD( x ) (( x << 16 )| x )
74# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
75# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
76# else
77# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
78# endif
79
80#else
81# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
82#endif
83
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
wdenk281e00a2004-08-01 22:48:16 +000086
Jean-Christophe PLAGNIOL-VILLARDdb695b72008-03-09 10:44:01 +010087static FLASH_BUS_RET flash_status_reg (void)
wdenk281e00a2004-08-01 22:48:16 +000088{
89
90 FLASH_BUS *addr = (FLASH_BUS *) 0;
91
92 *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
93
94 return *addr;
95}
96
97static int flash_ready (ulong timeout)
98{
99 int ok = 1;
Graeme Russa60d1e52011-07-15 23:31:37 +0000100 ulong start;
wdenk281e00a2004-08-01 22:48:16 +0000101
Graeme Russa60d1e52011-07-15 23:31:37 +0000102 start = get_timer(0);
wdenk281e00a2004-08-01 22:48:16 +0000103 while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
104 FLASH_CMD (CFI_INTEL_SR_READY)) {
Graeme Russa60d1e52011-07-15 23:31:37 +0000105 if (get_timer(start) > timeout && timeout != 0) {
wdenk281e00a2004-08-01 22:48:16 +0000106 ok = 0;
107 break;
108 }
109 }
110 return ok;
111}
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
wdenk281e00a2004-08-01 22:48:16 +0000114# error "SCB9328 platform has only one flash bank!"
115#endif
116
117
118ulong flash_init (void)
119{
120 int i;
121 unsigned long address = SCB9328_FLASH_BASE;
122
123 flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
wdenk281e00a2004-08-01 22:48:16 +0000125 flash_info[0].flash_id = INTEL_MANUFACT;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
wdenk281e00a2004-08-01 22:48:16 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
wdenk281e00a2004-08-01 22:48:16 +0000129 flash_info[0].start[i] = address;
130#ifdef SCB9328_FLASH_UNLOCK
131 /* Some devices are hw locked after start. */
132 *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
133 *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
134 flash_ready (0);
135 *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
136#endif
137 address += SCB9328_FLASH_SECT_SIZE;
138 }
139
140 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 CONFIG_SYS_FLASH_BASE,
142 CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
wdenk281e00a2004-08-01 22:48:16 +0000143 &flash_info[0]);
144
145 flash_protect (FLAG_PROTECT_SET,
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200146 CONFIG_ENV_ADDR,
147 CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
wdenk281e00a2004-08-01 22:48:16 +0000148
149 return SCB9328_FLASH_BANK_SIZE;
150}
151
152void flash_print_info (flash_info_t * info)
153{
154 int i;
155
156 printf (" Intel vendor\n");
157 printf (" Size: %ld MB in %d Sectors\n",
158 info->size >> 20, info->sector_count);
159
160 printf (" Sector Start Addresses:");
161 for (i = 0; i < info->sector_count; i++) {
162 if (!(i % 5)) {
163 printf ("\n");
164 }
165
166 printf (" %08lX%s", info->start[i],
167 info->protect[i] ? " (RO)" : " ");
168 }
169 printf ("\n");
170}
171
172
173int flash_erase (flash_info_t * info, int s_first, int s_last)
174{
175 int flag, non_protected = 0, sector;
176 int rc = ERR_OK;
177
178 FLASH_BUS *address;
179
180 for (sector = s_first; sector <= s_last; sector++) {
181 if (!info->protect[sector]) {
182 non_protected++;
183 }
184 }
185
186 if (!non_protected) {
187 return ERR_PROTECTED;
188 }
189
190 /*
191 * Disable interrupts which might cause a timeout
192 * here. Remember that our exception vectors are
193 * at address 0 in the flash, and we don't want a
194 * (ticker) exception to happen while the flash
195 * chip is in programming mode.
196 */
197 flag = disable_interrupts ();
198
199
200 /* Start erase on unprotected sectors */
201 for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
202 if (info->protect[sector]) {
203 printf ("Protected sector %2d skipping...\n", sector);
204 continue;
205 } else {
206 printf ("Erasing sector %2d ... ", sector);
207 }
208
209 address = (FLASH_BUS *) (info->start[sector]);
210
211 *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
212 *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
wdenk281e00a2004-08-01 22:48:16 +0000214 *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
215 printf ("ok.\n");
216 } else {
217 *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
218 rc = ERR_TIMOUT;
219 printf ("timeout! Aborting...\n");
220 break;
221 }
222 *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
223 }
224 if (ctrlc ())
225 printf ("User Interrupt!\n");
226
227 /* allow flash to settle - wait 10 ms */
228 udelay_masked (10000);
229 if (flag) {
230 enable_interrupts ();
231 }
232
233 return rc;
234}
235
236static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
237{
238 FLASH_BUS *address = (FLASH_BUS *) dest;
239 int rc = ERR_OK;
240 int flag;
241
242 /* Check if Flash is (sufficiently) erased */
243 if ((*address & data) != data) {
244 return ERR_NOT_ERASED;
245 }
246
247 /*
248 * Disable interrupts which might cause a timeout
249 * here. Remember that our exception vectors are
250 * at address 0 in the flash, and we don't want a
251 * (ticker) exception to happen while the flash
252 * chip is in programming mode.
253 */
254
255 flag = disable_interrupts ();
256
257 *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
258 *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
259 *address = data;
260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261 if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
wdenk281e00a2004-08-01 22:48:16 +0000262 *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
263 rc = ERR_TIMOUT;
264 printf ("timeout! Aborting...\n");
265 }
266
267 *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
268 if (flag) {
269 enable_interrupts ();
270 }
271
272 return rc;
273}
274
275int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
276{
277 ulong read_addr, write_addr;
278 FLASH_BUS data;
279 int i, result = ERR_OK;
280
281
282 read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
283 write_addr = read_addr;
284 if (read_addr != addr) {
285 data = 0;
286 for (i = 0; i < sizeof (FLASH_BUS); i++) {
287 if (read_addr < addr || cnt == 0) {
288 data |= *((uchar *) read_addr) << i * 8;
289 } else {
290 data |= (*src++) << i * 8;
291 cnt--;
292 }
293 read_addr++;
294 }
295 if ((result = write_data (info, write_addr, data)) != ERR_OK) {
296 return result;
297 }
298 write_addr += sizeof (FLASH_BUS);
299 }
300 for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
301 if ((result = write_data (info, write_addr,
302 *((FLASH_BUS *) src))) != ERR_OK) {
303 return result;
304 }
305 write_addr += sizeof (FLASH_BUS);
306 src += sizeof (FLASH_BUS);
307 }
308 if (cnt > 0) {
309 read_addr = write_addr;
310 data = 0;
311 for (i = 0; i < sizeof (FLASH_BUS); i++) {
312 if (cnt > 0) {
313 data |= (*src++) << i * 8;
314 cnt--;
315 } else {
316 data |= *((uchar *) read_addr) << i * 8;
317 }
318 read_addr++;
319 }
320 if ((result = write_data (info, write_addr, data)) != 0) {
321 return result;
322 }
323 }
324 return ERR_OK;
325}