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wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2003
6 * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <pci.h>
30
31/*****************************************************************************
32 * initialize SDRAM/DDRAM controller.
33 * TBD: get data from I2C EEPROM
34 *****************************************************************************/
35long int initdram (int board_type)
36{
37 ulong dramsize = 0;
38#ifndef CFG_RAMBOOT
wdenkd4ca31c2004-01-02 14:00:00 +000039#if 0
wdenkc1896002003-12-28 11:44:59 +000040 ulong t;
41 ulong tap_del;
wdenkd4ca31c2004-01-02 14:00:00 +000042#endif
wdenkc1896002003-12-28 11:44:59 +000043
44 #define MODE_EN 0x80000000
45 #define SOFT_PRE 2
46 #define SOFT_REF 4
47
48 /* configure SDRAM start/end */
49 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
50 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
51
52 /* setup config registers */
53 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
54 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
55
56 /* unlock mode register */
57 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
58 /* precharge all banks */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
wdenk42dfe7a2004-03-14 22:25:36 +000060#ifdef CFG_DRAM_DDR
wdenkc1896002003-12-28 11:44:59 +000061 /* set extended mode register */
62 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
63#endif
64 /* set mode register */
65 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
68 /* auto refresh */
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
70 /* set mode register */
71 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
72 /* normal operation */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
74 /* write default TAP delay */
75 *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
76
77#if 0
wdenkd4ca31c2004-01-02 14:00:00 +000078 for (tap_del = 0; tap_del < 32; tap_del++)
79 {
wdenkc1896002003-12-28 11:44:59 +000080 *(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
81
82 printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
83 for (t = 0; t < 0x04000000; t+=4)
84 *(vu_long *) t = t;
85 printf ("Checking DRAM...\n");
wdenkd4ca31c2004-01-02 14:00:00 +000086 for (t = 0; t < 0x04000000; t+=4)
87 {
wdenkc1896002003-12-28 11:44:59 +000088 ulong rval = *(vu_long *) t;
wdenkd4ca31c2004-01-02 14:00:00 +000089 if (rval != t)
90 {
wdenkc1896002003-12-28 11:44:59 +000091 printf ("mismatch at %x: ", t);
92 printf (" 1.read %x", rval);
93 printf (" 2.read %x", *(vu_long *) t);
94 printf (" 3.read %x", *(vu_long *) t);
95 break;
96 }
97 }
98 }
99#endif
100#endif /* CFG_RAMBOOT */
101
102 dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
103
104 /* return total ram size */
105 return dramsize;
106}
107
108/*****************************************************************************
109 * print board identification
110 *****************************************************************************/
111int checkboard (void)
112{
113#if defined (CONFIG_EVAL5200)
114 puts ("Board: EMK TOP5200 on EVAL5200\n");
115#else
wdenk4d13cba2004-03-14 14:09:05 +0000116#if defined (CONFIG_LITE5200)
117 puts ("Board: LITE5200\n");
118#else
wdenkc1896002003-12-28 11:44:59 +0000119#if defined (CONFIG_MINI5200)
120 puts ("Board: EMK TOP5200 on MINI5200\n");
121#else
122 puts ("Board: EMK TOP5200\n");
123#endif
124#endif
wdenk4d13cba2004-03-14 14:09:05 +0000125#endif
wdenkc1896002003-12-28 11:44:59 +0000126 return 0;
127}
128
129/*****************************************************************************
130 * prepare for FLASH detection
131 *****************************************************************************/
132void flash_preinit(void)
133{
134 /*
135 * Now, when we are in RAM, enable flash write
136 * access for detection process.
137 * Note that CS_BOOT cannot be cleared when
138 * executing in flash.
139 */
140 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
141}
142
143/*****************************************************************************
144 * finalize FLASH setup
145 *****************************************************************************/
146void flash_afterinit(uint bank, ulong start, ulong size)
147{
148 if (bank == 0) { /* adjust mapping */
149 *(vu_long *)MPC5XXX_BOOTCS_START =
150 *(vu_long *)MPC5XXX_CS0_START = START_REG(start);
151 *(vu_long *)MPC5XXX_BOOTCS_STOP =
152 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(start, size);
153 }
154}
155
156/*****************************************************************************
157 * otherinits after RAM is there and we are relocated to RAM
158 * note: though this is an int function, nobody cares for the result!
159 *****************************************************************************/
160int misc_init_r (void)
161{
wdenk4d13cba2004-03-14 14:09:05 +0000162#if !defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +0000163 /* read 'factory' part of EEPROM */
wdenk63e73c92004-02-23 22:22:28 +0000164 extern void read_factory_r (void);
165 read_factory_r ();
wdenk4d13cba2004-03-14 14:09:05 +0000166#endif
wdenkc1896002003-12-28 11:44:59 +0000167 return (0);
168}
169
170/*****************************************************************************
171 * initialize the PCI system
172 *****************************************************************************/
173#ifdef CONFIG_PCI
174static struct pci_controller hose;
175
176extern void pci_mpc5xxx_init(struct pci_controller *);
177
178void pci_init_board(void)
179{
180 pci_mpc5xxx_init(&hose);
181}
182#endif
wdenk4d13cba2004-03-14 14:09:05 +0000183
184/*****************************************************************************
wdenk498b8db2004-04-18 22:26:17 +0000185 * provide the IDE Reset Function
wdenk4d13cba2004-03-14 14:09:05 +0000186 *****************************************************************************/
wdenk498b8db2004-04-18 22:26:17 +0000187#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
188
189#define GPIO_PSC1_4 0x01000000UL
190
191void init_ide_reset (void)
192{
193 debug ("init_ide_reset\n");
194
195 /* Configure PSC1_4 as GPIO output for ATA reset */
196 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
197 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
198}
199
wdenk4d13cba2004-03-14 14:09:05 +0000200void ide_set_reset (int idereset)
201{
wdenk498b8db2004-04-18 22:26:17 +0000202 debug ("ide_reset(%d)\n", idereset);
203
wdenk4d13cba2004-03-14 14:09:05 +0000204 if (idereset) {
205 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
206 } else {
wdenk498b8db2004-04-18 22:26:17 +0000207 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000208 }
wdenk4d13cba2004-03-14 14:09:05 +0000209}
wdenk498b8db2004-04-18 22:26:17 +0000210#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */