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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
3 *
4 * This driver for AMD PCnet network controllers is derived from the
5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#include <common.h>
11#include <malloc.h>
12#include <net.h>
Ben Warrene3090532008-08-31 10:08:43 -070013#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000014#include <asm/io.h>
15#include <pci.h>
16
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020017#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
wdenkc6097192002-11-03 00:24:07 +000018
Wolfgang Denk138b6082011-11-05 05:12:58 +000019#define PCNET_DEBUG1(fmt,args...) \
20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
21#define PCNET_DEBUG2(fmt,args...) \
22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
wdenkc6097192002-11-03 00:24:07 +000023
wdenkc6097192002-11-03 00:24:07 +000024#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
25#error "Macro for PCnet chip version is not defined!"
26#endif
27
28/*
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
32 */
33#define PCNET_LOG_TX_BUFFERS 0
34#define PCNET_LOG_RX_BUFFERS 2
35
36#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
37#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
38
39#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
40#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
41
42#define PKT_BUF_SZ 1544
43
44/* The PCNET Rx and Tx ring descriptors. */
45struct pcnet_rx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020046 u32 base;
47 s16 buf_length;
48 s16 status;
49 u32 msg_length;
50 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000051};
52
53struct pcnet_tx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020054 u32 base;
55 s16 length;
56 s16 status;
57 u32 misc;
58 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000059};
60
61/* The PCNET 32-Bit initialization block, described in databook. */
62struct pcnet_init_block {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020063 u16 mode;
64 u16 tlen_rlen;
65 u8 phys_addr[6];
66 u16 reserved;
67 u32 filter[2];
68 /* Receive and transmit ring base, along with extra bits. */
69 u32 rx_ring;
70 u32 tx_ring;
71 u32 reserved2;
wdenkc6097192002-11-03 00:24:07 +000072};
73
Paul Burtonf1ae3822014-04-07 16:41:46 +010074struct pcnet_uncached_priv {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020075 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
76 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
77 struct pcnet_init_block init_block;
Paul Burtonf1ae3822014-04-07 16:41:46 +010078};
79
80typedef struct pcnet_priv {
81 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020082 /* Receive Buffer space */
Paul Burtona354ddc2014-04-07 16:41:47 +010083 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020084 int cur_rx;
85 int cur_tx;
wdenkc6097192002-11-03 00:24:07 +000086} pcnet_priv_t;
87
88static pcnet_priv_t *lp;
89
90/* Offsets from base I/O address for WIO mode */
91#define PCNET_RDP 0x10
92#define PCNET_RAP 0x12
93#define PCNET_RESET 0x14
94#define PCNET_BDP 0x16
95
Paul Burton6011dab2013-11-08 11:18:43 +000096static u16 pcnet_read_csr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +000097{
Paul Burton6011dab2013-11-08 11:18:43 +000098 outw(index, dev->iobase + PCNET_RAP);
99 return inw(dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000100}
101
Paul Burton6011dab2013-11-08 11:18:43 +0000102static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000103{
Paul Burton6011dab2013-11-08 11:18:43 +0000104 outw(index, dev->iobase + PCNET_RAP);
105 outw(val, dev->iobase + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000106}
107
Paul Burton6011dab2013-11-08 11:18:43 +0000108static u16 pcnet_read_bcr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +0000109{
Paul Burton6011dab2013-11-08 11:18:43 +0000110 outw(index, dev->iobase + PCNET_RAP);
111 return inw(dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000112}
113
Paul Burton6011dab2013-11-08 11:18:43 +0000114static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000115{
Paul Burton6011dab2013-11-08 11:18:43 +0000116 outw(index, dev->iobase + PCNET_RAP);
117 outw(val, dev->iobase + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000118}
119
Paul Burton6011dab2013-11-08 11:18:43 +0000120static void pcnet_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000121{
Paul Burton6011dab2013-11-08 11:18:43 +0000122 inw(dev->iobase + PCNET_RESET);
wdenkc6097192002-11-03 00:24:07 +0000123}
124
Paul Burton6011dab2013-11-08 11:18:43 +0000125static int pcnet_check(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000126{
Paul Burton6011dab2013-11-08 11:18:43 +0000127 outw(88, dev->iobase + PCNET_RAP);
128 return inw(dev->iobase + PCNET_RAP) == 88;
wdenkc6097192002-11-03 00:24:07 +0000129}
130
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200131static int pcnet_init (struct eth_device *dev, bd_t * bis);
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000132static int pcnet_send(struct eth_device *dev, void *packet, int length);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200133static int pcnet_recv (struct eth_device *dev);
134static void pcnet_halt (struct eth_device *dev);
135static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
wdenkc6097192002-11-03 00:24:07 +0000136
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100137static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
Paul Burton4677d662016-05-26 14:49:34 +0100138 void *addr)
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100139{
Paul Burton442d2e02016-05-26 14:49:35 +0100140 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100141 void *virt_addr = addr;
142
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100143 return pci_virt_to_mem(devbusfn, virt_addr);
144}
wdenkc6097192002-11-03 00:24:07 +0000145
146static struct pci_device_id supported[] = {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200147 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
148 {}
wdenkc6097192002-11-03 00:24:07 +0000149};
150
151
Paul Burton6011dab2013-11-08 11:18:43 +0000152int pcnet_initialize(bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000153{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200154 pci_dev_t devbusfn;
155 struct eth_device *dev;
156 u16 command, status;
157 int dev_nr = 0;
Paul Burtonbed1ca32016-05-26 17:32:29 +0100158 u32 bar;
wdenkc6097192002-11-03 00:24:07 +0000159
Paul Burton6011dab2013-11-08 11:18:43 +0000160 PCNET_DEBUG1("\npcnet_initialize...\n");
wdenkc6097192002-11-03 00:24:07 +0000161
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200162 for (dev_nr = 0;; dev_nr++) {
wdenkc6097192002-11-03 00:24:07 +0000163
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200164 /*
165 * Find the PCnet PCI device(s).
166 */
Paul Burton6011dab2013-11-08 11:18:43 +0000167 devbusfn = pci_find_devices(supported, dev_nr);
168 if (devbusfn < 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200169 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200170
171 /*
172 * Allocate and pre-fill the device structure.
173 */
Paul Burton6011dab2013-11-08 11:18:43 +0000174 dev = (struct eth_device *)malloc(sizeof(*dev));
Nobuhiro Iwamatsu5ed0eec2010-10-19 14:03:45 +0900175 if (!dev) {
176 printf("pcnet: Can not allocate memory\n");
177 break;
178 }
179 memset(dev, 0, sizeof(*dev));
Paul Burton442d2e02016-05-26 14:49:35 +0100180 dev->priv = (void *)(unsigned long)devbusfn;
Paul Burton6011dab2013-11-08 11:18:43 +0000181 sprintf(dev->name, "pcnet#%d", dev_nr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200182
183 /*
184 * Setup the PCI device.
185 */
Paul Burtonbed1ca32016-05-26 17:32:29 +0100186 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
187 dev->iobase = pci_io_to_phys(devbusfn, bar);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200188 dev->iobase &= ~0xf;
189
Paul Burton442d2e02016-05-26 14:49:35 +0100190 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
191 dev->name, devbusfn, (unsigned long)dev->iobase);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200192
193 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
Paul Burton6011dab2013-11-08 11:18:43 +0000194 pci_write_config_word(devbusfn, PCI_COMMAND, command);
195 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200196 if ((status & command) != command) {
Paul Burton6011dab2013-11-08 11:18:43 +0000197 printf("%s: Couldn't enable IO access or Bus Mastering\n",
198 dev->name);
199 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200200 continue;
201 }
202
Paul Burton6011dab2013-11-08 11:18:43 +0000203 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200204
205 /*
206 * Probe the PCnet chip.
207 */
Paul Burton6011dab2013-11-08 11:18:43 +0000208 if (pcnet_probe(dev, bis, dev_nr) < 0) {
209 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200210 continue;
211 }
212
213 /*
214 * Setup device structure and register the driver.
215 */
216 dev->init = pcnet_init;
217 dev->halt = pcnet_halt;
218 dev->send = pcnet_send;
219 dev->recv = pcnet_recv;
220
Paul Burton6011dab2013-11-08 11:18:43 +0000221 eth_register(dev);
wdenkc6097192002-11-03 00:24:07 +0000222 }
223
Paul Burton6011dab2013-11-08 11:18:43 +0000224 udelay(10 * 1000);
wdenkc6097192002-11-03 00:24:07 +0000225
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200226 return dev_nr;
wdenkc6097192002-11-03 00:24:07 +0000227}
228
Paul Burton6011dab2013-11-08 11:18:43 +0000229static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
wdenkc6097192002-11-03 00:24:07 +0000230{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200231 int chip_version;
232 char *chipname;
233
wdenkc6097192002-11-03 00:24:07 +0000234#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200235 int i;
wdenkc6097192002-11-03 00:24:07 +0000236#endif
237
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200238 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000239 pcnet_reset(dev);
wdenkc6097192002-11-03 00:24:07 +0000240
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200241 /* Check if register access is working */
Paul Burton6011dab2013-11-08 11:18:43 +0000242 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
243 printf("%s: CSR register access check failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200244 return -1;
245 }
wdenkc6097192002-11-03 00:24:07 +0000246
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200247 /* Identify the chip */
248 chip_version =
Paul Burton6011dab2013-11-08 11:18:43 +0000249 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200250 if ((chip_version & 0xfff) != 0x003)
251 return -1;
252 chip_version = (chip_version >> 12) & 0xffff;
253 switch (chip_version) {
254 case 0x2621:
255 chipname = "PCnet/PCI II 79C970A"; /* PCI */
256 break;
wdenkc6097192002-11-03 00:24:07 +0000257#ifdef CONFIG_PCNET_79C973
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200258 case 0x2625:
259 chipname = "PCnet/FAST III 79C973"; /* PCI */
260 break;
wdenkc6097192002-11-03 00:24:07 +0000261#endif
262#ifdef CONFIG_PCNET_79C975
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200263 case 0x2627:
264 chipname = "PCnet/FAST III 79C975"; /* PCI */
265 break;
wdenkc6097192002-11-03 00:24:07 +0000266#endif
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200267 default:
Paul Burton6011dab2013-11-08 11:18:43 +0000268 printf("%s: PCnet version %#x not supported\n",
269 dev->name, chip_version);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200270 return -1;
271 }
wdenkc6097192002-11-03 00:24:07 +0000272
Paul Burton6011dab2013-11-08 11:18:43 +0000273 PCNET_DEBUG1("AMD %s\n", chipname);
wdenkc6097192002-11-03 00:24:07 +0000274
275#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200276 /*
277 * In most chips, after a chip reset, the ethernet address is read from
278 * the station address PROM at the base address and programmed into the
279 * "Physical Address Registers" CSR12-14.
280 */
281 for (i = 0; i < 3; i++) {
282 unsigned int val;
283
Paul Burton6011dab2013-11-08 11:18:43 +0000284 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200285 /* There may be endianness issues here. */
286 dev->enetaddr[2 * i] = val & 0x0ff;
287 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
288 }
wdenkc6097192002-11-03 00:24:07 +0000289#endif /* PCNET_HAS_PROM */
290
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200291 return 0;
wdenkc6097192002-11-03 00:24:07 +0000292}
293
Paul Burton6011dab2013-11-08 11:18:43 +0000294static int pcnet_init(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000295{
Paul Burtonf1ae3822014-04-07 16:41:46 +0100296 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200297 int i, val;
Paul Burton442d2e02016-05-26 14:49:35 +0100298 unsigned long addr;
wdenkc6097192002-11-03 00:24:07 +0000299
Paul Burton6011dab2013-11-08 11:18:43 +0000300 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
wdenkc6097192002-11-03 00:24:07 +0000301
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200302 /* Switch pcnet to 32bit mode */
Paul Burton6011dab2013-11-08 11:18:43 +0000303 pcnet_write_bcr(dev, 20, 2);
wdenkc6097192002-11-03 00:24:07 +0000304
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200305 /* Set/reset autoselect bit */
Paul Burton6011dab2013-11-08 11:18:43 +0000306 val = pcnet_read_bcr(dev, 2) & ~2;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200307 val |= 2;
Paul Burton6011dab2013-11-08 11:18:43 +0000308 pcnet_write_bcr(dev, 2, val);
wdenkc6097192002-11-03 00:24:07 +0000309
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200310 /* Enable auto negotiate, setup, disable fd */
Paul Burton6011dab2013-11-08 11:18:43 +0000311 val = pcnet_read_bcr(dev, 32) & ~0x98;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200312 val |= 0x20;
Paul Burton6011dab2013-11-08 11:18:43 +0000313 pcnet_write_bcr(dev, 32, val);
wdenkc6097192002-11-03 00:24:07 +0000314
wdenkc6097192002-11-03 00:24:07 +0000315 /*
Paul Burton62715a22013-11-08 11:18:46 +0000316 * Enable NOUFLO on supported controllers, with the transmit
317 * start point set to the full packet. This will cause entire
318 * packets to be buffered by the ethernet controller before
319 * transmission, eliminating underflows which are common on
320 * slower devices. Controllers which do not support NOUFLO will
321 * simply be left with a larger transmit FIFO threshold.
322 */
323 val = pcnet_read_bcr(dev, 18);
324 val |= 1 << 11;
325 pcnet_write_bcr(dev, 18, val);
326 val = pcnet_read_csr(dev, 80);
327 val |= 0x3 << 10;
328 pcnet_write_csr(dev, 80, val);
329
330 /*
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200331 * We only maintain one structure because the drivers will never
332 * be used concurrently. In 32bit mode the RX and TX ring entries
333 * must be aligned on 16-byte boundaries.
wdenkc6097192002-11-03 00:24:07 +0000334 */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200335 if (lp == NULL) {
Paul Burton442d2e02016-05-26 14:49:35 +0100336 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200337 addr = (addr + 0xf) & ~0xf;
Paul Burton6011dab2013-11-08 11:18:43 +0000338 lp = (pcnet_priv_t *)addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100339
Paul Burton442d2e02016-05-26 14:49:35 +0100340 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
341 sizeof(*lp->uc));
Paul Burtonf1ae3822014-04-07 16:41:46 +0100342 flush_dcache_range(addr, addr + sizeof(*lp->uc));
343 addr = UNCACHED_SDRAM(addr);
344 lp->uc = (struct pcnet_uncached_priv *)addr;
Paul Burtona354ddc2014-04-07 16:41:47 +0100345
Paul Burton442d2e02016-05-26 14:49:35 +0100346 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
347 sizeof(*lp->rx_buf));
Paul Burtona354ddc2014-04-07 16:41:47 +0100348 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
349 lp->rx_buf = (void *)addr;
wdenkc6097192002-11-03 00:24:07 +0000350 }
wdenkc6097192002-11-03 00:24:07 +0000351
Paul Burtonf1ae3822014-04-07 16:41:46 +0100352 uc = lp->uc;
353
354 uc->init_block.mode = cpu_to_le16(0x0000);
355 uc->init_block.filter[0] = 0x00000000;
356 uc->init_block.filter[1] = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000357
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200358 /*
359 * Initialize the Rx ring.
360 */
361 lp->cur_rx = 0;
362 for (i = 0; i < RX_RING_SIZE; i++) {
Paul Burton4677d662016-05-26 14:49:34 +0100363 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100364 uc->rx_ring[i].base = cpu_to_le32(addr);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100365 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
366 uc->rx_ring[i].status = cpu_to_le16(0x8000);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200367 PCNET_DEBUG1
368 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
Paul Burtonf1ae3822014-04-07 16:41:46 +0100369 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
370 uc->rx_ring[i].status);
wdenkc6097192002-11-03 00:24:07 +0000371 }
wdenkc6097192002-11-03 00:24:07 +0000372
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200373 /*
374 * Initialize the Tx ring. The Tx buffer address is filled in as
375 * needed, but we do need to clear the upper ownership bit.
376 */
377 lp->cur_tx = 0;
378 for (i = 0; i < TX_RING_SIZE; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100379 uc->tx_ring[i].base = 0;
380 uc->tx_ring[i].status = 0;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200381 }
382
383 /*
384 * Setup Init Block.
385 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100386 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200387
388 for (i = 0; i < 6; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100389 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
390 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200391 }
392
Paul Burtonf1ae3822014-04-07 16:41:46 +0100393 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
Paul Burton6011dab2013-11-08 11:18:43 +0000394 RX_RING_LEN_BITS);
Paul Burton4677d662016-05-26 14:49:34 +0100395 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100396 uc->init_block.rx_ring = cpu_to_le32(addr);
Paul Burton4677d662016-05-26 14:49:34 +0100397 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100398 uc->init_block.tx_ring = cpu_to_le32(addr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200399
Paul Burton6011dab2013-11-08 11:18:43 +0000400 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
Paul Burtonf1ae3822014-04-07 16:41:46 +0100401 uc->init_block.tlen_rlen,
402 uc->init_block.rx_ring, uc->init_block.tx_ring);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200403
404 /*
405 * Tell the controller where the Init Block is located.
406 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100407 barrier();
Paul Burton4677d662016-05-26 14:49:34 +0100408 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
Paul Burton6011dab2013-11-08 11:18:43 +0000409 pcnet_write_csr(dev, 1, addr & 0xffff);
410 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200411
Paul Burton6011dab2013-11-08 11:18:43 +0000412 pcnet_write_csr(dev, 4, 0x0915);
413 pcnet_write_csr(dev, 0, 0x0001); /* start */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200414
415 /* Wait for Init Done bit */
416 for (i = 10000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000417 if (pcnet_read_csr(dev, 0) & 0x0100)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200418 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000419 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200420 }
421 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000422 printf("%s: TIMEOUT: controller init failed\n", dev->name);
423 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200424 return -1;
425 }
426
427 /*
428 * Finally start network controller operation.
429 */
Paul Burton6011dab2013-11-08 11:18:43 +0000430 pcnet_write_csr(dev, 0, 0x0002);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200431
432 return 0;
wdenkc6097192002-11-03 00:24:07 +0000433}
434
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000435static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
wdenkc6097192002-11-03 00:24:07 +0000436{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200437 int i, status;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100438 u32 addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100439 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
wdenkc6097192002-11-03 00:24:07 +0000440
Paul Burton6011dab2013-11-08 11:18:43 +0000441 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
442 packet);
wdenkc6097192002-11-03 00:24:07 +0000443
Paul Burtonf3ac8662013-11-08 11:18:45 +0000444 flush_dcache_range((unsigned long)packet,
445 (unsigned long)packet + pkt_len);
446
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200447 /* Wait for completion by testing the OWN bit */
448 for (i = 1000; i > 0; i--) {
Paul Burton6fb49e42014-04-07 16:41:48 +0100449 status = readw(&entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200450 if ((status & 0x8000) == 0)
451 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000452 udelay(100);
453 PCNET_DEBUG2(".");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200454 }
455 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000456 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
457 dev->name, lp->cur_tx, status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200458 pkt_len = 0;
459 goto failure;
460 }
wdenkc6097192002-11-03 00:24:07 +0000461
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200462 /*
463 * Setup Tx ring. Caution: the write order is important here,
464 * set the status with the "ownership" bits last.
465 */
Paul Burton4677d662016-05-26 14:49:34 +0100466 addr = pcnet_virt_to_mem(dev, packet);
Paul Burton6fb49e42014-04-07 16:41:48 +0100467 writew(-pkt_len, &entry->length);
468 writel(0, &entry->misc);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100469 writel(addr, &entry->base);
Paul Burton6fb49e42014-04-07 16:41:48 +0100470 writew(0x8300, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200471
472 /* Trigger an immediate send poll. */
Paul Burton6011dab2013-11-08 11:18:43 +0000473 pcnet_write_csr(dev, 0, 0x0008);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200474
475 failure:
476 if (++lp->cur_tx >= TX_RING_SIZE)
477 lp->cur_tx = 0;
478
Paul Burton6011dab2013-11-08 11:18:43 +0000479 PCNET_DEBUG2("done\n");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200480 return pkt_len;
wdenkc6097192002-11-03 00:24:07 +0000481}
482
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200483static int pcnet_recv (struct eth_device *dev)
484{
485 struct pcnet_rx_head *entry;
Paul Burtona354ddc2014-04-07 16:41:47 +0100486 unsigned char *buf;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200487 int pkt_len = 0;
Paul Burton6fb49e42014-04-07 16:41:48 +0100488 u16 status, err_status;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200489
490 while (1) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100491 entry = &lp->uc->rx_ring[lp->cur_rx];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200492 /*
493 * If we own the next entry, it's a new packet. Send it up.
494 */
Paul Burton6fb49e42014-04-07 16:41:48 +0100495 status = readw(&entry->status);
Paul Burton6011dab2013-11-08 11:18:43 +0000496 if ((status & 0x8000) != 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200497 break;
Paul Burton6fb49e42014-04-07 16:41:48 +0100498 err_status = status >> 8;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200499
Paul Burton6fb49e42014-04-07 16:41:48 +0100500 if (err_status != 0x03) { /* There was an error. */
Paul Burton6011dab2013-11-08 11:18:43 +0000501 printf("%s: Rx%d", dev->name, lp->cur_rx);
Paul Burton6fb49e42014-04-07 16:41:48 +0100502 PCNET_DEBUG1(" (status=0x%x)", err_status);
503 if (err_status & 0x20)
Paul Burton6011dab2013-11-08 11:18:43 +0000504 printf(" Frame");
Paul Burton6fb49e42014-04-07 16:41:48 +0100505 if (err_status & 0x10)
Paul Burton6011dab2013-11-08 11:18:43 +0000506 printf(" Overflow");
Paul Burton6fb49e42014-04-07 16:41:48 +0100507 if (err_status & 0x08)
Paul Burton6011dab2013-11-08 11:18:43 +0000508 printf(" CRC");
Paul Burton6fb49e42014-04-07 16:41:48 +0100509 if (err_status & 0x04)
Paul Burton6011dab2013-11-08 11:18:43 +0000510 printf(" Fifo");
511 printf(" Error\n");
Paul Burton6fb49e42014-04-07 16:41:48 +0100512 status &= 0x03ff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200513
514 } else {
Paul Burton6fb49e42014-04-07 16:41:48 +0100515 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200516 if (pkt_len < 60) {
Paul Burton6011dab2013-11-08 11:18:43 +0000517 printf("%s: Rx%d: invalid packet length %d\n",
518 dev->name, lp->cur_rx, pkt_len);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200519 } else {
Paul Burtona354ddc2014-04-07 16:41:47 +0100520 buf = (*lp->rx_buf)[lp->cur_rx];
521 invalidate_dcache_range((unsigned long)buf,
522 (unsigned long)buf + pkt_len);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500523 net_process_received_packet(buf, pkt_len);
Paul Burton6011dab2013-11-08 11:18:43 +0000524 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
Paul Burtona354ddc2014-04-07 16:41:47 +0100525 lp->cur_rx, pkt_len, buf);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200526 }
527 }
Paul Burton6fb49e42014-04-07 16:41:48 +0100528
529 status |= 0x8000;
530 writew(status, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200531
532 if (++lp->cur_rx >= RX_RING_SIZE)
533 lp->cur_rx = 0;
534 }
535 return pkt_len;
536}
537
Paul Burton6011dab2013-11-08 11:18:43 +0000538static void pcnet_halt(struct eth_device *dev)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200539{
540 int i;
541
Paul Burton6011dab2013-11-08 11:18:43 +0000542 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200543
544 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000545 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200546
547 /* Wait for Stop bit */
548 for (i = 1000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000549 if (pcnet_read_csr(dev, 0) & 0x4)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200550 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000551 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200552 }
Paul Burton6011dab2013-11-08 11:18:43 +0000553 if (i <= 0)
554 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200555}