blob: 023736ef2b35506379977d0e0cb5bf8364aeb2de [file] [log] [blame]
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Markus Klotzbuecher090eb732006-07-12 15:26:01 +02009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020025#define CONFIG_DISPLAY_BOARDINFO
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020026
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0x40000000
28
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020029#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
31#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020032#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020033 /* (it will be used if there is no */
34 /* 'cpuclk' variable with valid value) */
35
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020036#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020037#define CONFIG_SYS_SMC_RXBUFLEN 128
38#define CONFIG_SYS_MAXIDLE 10
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020039#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
40
41#define CONFIG_BOOTCOUNT_LIMIT
42
43#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44
45#define CONFIG_BOARD_TYPES 1 /* support board types */
46
47#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010048 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020049 "echo"
50
51#undef CONFIG_BOOTARGS
52
53#define CONFIG_EXTRA_ENV_SETTINGS \
54 "netdev=eth0\0" \
55 "nfsargs=setenv bootargs root=/dev/nfs rw " \
56 "nfsroot=${serverip}:${rootpath}\0" \
57 "ramargs=setenv bootargs root=/dev/ram rw\0" \
58 "addip=setenv bootargs ${bootargs} " \
59 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
60 ":${hostname}:${netdev}:off panic=1\0" \
61 "flash_nfs=run nfsargs addip;" \
62 "bootm ${kernel_addr}\0" \
63 "flash_self=run ramargs addip;" \
64 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
66 "rootpath=/opt/eldk/ppc_8xx\0" \
Martin Krause11d9eec2007-09-26 17:55:56 +020067 "bootfile=/tftpboot/TQM885D/uImage\0" \
68 "fdt_addr=400C0000\0" \
69 "kernel_addr=40100000\0" \
70 "ramdisk_addr=40280000\0" \
71 "load=tftp 200000 ${u-boot}\0" \
72 "update=protect off 40000000 +${filesize};" \
73 "erase 40000000 +${filesize};" \
74 "cp.b 200000 40000000 ${filesize};" \
75 "protect on 40000000 +${filesize}\0" \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020076 ""
77#define CONFIG_BOOTCOMMAND "run flash_self"
78
79#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020081
82#undef CONFIG_WATCHDOG /* watchdog disabled */
83
84#define CONFIG_STATUS_LED 1 /* Status LED enabled */
85
86#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
87
88/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010089#define CONFIG_SYS_I2C
90#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
91#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
92#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
Markus Klotzbuecher090eb732006-07-12 15:26:01 +020093/*
94 * Software (bit-bang) I2C driver configuration
95 */
96#define PB_SCL 0x00000020 /* PB 26 */
97#define PB_SDA 0x00000010 /* PB 27 */
98
99#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
100#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
101#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
102#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
103#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
104 else immr->im_cpm.cp_pbdat &= ~PB_SDA
105#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
106 else immr->im_cpm.cp_pbdat &= ~PB_SCL
107#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
110#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
111#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
112#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200113
114# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200116
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500117/*
118 * BOOTP options
119 */
120#define CONFIG_BOOTP_SUBNETMASK
121#define CONFIG_BOOTP_GATEWAY
122#define CONFIG_BOOTP_HOSTNAME
123#define CONFIG_BOOTP_BOOTPATH
124#define CONFIG_BOOTP_BOOTFILESIZE
125
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200126
127#define CONFIG_MAC_PARTITION
128#define CONFIG_DOS_PARTITION
129
Martin Krause11d9eec2007-09-26 17:55:56 +0200130#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200131
132#define CONFIG_TIMESTAMP /* but print image timestmps */
133
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200134
Jon Loeliger26946902007-07-04 22:30:50 -0500135/*
136 * Command line configuration.
137 */
Jon Loeliger26946902007-07-04 22:30:50 -0500138#define CONFIG_CMD_ASKENV
139#define CONFIG_CMD_DATE
140#define CONFIG_CMD_DHCP
141#define CONFIG_CMD_EEPROM
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100142#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500143#define CONFIG_CMD_I2C
144#define CONFIG_CMD_IDE
145#define CONFIG_CMD_MII
Jon Loeliger26946902007-07-04 22:30:50 -0500146#define CONFIG_CMD_PING
147
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200148
149/*
150 * Miscellaneous configurable options
151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_LONGHELP /* undef to save memory */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200153
Wolfgang Denk2751a952006-10-28 02:29:14 +0200154#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200156
Jon Loeliger26946902007-07-04 22:30:50 -0500157#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200159#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200161#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
163#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
164#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
167#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
168#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200169 memory test.*/
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200172
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200173/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500174 * Enable loopw command.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200175 */
176#define CONFIG_LOOPW
177
178/*
179 * Low Level Configuration Settings
180 * (address mappings, register initial values, etc.)
181 * You should know what you are doing if you make changes here.
182 */
183/*-----------------------------------------------------------------------
184 * Internal Memory Mapped Register
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_IMMR 0xFFF00000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200187
188/*-----------------------------------------------------------------------
189 * Definitions for initial stack pointer and data area (in DPRAM)
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200192#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200193#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200195
196/*-----------------------------------------------------------------------
197 * Start addresses for the final memory configuration
198 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_SDRAM_BASE 0x00000000
202#define CONFIG_SYS_FLASH_BASE 0x40000000
203#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
205#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200213
214/*-----------------------------------------------------------------------
215 * FLASH organization
216 */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200217
Martin Krausee318d9e2007-09-27 11:10:08 +0200218/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200220#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
222#define CONFIG_SYS_FLASH_EMPTY_INFO
223#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
225#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200226
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200227#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200228#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
229#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
230#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200231
232/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200233#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
234#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200235
236/*-----------------------------------------------------------------------
237 * Hardware Information Block
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
240#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
241#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200242
243/*-----------------------------------------------------------------------
244 * Cache Configuration
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500247#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200249#endif
250
251/*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 11-9
253 * SYPCR can only be written once after reset!
254 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */
257#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200262#endif
263
264/*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 11-6
266 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state
268 */
269#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200271#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200273#endif /* CONFIG_CAN_DRIVER */
274
275/*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26
277 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200281
282/*-----------------------------------------------------------------------
283 * PISCR - Periodic Interrupt Status and Control 11-31
284 *-----------------------------------------------------------------------
285 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200288
289/*-----------------------------------------------------------------------
290 * SCCR - System Clock and reset Control Register 15-27
291 *-----------------------------------------------------------------------
292 * Set clock output, timebase and RTC source and divider,
293 * power management and some other internal clocks
294 */
295#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200297 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
298 SCCR_DFALCD00)
299
300/*-----------------------------------------------------------------------
301 * PCMCIA stuff
302 *-----------------------------------------------------------------------
303 *
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
306#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
307#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
308#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
309#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
310#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
311#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
312#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200313
314/*-----------------------------------------------------------------------
315 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
316 *-----------------------------------------------------------------------
317 */
318
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000319#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200320#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
321
322#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
323#undef CONFIG_IDE_LED /* LED for ide not supported */
324#undef CONFIG_IDE_RESET /* reset for ide not supported */
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
327#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200332
333/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200335
336/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200338
339/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200341
342/*-----------------------------------------------------------------------
343 *
344 *-----------------------------------------------------------------------
345 *
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_DER 0
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200348
349/*
350 * Init Memory Controller:
351 *
352 * BR0/1 and OR0/1 (FLASH)
353 */
354
355#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
356#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
357
358/* used to re-map FLASH both when starting from SRAM or FLASH:
359 * restrict access enough to keep SRAM working (if any)
360 * but not too much to meddle with FLASH accesses
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
363#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200364
365/*
366 * FLASH timing: Default value of OR0 after reset
367 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200369 OR_SCY_6_CLK | OR_TRLX)
370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
372#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
373#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
376#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
377#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200378
379/*
380 * BR2/3 and OR2/3 (SDRAM)
381 *
382 */
383#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
384#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
385#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
386
387/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200389
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
391#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200392
393#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
395#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200396#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
398#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
399#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
400#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200401 BR_PS_8 | BR_MS_UPMB | BR_V )
402#endif /* CONFIG_CAN_DRIVER */
403
404/*
405 * 4096 Rows from SDRAM example configuration
406 * 1000 factor s -> ms
407 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
408 * 4 Number of refresh cycles per period
409 * 64 Refresh cycle in ms per number of rows
410 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200412
413/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200414 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
415 *
416 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Jens Gehrlein492c7042007-09-27 14:54:46 +0200418 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
419 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
421 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
422 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
423 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Jens Gehrlein492c7042007-09-27 14:54:46 +0200424 *
425 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
426 * be met also in the default configuration, i.e. if environment variable
427 * 'cpuclk' is not set.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200428 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_MAMR_PTA 128
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200430
431/*
Jens Gehrlein492c7042007-09-27 14:54:46 +0200432 * Memory Periodic Timer Prescaler Register (MPTPR) values.
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200433 */
Jens Gehrlein492c7042007-09-27 14:54:46 +0200434/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Jens Gehrlein492c7042007-09-27 14:54:46 +0200436/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200438
439/*
440 * MAMR settings for SDRAM
441 */
442
443/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200445 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
446 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
447/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200449 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
450 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
451/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200453 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
454 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
455
456/*
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200457 * Network configuration
458 */
459#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
460#define CONFIG_FEC_ENET /* enable ethernet on FEC */
461#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
462#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
463
Jon Loeliger26946902007-07-04 22:30:50 -0500464#if defined(CONFIG_CMD_MII)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500466#define CONFIG_MII_INIT 1
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200467#endif
468
469#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
470 switching to another netwok (if the
471 tried network is unreachable) */
472
Heiko Schocher48690d82010-07-20 17:45:02 +0200473#define CONFIG_ETHPRIME "SCC"
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200474
Heiko Schocher7026ead2010-02-09 15:50:27 +0100475/* pass open firmware flat tree */
476#define CONFIG_OF_LIBFDT 1
477#define CONFIG_OF_BOARD_SETUP 1
478#define CONFIG_HWCONFIG 1
479
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200480#endif /* __CONFIG_H */