blob: dc994b748ad532dd19ef0ca5e9eb7da3569b55ea [file] [log] [blame]
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +08001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 NXP
4 *
5 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
6 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <malloc.h>
12#include <mapmem.h>
13#include <pci.h>
14#include <asm/fsl_pci.h>
15#include <asm/fsl_serdes.h>
16#include <asm/io.h>
17#include "pcie_fsl.h"
Simon Glass336d4612020-02-03 07:36:16 -070018#include <dm/device_compat.h>
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080019
20LIST_HEAD(fsl_pcie_list);
21
22static int fsl_pcie_link_up(struct fsl_pcie *pcie);
23
24static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
25{
26 struct udevice *bus = pcie->bus;
27
28 if (!pcie->enabled)
29 return -ENXIO;
30
31 if (PCI_BUS(bdf) < bus->seq)
32 return -EINVAL;
33
34 if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
35 return -EINVAL;
36
37 if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
38 return -EINVAL;
39
40 if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
41 return -EINVAL;
42
43 return 0;
44}
45
Simon Glassc4e72c42020-01-27 08:49:37 -070046static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080047 uint offset, ulong *valuep,
48 enum pci_size_t size)
49{
50 struct fsl_pcie *pcie = dev_get_priv(bus);
51 ccsr_fsl_pci_t *regs = pcie->regs;
52 u32 val;
53
54 if (fsl_pcie_addr_valid(pcie, bdf)) {
55 *valuep = pci_get_ff(size);
56 return 0;
57 }
58
59 bdf = bdf - PCI_BDF(bus->seq, 0, 0);
60 val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
61 out_be32(&regs->cfg_addr, val);
62
63 sync();
64
65 switch (size) {
66 case PCI_SIZE_8:
67 *valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
68 break;
69 case PCI_SIZE_16:
70 *valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
71 (offset & 2)));
72 break;
73 case PCI_SIZE_32:
74 *valuep = in_le32(&regs->cfg_data);
75 break;
76 }
77
78 return 0;
79}
80
81static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
82 uint offset, ulong value,
83 enum pci_size_t size)
84{
85 struct fsl_pcie *pcie = dev_get_priv(bus);
86 ccsr_fsl_pci_t *regs = pcie->regs;
87 u32 val;
88 u8 val_8;
89 u16 val_16;
90 u32 val_32;
91
92 if (fsl_pcie_addr_valid(pcie, bdf))
93 return 0;
94
95 bdf = bdf - PCI_BDF(bus->seq, 0, 0);
96 val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
97 out_be32(&regs->cfg_addr, val);
98
99 sync();
100
101 switch (size) {
102 case PCI_SIZE_8:
103 val_8 = value;
104 out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
105 break;
106 case PCI_SIZE_16:
107 val_16 = value;
108 out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
109 break;
110 case PCI_SIZE_32:
111 val_32 = value;
112 out_le32(&regs->cfg_data, val_32);
113 break;
114 }
115
116 return 0;
117}
118
119static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
120 ulong *valuep, enum pci_size_t size)
121{
122 int ret;
123 struct udevice *bus = pcie->bus;
124
125 ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
126 offset, valuep, size);
127
128 return ret;
129}
130
131static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
132 ulong value, enum pci_size_t size)
133{
134 struct udevice *bus = pcie->bus;
135
136 return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
137 offset, value, size);
138}
139
140static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
141 u8 *valuep)
142{
143 ulong val;
144 int ret;
145
146 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
147 *valuep = val;
148
149 return ret;
150}
151
152static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
153 u16 *valuep)
154{
155 ulong val;
156 int ret;
157
158 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
159 *valuep = val;
160
161 return ret;
162}
163
164static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
165 u32 *valuep)
166{
167 ulong val;
168 int ret;
169
170 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
171 *valuep = val;
172
173 return ret;
174}
175
176static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
177 u8 value)
178{
179 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
180}
181
182static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
183 u16 value)
184{
185 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
186}
187
188static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
189 u32 value)
190{
191 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
192}
193
194static int fsl_pcie_link_up(struct fsl_pcie *pcie)
195{
196 ccsr_fsl_pci_t *regs = pcie->regs;
197 u16 ltssm;
198
199 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
200 ltssm = (in_be32(&regs->pex_csr0)
201 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
202 return ltssm == LTSSM_L0_REV3;
203 }
204
205 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
206
207 return ltssm == LTSSM_L0;
208}
209
210static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
211{
212 u8 header_type;
213
214 fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
215
216 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
217}
218
219static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
220{
221 struct pci_region *io, *mem, *pref;
222
223 pci_get_regions(pcie->bus, &io, &mem, &pref);
224
225 if (mem)
226 set_next_law(mem->phys_start,
227 law_size_bits(mem->size),
228 pcie->law_trgt_if);
229
230 if (io)
231 set_next_law(io->phys_start,
232 law_size_bits(io->size),
233 pcie->law_trgt_if);
234
235 return 0;
236}
237
238static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
239{
240 ccsr_fsl_pci_t *regs = pcie->regs;
241
242 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
243 setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
244 return;
245 }
246
247 fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
248}
249
250static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
251 int type, u64 phys, u64 bus_addr,
252 pci_size_t size)
253{
254 ccsr_fsl_pci_t *regs = pcie->regs;
255 pot_t *po = &regs->pot[idx];
256 u32 war, sz;
257
258 if (idx < 0)
259 return -EINVAL;
260
261 out_be32(&po->powbar, phys >> 12);
262 out_be32(&po->potar, bus_addr >> 12);
263#ifdef CONFIG_SYS_PCI_64BIT
264 out_be32(&po->potear, bus_addr >> 44);
265#else
266 out_be32(&po->potear, 0);
267#endif
268
269 sz = (__ilog2_u64((u64)size) - 1);
270 war = POWAR_EN | sz;
271
272 if (type == PCI_REGION_IO)
273 war |= POWAR_IO_READ | POWAR_IO_WRITE;
274 else
275 war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
276
277 out_be32(&po->powar, war);
278
279 return 0;
280}
281
282static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
283 bool pf, u64 phys, u64 bus_addr,
284 pci_size_t size)
285{
286 ccsr_fsl_pci_t *regs = pcie->regs;
287 pit_t *pi = &regs->pit[idx];
288 u32 sz = (__ilog2_u64(size) - 1);
289 u32 flag = PIWAR_LOCAL;
290
291 if (idx < 0)
292 return -EINVAL;
293
294 out_be32(&pi->pitar, phys >> 12);
295 out_be32(&pi->piwbar, bus_addr >> 12);
296
297#ifdef CONFIG_SYS_PCI_64BIT
298 out_be32(&pi->piwbear, bus_addr >> 44);
299#else
300 out_be32(&pi->piwbear, 0);
301#endif
302
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000303#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
304 flag = 0;
305#endif
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800306
307 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
308 if (pf)
309 flag |= PIWAR_PF;
310 out_be32(&pi->piwar, flag | sz);
311
312 return 0;
313}
314
315static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
316{
317 struct pci_region *io, *mem, *pref;
318 int idx = 1; /* skip 0 */
319
320 pci_get_regions(pcie->bus, &io, &mem, &pref);
321
322 if (io)
323 /* ATU : OUTBOUND : IO */
324 fsl_pcie_setup_outbound_win(pcie, idx++,
325 PCI_REGION_IO,
326 io->phys_start,
327 io->bus_start,
328 io->size);
329
330 if (mem)
331 /* ATU : OUTBOUND : MEM */
332 fsl_pcie_setup_outbound_win(pcie, idx++,
333 PCI_REGION_MEM,
334 mem->phys_start,
335 mem->bus_start,
336 mem->size);
337 return 0;
338}
339
340static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
341{
342 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
343 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
344 u64 sz = min((u64)gd->ram_size, (1ull << 32));
345 pci_size_t pci_sz;
346 int idx;
347
348 if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
349 idx = 2;
350 else
351 idx = 3;
352
353 pci_sz = 1ull << __ilog2_u64(sz);
354
355 dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
356 (u64)bus_start, (u64)phys_start, (u64)sz);
357
358 /* if we aren't an exact power of two match, pci_sz is smaller
359 * round it up to the next power of two. We report the actual
360 * size to pci region tracking.
361 */
362 if (pci_sz != sz)
363 sz = 2ull << __ilog2_u64(sz);
364
365 fsl_pcie_setup_inbound_win(pcie, idx--, true,
366 CONFIG_SYS_PCI_MEMORY_PHYS,
367 CONFIG_SYS_PCI_MEMORY_BUS, sz);
368#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
369 /*
370 * On 64-bit capable systems, set up a mapping for all of DRAM
371 * in high pci address space.
372 */
373 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
374 /* round up to the next largest power of two */
375 if (gd->ram_size > pci_sz)
376 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
377
378 dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
379 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
380 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
381
382 fsl_pcie_setup_inbound_win(pcie, idx--, true,
383 CONFIG_SYS_PCI_MEMORY_PHYS,
384 CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
385#endif
386
387 return 0;
388}
389
390static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
391{
392 fsl_pcie_setup_outbound_wins(pcie);
393 fsl_pcie_setup_inbound_wins(pcie);
394
395 return 0;
396}
397
398static int fsl_pcie_init_port(struct fsl_pcie *pcie)
399{
400 ccsr_fsl_pci_t *regs = pcie->regs;
401 u32 val_32;
402 u16 val_16;
403
404 fsl_pcie_init_atmu(pcie);
405
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000406#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
407 val_32 = 0;
408 fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
409 val_32 &= ~0x03;
410 fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
411 udelay(1);
412#endif
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800413
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000414#ifdef CONFIG_FSL_PCIE_RESET
415 u16 ltssm;
416 int i;
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800417
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000418 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
419 /* assert PCIe reset */
420 setbits_be32(&regs->pdb_stat, 0x08000000);
421 (void)in_be32(&regs->pdb_stat);
422 udelay(1000);
423 /* clear PCIe reset */
424 clrbits_be32(&regs->pdb_stat, 0x08000000);
425 asm("sync;isync");
426 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
427 udelay(1000);
428 } else {
429 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
430 if (ltssm == 1) {
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800431 /* assert PCIe reset */
432 setbits_be32(&regs->pdb_stat, 0x08000000);
433 (void)in_be32(&regs->pdb_stat);
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000434 udelay(100);
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800435 /* clear PCIe reset */
436 clrbits_be32(&regs->pdb_stat, 0x08000000);
437 asm("sync;isync");
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000438 for (i = 0; i < 100 &&
439 !fsl_pcie_link_up(pcie); i++)
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800440 udelay(1000);
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800441 }
442 }
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000443#endif
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800444
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000445#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
446 if (!fsl_pcie_link_up(pcie)) {
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800447 serdes_corenet_t *srds_regs;
448
449 srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
450 val_32 = in_be32(&srds_regs->srdspccr0);
451
452 if ((val_32 >> 28) == 3) {
453 int i;
454
455 out_be32(&srds_regs->srdspccr0, 2 << 28);
456 setbits_be32(&regs->pdb_stat, 0x08000000);
457 in_be32(&regs->pdb_stat);
458 udelay(100);
459 clrbits_be32(&regs->pdb_stat, 0x08000000);
460 asm("sync;isync");
461 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
462 udelay(1000);
463 }
464 }
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000465#endif
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800466
467 /*
468 * The Read-Only Write Enable bit defaults to 1 instead of 0.
469 * Set to 0 to protect the read-only registers.
470 */
Hou Zhiqiangadc983b2019-08-27 10:13:48 +0000471#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
472 clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
473#endif
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800474
475 /*
476 * Enable All Error Interrupts except
477 * - Master abort (pci)
478 * - Master PERR (pci)
479 * - ICCA (PCIe)
480 */
481 out_be32(&regs->peer, ~0x20140);
482
483 /* set URR, FER, NFER (but not CER) */
484 fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
485 val_32 |= 0xf000e;
486 fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
487
488 /* Clear all error indications */
489 out_be32(&regs->pme_msg_det, 0xffffffff);
490 out_be32(&regs->pme_msg_int_en, 0xffffffff);
491 out_be32(&regs->pedr, 0xffffffff);
492
493 fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
494 if (val_16)
495 fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
496
497 fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
498 if (val_16)
499 fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
500
501 return 0;
502}
503
504static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
505{
506 ccsr_fsl_pci_t *regs = pcie->regs;
Hou Zhiqiangd18d06a2019-08-27 10:13:51 +0000507 u32 classcode_reg;
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800508 u32 val;
509
Hou Zhiqiangd18d06a2019-08-27 10:13:51 +0000510 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
511 classcode_reg = PCI_CLASS_REVISION;
512 setbits_be32(&regs->dbi_ro_wr_en, 0x01);
513 } else {
514 classcode_reg = CSR_CLASSCODE;
515 }
516
517 fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800518 val &= 0xff;
519 val |= PCI_CLASS_BRIDGE_PCI << 16;
Hou Zhiqiangd18d06a2019-08-27 10:13:51 +0000520 fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
521
522 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
523 clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800524
525 return 0;
526}
527
528static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
529{
530 return fsl_pcie_fixup_classcode(pcie);
531}
532
533static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
534{
535 fsl_pcie_config_ready(pcie);
536
537 return 0;
538}
539
540static int fsl_pcie_probe(struct udevice *dev)
541{
542 struct fsl_pcie *pcie = dev_get_priv(dev);
543 ccsr_fsl_pci_t *regs = pcie->regs;
544 u16 val_16;
545
546 pcie->bus = dev;
547 pcie->block_rev = in_be32(&regs->block_rev1);
548
549 list_add(&pcie->list, &fsl_pcie_list);
550 pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
551 if (!pcie->enabled) {
552 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
553 return 0;
554 }
555
556 fsl_pcie_setup_law(pcie);
557
558 pcie->mode = fsl_pcie_is_agent(pcie);
559
560 fsl_pcie_init_port(pcie);
561
562 printf("PCIe%d: %s ", pcie->idx, dev->name);
563
564 if (pcie->mode) {
565 printf("Endpoint");
566 fsl_pcie_init_ep(pcie);
567 } else {
568 printf("Root Complex");
569 fsl_pcie_init_rc(pcie);
570 }
571
572 if (!fsl_pcie_link_up(pcie)) {
573 printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
574 return 0;
575 }
576
577 fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
578 printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
579
580 return 0;
581}
582
583static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
584{
585 struct fsl_pcie *pcie = dev_get_priv(dev);
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +0000586 struct fsl_pcie_data *info;
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800587 int ret;
588
589 pcie->regs = dev_remap_addr(dev);
590 if (!pcie->regs) {
591 pr_err("\"reg\" resource not found\n");
592 return -EINVAL;
593 }
594
595 ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
596 if (ret < 0) {
597 pr_err("\"law_trgt_if\" not found\n");
598 return ret;
599 }
600
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +0000601 info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
602 pcie->info = info;
603 pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
604 info->block_offset) / info->stride;
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800605
606 return 0;
607}
608
609static const struct dm_pci_ops fsl_pcie_ops = {
610 .read_config = fsl_pcie_read_config,
611 .write_config = fsl_pcie_write_config,
612};
613
Hou Zhiqiangba827362019-08-27 11:04:01 +0000614static struct fsl_pcie_data p1_p2_data = {
615 .block_offset = 0xa000,
616 .block_offset_mask = 0xffff,
617 .stride = 0x1000,
618};
619
Hou Zhiqiang1a928022019-08-27 11:04:25 +0000620static struct fsl_pcie_data p2041_data = {
621 .block_offset = 0x200000,
622 .block_offset_mask = 0x3fffff,
623 .stride = 0x1000,
624};
625
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +0000626static struct fsl_pcie_data t2080_data = {
627 .block_offset = 0x240000,
628 .block_offset_mask = 0x3fffff,
629 .stride = 0x10000,
630};
631
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800632static const struct udevice_id fsl_pcie_ids[] = {
Hou Zhiqiang92e025c2019-08-27 11:05:19 +0000633 { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
Hou Zhiqiangba827362019-08-27 11:04:01 +0000634 { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
Hou Zhiqiang1a928022019-08-27 11:04:25 +0000635 { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
Hou Zhiqiang096d5f82019-08-27 11:04:39 +0000636 { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
Hou Zhiqiang7b7e4e12019-08-27 11:04:52 +0000637 { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
Hou Zhiqiang52744592019-08-27 11:05:02 +0000638 { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
Hou Zhiqianga8c79f62019-08-27 11:03:24 +0000639 { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
Hou Zhiqiang4392ddb2019-08-27 11:03:44 +0000640 { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +0000641 { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
Hou Zhiqiang9acc0382019-08-27 11:03:06 +0000642 { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +0800643 { }
644};
645
646U_BOOT_DRIVER(fsl_pcie) = {
647 .name = "fsl_pcie",
648 .id = UCLASS_PCI,
649 .of_match = fsl_pcie_ids,
650 .ops = &fsl_pcie_ops,
651 .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
652 .probe = fsl_pcie_probe,
653 .priv_auto_alloc_size = sizeof(struct fsl_pcie),
654};