blob: 5b134aa47c2492022346847290b3156875891bb2 [file] [log] [blame]
TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
TsiChung Liew536e7da2008-10-22 11:38:21 +00005 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
TsiChung Liew8e585f02007-06-18 13:50:13 -05008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -060028#include <timestamp.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050029#include "version.h"
30
31#ifndef CONFIG_IDENT_STRING
32#define CONFIG_IDENT_STRING ""
33#endif
34
35#define _START _start
36#define _FAULT _fault
37
TsiChung Liew8e585f02007-06-18 13:50:13 -050038#define SAVE_ALL \
39 move.w #0x2700,%sr; /* disable intrs */ \
40 subl #60,%sp; /* space for 15 regs */ \
41 moveml %d0-%d7/%a0-%a6,%sp@;
42
43#define RESTORE_ALL \
44 moveml %sp@,%d0-%d7/%a0-%a6; \
45 addl #60,%sp; /* space for 15 regs */ \
46 rte;
47
Wolfgang Wegnerc7de8102010-03-02 10:59:20 +010048#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChung Liew8e585f02007-06-18 13:50:13 -050049.text
50/*
51 * Vector table. This is used for initial platform startup.
52 * These vectors are to catch any un-intended traps.
53 */
54_vectors:
55
TsiChungLiewddd104f2007-07-05 23:06:55 -050056INITSP: .long 0x00000000 /* Initial SP */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020057INITPC: .long _START /* Initial PC */
TsiChungLiewddd104f2007-07-05 23:06:55 -050058vector02: .long _FAULT /* Access Error */
59vector03: .long _FAULT /* Address Error */
60vector04: .long _FAULT /* Illegal Instruction */
61vector05: .long _FAULT /* Reserved */
62vector06: .long _FAULT /* Reserved */
63vector07: .long _FAULT /* Reserved */
64vector08: .long _FAULT /* Privilege Violation */
65vector09: .long _FAULT /* Trace */
66vector0A: .long _FAULT /* Unimplemented A-Line */
67vector0B: .long _FAULT /* Unimplemented F-Line */
68vector0C: .long _FAULT /* Debug Interrupt */
69vector0D: .long _FAULT /* Reserved */
70vector0E: .long _FAULT /* Format Error */
71vector0F: .long _FAULT /* Unitialized Int. */
TsiChung Liew8e585f02007-06-18 13:50:13 -050072
TsiChungLiewddd104f2007-07-05 23:06:55 -050073/* Reserved */
TsiChung Liew8e585f02007-06-18 13:50:13 -050074vector10_17:
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76
TsiChungLiewddd104f2007-07-05 23:06:55 -050077vector18: .long _FAULT /* Spurious Interrupt */
78vector19: .long _FAULT /* Autovector Level 1 */
79vector1A: .long _FAULT /* Autovector Level 2 */
80vector1B: .long _FAULT /* Autovector Level 3 */
81vector1C: .long _FAULT /* Autovector Level 4 */
82vector1D: .long _FAULT /* Autovector Level 5 */
83vector1E: .long _FAULT /* Autovector Level 6 */
84vector1F: .long _FAULT /* Autovector Level 7 */
TsiChung Liew8e585f02007-06-18 13:50:13 -050085
86/* TRAP #0 - #15 */
87vector20_2F:
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90
91/* Reserved */
92vector30_3F:
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95
96vector64_127:
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
105
106vector128_191:
107.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115
116vector192_255:
117.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
121.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
124.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
Wolfgang Wegnerc7de8102010-03-02 10:59:20 +0100125#endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500126
127 .text
128
129 .globl _start
130_start:
131 nop
132 nop
TsiChungLiewddd104f2007-07-05 23:06:55 -0500133 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500134
Wolfgang Wegnerc7de8102010-03-02 10:59:20 +0100135#if !defined(CONFIG_MONITOR_IS_IN_RAM)
TsiChungLiewddd104f2007-07-05 23:06:55 -0500136 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500138 movec %d0, %VBR
Wolfgang Wegnerc7de8102010-03-02 10:59:20 +0100139#endif
TsiChung Liew8e585f02007-06-18 13:50:13 -0500140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiewc67e12e2007-10-25 17:12:36 -0500142 movec %d0, %RAMBAR1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500143
144 /* invalidate and disable cache */
145 move.l #0x01000000, %d0 /* Invalidate cache cmd */
146 movec %d0, %CACR /* Invalidate cache */
147 move.l #0, %d0
148 movec %d0, %ACR0
149 movec %d0, %ACR1
150
TsiChung Liew536e7da2008-10-22 11:38:21 +0000151#ifdef CONFIG_MCF5301x
152 move.l #(0xFC0a0010), %a0
153 move.w (%a0), %d0
154 and.l %d0, 0xEFFF
155
156 move.w %d0, (%a0)
157#endif
158
TsiChung Liew8e585f02007-06-18 13:50:13 -0500159 /* initialize general use internal ram */
160 move.l #0, %d0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
162 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
TsiChung Liew8e585f02007-06-18 13:50:13 -0500163 move.l %d0, (%a1)
164 move.l %d0, (%a2)
165
TsiChungLiewddd104f2007-07-05 23:06:55 -0500166 /* set stackpointer to end of internal ram to get some stackspace for the
167 first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChung Liew8e585f02007-06-18 13:50:13 -0500169 clr.l %sp@-
170
TsiChungLiewddd104f2007-07-05 23:06:55 -0500171 move.l #__got_start, %a5 /* put relocation table address to a5 */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500172
TsiChungLiewddd104f2007-07-05 23:06:55 -0500173 bsr cpu_init_f /* run low-level CPU init code (from flash) */
174 bsr board_init_f /* run low-level board init code (from flash) */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500175
176 /* board_init_f() does not return */
177
178/*------------------------------------------------------------------------------*/
179
180/*
181 * void relocate_code (addr_sp, gd, addr_moni)
182 *
183 * This "function" does not return, instead it continues in RAM
184 * after relocating the monitor code.
185 *
186 * r3 = dest
187 * r4 = src
188 * r5 = length in bytes
189 * r6 = cachelinesize
190 */
191 .globl relocate_code
192relocate_code:
193 link.w %a6,#0
194 move.l 8(%a6), %sp /* set new stack pointer */
195
196 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
197 move.l 16(%a6), %a0 /* Save copy of Destination Address */
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500200 move.l #__init_end, %a2
201 move.l %a0, %a3
202
203 /* copy the code to RAM */
2041:
205 move.l (%a1)+, (%a3)+
206 cmp.l %a1,%a2
207 bgt.s 1b
208
209/*
210 * We are done. Do not return, instead branch to second part of board
211 * initialization, now running from RAM.
212 */
213 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500215 jmp (%a1)
216
217in_ram:
218
219clear_bss:
220 /*
221 * Now clear BSS segment
222 */
223 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500225 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChung Liew8e585f02007-06-18 13:50:13 -05002276:
228 clr.l (%a1)+
229 cmp.l %a1,%d1
230 bgt.s 6b
231
232 /*
233 * fix got table in RAM
234 */
235 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500237 move.l %a1,%a5 /* * fix got pointer register a5 */
238
239 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChung Liew8e585f02007-06-18 13:50:13 -0500241
2427:
243 move.l (%a1),%d1
244 sub.l #_start,%d1
245 add.l %a0,%d1
246 move.l %d1,(%a1)+
247 cmp.l %a2, %a1
248 bne 7b
249
250 /* calculate relative jump to board_init_r in ram */
251 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500253
254 /* set parameters for board_init_r */
255 move.l %a0,-(%sp) /* dest_addr */
256 move.l %d0,-(%sp) /* gd */
257 jsr (%a1)
258
259/*------------------------------------------------------------------------------*/
260/* exception code */
261 .globl _fault
262_fault:
263 jmp _fault
264 .globl _exc_handler
265
266_exc_handler:
267 SAVE_ALL
268 movel %sp,%sp@-
269 bsr exc_handler
270 addql #4,%sp
271 RESTORE_ALL
272
273 .globl _int_handler
274_int_handler:
275 SAVE_ALL
276 movel %sp,%sp@-
277 bsr int_handler
278 addql #4,%sp
279 RESTORE_ALL
280
281/*------------------------------------------------------------------------------*/
282/* cache functions */
283 .globl icache_enable
284icache_enable:
285 move.l #0x01000000, %d0 /* Invalidate cache cmd */
286 movec %d0, %CACR /* Invalidate cache */
Wolfgang Wegner992d7122009-10-28 15:11:00 -0500287 move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0) << 11)), %d0
TsiChung Liew8e585f02007-06-18 13:50:13 -0500288 movec %d0, %ACR0 /* Enable cache */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500289
TsiChungLiewddd104f2007-07-05 23:06:55 -0500290 move.l #0x80000200, %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500291 movec %d0, %CACR /* Enable cache */
TsiChungLiewddd104f2007-07-05 23:06:55 -0500292 nop
TsiChung Liew8e585f02007-06-18 13:50:13 -0500293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500295 moveq #1, %d0
296 move.l %d0, (%a1)
297 rts
298
299 .globl icache_disable
300icache_disable:
TsiChung0dca8742007-07-10 15:45:43 -0500301 move.l #0x01000000, %d0 /* Setup cache mask */
302 movec %d0, %CACR /* Disable cache */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500303 clr.l %d0 /* Setup cache mask */
TsiChung0dca8742007-07-10 15:45:43 -0500304 movec %d0, %ACR0
305 movec %d0, %ACR1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500308 moveq #0, %d0
309 move.l %d0, (%a1)
310 rts
311
312 .globl icache_status
313icache_status:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500315 move.l (%a1), %d0
316 rts
317
318 .globl icache_invalid
319icache_invalid:
TsiChung0dca8742007-07-10 15:45:43 -0500320 move.l #0x81000200, %d0 /* Setup cache mask */
TsiChung Liew8e585f02007-06-18 13:50:13 -0500321 movec %d0, %CACR /* Enable cache */
322 rts
323
324 .globl dcache_enable
325dcache_enable:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500327 moveq #1, %d0
328 move.l %d0, (%a1)
329 rts
330
331 /* No dcache, just a dummy function */
332 .globl dcache_disable
333dcache_disable:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500335 moveq #0, %d0
336 move.l %d0, (%a1)
337 rts
338
339 .globl dcache_status
340dcache_status:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
TsiChung Liew8e585f02007-06-18 13:50:13 -0500342 move.l (%a1), %d0
343 rts
344
345/*------------------------------------------------------------------------------*/
346
347 .globl version_string
348version_string:
349 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600350 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
TsiChung Liew8e585f02007-06-18 13:50:13 -0500351 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500352 .align 4