blob: ae6bc656d94ffbcb55a77df79026915b55bebe09 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbellcba69ee2014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 *
5 * (C) Copyright 2007-2011
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
8 *
9 * Some init for sunxi platform.
Ian Campbellcba69ee2014-05-05 11:52:26 +010010 */
11
12#include <common.h>
Simon Glass9edefc22019-11-14 12:57:37 -070013#include <cpu_func.h>
Simon Glass691d7192020-05-10 11:40:02 -060014#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060015#include <log.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020016#include <mmc.h>
Hans de Goede66203772014-06-13 22:55:49 +020017#include <i2c.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010018#include <serial.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010019#include <spl.h>
Simon Glass90526e92020-05-10 11:39:56 -060020#include <asm/cache.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010021#include <asm/gpio.h>
22#include <asm/io.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
Bernhard Nortmannaf654d12015-09-17 18:52:52 +020025#include <asm/arch/spl.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010026#include <asm/arch/sys_proto.h>
27#include <asm/arch/timer.h>
Chen-Yu Tsai92369842015-08-25 10:49:19 +080028#include <asm/arch/tzpc.h>
Daniel Kochmańskia1514032015-05-29 16:55:42 +020029#include <asm/arch/mmc.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010030
Ian Campbell799aff32014-07-06 20:03:20 +010031#include <linux/compiler.h>
32
Simon Glass942cb0b2015-02-07 10:47:30 -070033struct fel_stash {
34 uint32_t sp;
35 uint32_t lr;
Siarhei Siamashka840fe952015-02-16 10:23:59 +020036 uint32_t cpsr;
37 uint32_t sctlr;
38 uint32_t vbar;
39 uint32_t cr;
Simon Glass942cb0b2015-02-07 10:47:30 -070040};
41
42struct fel_stash fel_stash __attribute__((section(".data")));
43
Andre Przywarace6912e2017-02-16 01:20:24 +000044#ifdef CONFIG_ARM64
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020045#include <asm/armv8/mmu.h>
46
47static struct mm_region sunxi_mem_map[] = {
48 {
49 /* SRAM, MMIO regions */
York Suncd4b0c52016-06-24 16:46:22 -070050 .virt = 0x0UL,
51 .phys = 0x0UL,
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020052 .size = 0x40000000UL,
53 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
54 PTE_BLOCK_NON_SHARE
55 }, {
56 /* RAM */
York Suncd4b0c52016-06-24 16:46:22 -070057 .virt = 0x40000000UL,
58 .phys = 0x40000000UL,
Icenowy Zheng70091342018-10-25 17:23:05 +080059 .size = 0xC0000000UL,
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020060 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
61 PTE_BLOCK_INNER_SHARE
62 }, {
63 /* List terminator */
64 0,
65 }
66};
67struct mm_region *mem_map = sunxi_mem_map;
68#endif
69
Simon Glassf6309742014-12-23 12:04:52 -070070static int gpio_init(void)
Ian Campbellcba69ee2014-05-05 11:52:26 +010071{
Icenowy Zheng5f19c932019-04-24 13:44:12 +080072 __maybe_unused uint val;
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080073#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
Chen-Yu Tsai379feba2016-11-30 14:57:32 +080074#if defined(CONFIG_MACH_SUN4I) || \
75 defined(CONFIG_MACH_SUN7I) || \
76 defined(CONFIG_MACH_SUN8I_R40)
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080077 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
78 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
79 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
80#endif
Chen-Yu Tsai379feba2016-11-30 14:57:32 +080081#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080082 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
83 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010084#else
Chen-Yu Tsai6ad8c742015-06-23 19:57:23 +080085 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
86 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
Paul Kocialkowski487b3272015-03-22 18:12:22 +010087#endif
Chen-Yu Tsaiff2b47f2014-10-22 16:47:42 +080088 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
Chen-Yu Tsai379feba2016-11-30 14:57:32 +080089#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
90 defined(CONFIG_MACH_SUN7I) || \
91 defined(CONFIG_MACH_SUN8I_R40))
Paul Kocialkowski487b3272015-03-22 18:12:22 +010092 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080094 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010095#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +010096 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +080098 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +010099#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100100 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
Maxime Ripard77115392014-10-03 20:16:28 +0800102 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
Chen-Yu Tsaie5068892015-06-23 19:57:25 +0800103#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
104 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
106 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Andre Przywara7b82a222017-02-16 01:20:27 +0000107#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100108 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
110 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200111#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
114 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
Icenowy Zheng7f51a402018-07-21 16:20:28 +0800115#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
118 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
Jernej Skrabecc13d98b2021-01-11 21:11:41 +0100119#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
122 sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
vishnupatekard5a33572015-11-29 01:07:20 +0800123#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
124 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
125 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
126 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
Icenowy Zhengc1994892017-04-08 15:30:12 +0800127#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
128 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
129 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
130 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
Hans de Goede1871a8c2015-01-13 19:25:06 +0100131#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
132 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
133 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
134 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +0100135#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100136 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
137 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
Chen-Yu Tsaiea520942014-10-03 20:16:21 +0800138 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
Laurent Itti5cd83b112015-05-05 17:02:00 -0700139#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
140 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
141 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
142 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Ian Campbelled41e622014-10-24 21:20:47 +0100143#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100144 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
145 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
Chen-Yu Tsaic757a502014-10-22 16:47:47 +0800146 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
Hans de Goedef84269c2014-06-09 11:36:58 +0200147#else
148#error Unsupported console port number. Please fix pin mux settings in board.c
149#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100150
Jernej Skrabec44726092021-01-11 21:11:34 +0100151#ifdef CONFIG_SUN50I_GEN_H6
Icenowy Zheng5f19c932019-04-24 13:44:12 +0800152 /* Update PIO power bias configuration by copy hardware detected value */
153 val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
154 writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
155 val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
156 writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
157#endif
158
Ian Campbellcba69ee2014-05-05 11:52:26 +0100159 return 0;
160}
161
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000162#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
Simon Glass2a2ee2a2016-09-24 18:20:13 -0600163static int spl_board_load_image(struct spl_image_info *spl_image,
164 struct spl_boot_device *bootdev)
Simon Glass942cb0b2015-02-07 10:47:30 -0700165{
166 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
167 return_to_fel(fel_stash.sp, fel_stash.lr);
Nikita Kiryanov36afd452015-11-08 17:11:49 +0200168
169 return 0;
Simon Glass942cb0b2015-02-07 10:47:30 -0700170}
Simon Glassebc4ef62016-11-30 15:30:50 -0700171SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
Simon Glass97d9df02016-09-24 18:20:12 -0600172#endif
Simon Glass942cb0b2015-02-07 10:47:30 -0700173
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100174void s_init(void)
Simon Glassf6309742014-12-23 12:04:52 -0700175{
Hans de Goede583fede2016-03-04 10:57:34 +0100176 /*
177 * Undocumented magic taken from boot0, without this DRAM
178 * access gets messed up (seems cache related).
179 * The boot0 sources describe this as: "config ema for cache sram"
180 */
181#if defined CONFIG_MACH_SUN6I
Simon Glassf6309742014-12-23 12:04:52 -0700182 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
Hans de Goede5f8afd72016-03-24 22:37:08 +0100183#elif defined CONFIG_MACH_SUN8I
184 __maybe_unused uint version;
Hans de Goede583fede2016-03-04 10:57:34 +0100185
186 /* Unlock sram version info reg, read it, relock */
187 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
Hans de Goede5f8afd72016-03-24 22:37:08 +0100188 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
Hans de Goede583fede2016-03-04 10:57:34 +0100189 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
190
Hans de Goede5f8afd72016-03-24 22:37:08 +0100191 /*
192 * Ideally this would be a switch case, but we do not know exactly
193 * which versions there are and which version needs which settings,
194 * so reproduce the per SoC code from the BSP.
195 */
196#if defined CONFIG_MACH_SUN8I_A23
197 if (version == 0x1650)
Hans de Goede583fede2016-03-04 10:57:34 +0100198 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
199 else /* 0x1661 ? */
200 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
Hans de Goede5f8afd72016-03-24 22:37:08 +0100201#elif defined CONFIG_MACH_SUN8I_A33
202 if (version != 0x1667)
203 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
204#endif
205 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
206 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
Simon Glassf6309742014-12-23 12:04:52 -0700207#endif
Hans de Goede583fede2016-03-04 10:57:34 +0100208
Andre Przywara85db5832017-02-16 01:20:21 +0000209#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
Simon Glassf6309742014-12-23 12:04:52 -0700210 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
211 asm volatile(
212 "mrc p15, 0, r0, c1, c0, 1\n"
213 "orr r0, r0, #1 << 6\n"
Andre Przywara1afd0f62017-02-16 01:20:18 +0000214 "mcr p15, 0, r0, c1, c0, 1\n"
215 ::: "r0");
Simon Glassf6309742014-12-23 12:04:52 -0700216#endif
Chen-Yu Tsai58236642016-01-06 15:13:06 +0800217#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
218 /* Enable non-secure access to some peripherals */
Chen-Yu Tsai92369842015-08-25 10:49:19 +0800219 tzpc_init();
220#endif
Simon Glassf6309742014-12-23 12:04:52 -0700221
222 clock_init();
223 timer_init();
224 gpio_init();
Jernej Skrabeca8f01cc2017-04-27 00:03:36 +0200225#ifndef CONFIG_DM_I2C
Simon Glassf6309742014-12-23 12:04:52 -0700226 i2c_init_board();
Jernej Skrabeca8f01cc2017-04-27 00:03:36 +0200227#endif
Hans de Goedefc8991c2016-03-17 13:53:03 +0100228 eth_init_board();
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100229}
Simon Glassf6309742014-12-23 12:04:52 -0700230
Andre Przywaraee98d762020-01-10 01:47:31 +0000231#define SUNXI_INVALID_BOOT_SOURCE -1
232
233static int sunxi_get_boot_source(void)
234{
235 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
236 return SUNXI_INVALID_BOOT_SOURCE;
237
238 return readb(SPL_ADDR + 0x28);
239}
240
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100241/* The sunxi internal brom will try to loader external bootloader
242 * from mmc0, nand flash, mmc2.
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100243 */
Maxime Ripard88290762017-08-23 10:06:30 +0200244uint32_t sunxi_get_boot_device(void)
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100245{
Andre Przywaraee98d762020-01-10 01:47:31 +0000246 int boot_source = sunxi_get_boot_source();
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200247
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200248 /*
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200249 * When booting from the SD card or NAND memory, the "eGON.BT0"
250 * signature is expected to be found in memory at the address 0x0004
251 * (see the "mksunxiboot" tool, which generates this header).
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200252 *
253 * When booting in the FEL mode over USB, this signature is patched in
254 * memory and replaced with something else by the 'fel' tool. This other
255 * signature is selected in such a way, that it can't be present in a
256 * valid bootable SD card image (because the BROM would refuse to
257 * execute the SPL in this case).
258 *
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200259 * This checks for the signature and if it is not found returns to
260 * the FEL code in the BROM to wait and receive the main u-boot
261 * binary over USB. If it is found, it determines where SPL was
262 * read from.
Siarhei Siamashka840fe952015-02-16 10:23:59 +0200263 */
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200264 switch (boot_source) {
Andre Przywaraee98d762020-01-10 01:47:31 +0000265 case SUNXI_INVALID_BOOT_SOURCE:
266 return BOOT_DEVICE_BOARD;
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200267 case SUNXI_BOOTED_FROM_MMC0:
Andre Przywara067e0b92018-12-16 02:04:58 +0000268 case SUNXI_BOOTED_FROM_MMC0_HIGH:
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200269 return BOOT_DEVICE_MMC1;
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200270 case SUNXI_BOOTED_FROM_NAND:
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200271 return BOOT_DEVICE_NAND;
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200272 case SUNXI_BOOTED_FROM_MMC2:
Andre Przywara067e0b92018-12-16 02:04:58 +0000273 case SUNXI_BOOTED_FROM_MMC2_HIGH:
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200274 return BOOT_DEVICE_MMC2;
275 case SUNXI_BOOTED_FROM_SPI:
276 return BOOT_DEVICE_SPI;
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200277 }
278
Hans de Goedeef36d9a2016-07-09 15:31:47 +0200279 panic("Unknown boot source %d\n", boot_source);
Daniel Kochmańskia1514032015-05-29 16:55:42 +0200280 return -1; /* Never reached */
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100281}
282
Maxime Ripard88290762017-08-23 10:06:30 +0200283#ifdef CONFIG_SPL_BUILD
Andre Przywarac0b417b2021-01-11 21:11:39 +0100284static u32 sunxi_get_spl_size(void)
285{
286 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
287 return 0;
288
289 return readl(SPL_ADDR + 0x10);
290}
291
Andre Przywara7c841d82020-01-10 01:47:32 +0000292/*
293 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
294 * an eMMC device. The boot source has bit 4 set in the latter case.
295 * By adding 120KB to the normal offset when booting from a "high" location
296 * we can support both cases.
Andre Przywarac0b417b2021-01-11 21:11:39 +0100297 * Also U-Boot proper is located at least 32KB after the SPL, but will
298 * immediately follow the SPL if that is bigger than that.
Andre Przywara7c841d82020-01-10 01:47:32 +0000299 */
Andre Przywarac0b417b2021-01-11 21:11:39 +0100300unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
301 unsigned long raw_sect)
Andre Przywara7c841d82020-01-10 01:47:32 +0000302{
Andre Przywarac0b417b2021-01-11 21:11:39 +0100303 unsigned long spl_size = sunxi_get_spl_size();
304 unsigned long sector;
305
306 sector = max(raw_sect, spl_size / 512);
Andre Przywara7c841d82020-01-10 01:47:32 +0000307
308 switch (sunxi_get_boot_source()) {
309 case SUNXI_BOOTED_FROM_MMC0_HIGH:
310 case SUNXI_BOOTED_FROM_MMC2_HIGH:
311 sector += (128 - 8) * 2;
312 break;
313 }
314
315 return sector;
316}
317
Maxime Ripard88290762017-08-23 10:06:30 +0200318u32 spl_boot_device(void)
319{
320 return sunxi_get_boot_device();
321}
322
Hans de Goedeb56f6e22015-01-21 16:24:05 +0100323void board_init_f(ulong dummy)
324{
Hans de Goede6d0bdfd2015-09-13 12:31:24 +0200325 spl_init();
Simon Glassf6309742014-12-23 12:04:52 -0700326 preloader_console_init();
327
328#ifdef CONFIG_SPL_I2C_SUPPORT
329 /* Needed early by sunxi_board_init if PMU is enabled */
330 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
331#endif
332 sunxi_board_init();
Simon Glassf6309742014-12-23 12:04:52 -0700333}
334#endif
335
Ian Campbellcba69ee2014-05-05 11:52:26 +0100336void reset_cpu(ulong addr)
337{
Chen-Yu Tsai6c7ae2b2016-11-30 16:27:14 +0800338#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
Hans de Goedec7e79de2014-06-09 11:36:56 +0200339 static const struct sunxi_wdog *wdog =
340 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
341
342 /* Set the watchdog for its shortest interval (.5s) and wait */
343 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
344 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedeae5de5a2014-06-13 22:55:52 +0200345
346 while (1) {
347 /* sun5i sometimes gets stuck without this */
348 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
349 }
Jernej Skrabec44726092021-01-11 21:11:34 +0100350#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
Clément Péron26f8e0d2019-04-17 19:41:05 +0200351#if defined(CONFIG_MACH_SUN50I_H6)
352 /* WDOG is broken for some H6 rev. use the R_WDOG instead */
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800353 static const struct sunxi_wdog *wdog =
Clément Péron26f8e0d2019-04-17 19:41:05 +0200354 (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
355#else
356 static const struct sunxi_wdog *wdog =
357 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
358#endif
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800359 /* Set the watchdog for its shortest interval (.5s) and wait */
360 writel(WDT_CFG_RESET, &wdog->cfg);
361 writel(WDT_MODE_EN, &wdog->mode);
362 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goedefc175432015-06-14 16:53:15 +0200363 while (1) { }
Chen-Yu Tsai78c396a2014-10-04 20:37:28 +0800364#endif
Ian Campbellcba69ee2014-05-05 11:52:26 +0100365}
366
Trevor Woerner10015022019-05-03 09:41:00 -0400367#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
Ian Campbellcba69ee2014-05-05 11:52:26 +0100368void enable_caches(void)
369{
370 /* Enable D-cache. I-cache is already enabled in start.S */
371 dcache_enable();
372}
373#endif