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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Magnus Lilja8449f282009-07-01 01:07:55 +02002/*
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
4 *
5 * (C) Copyright 2004
6 * Texas Instruments.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Kshitij Gupta <kshitij@ti.com>
9 *
10 * Configuration settings for the Freescale i.MX31 PDK board.
Magnus Lilja8449f282009-07-01 01:07:55 +020011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Stefano Babic86271112011-03-14 15:43:56 +010016#include <asm/arch/imx-regs.h>
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010017
Magnus Lilja8449f282009-07-01 01:07:55 +020018/* High Level Configuration Options */
Fabio Estevame89f1f92011-04-26 11:04:37 +000019#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
20#define CONFIG_SETUP_MEMORY_TAGS
21#define CONFIG_INITRD_TAG
Magnus Lilja8449f282009-07-01 01:07:55 +020022
Fabio Estevam9aa3c6a2011-09-22 08:07:14 +000023#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
24
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000025#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000026#define CONFIG_SPL_MAX_SIZE 2048
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000027
28#define CONFIG_SPL_TEXT_BASE 0x87dc0000
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000029
30#ifndef CONFIG_SPL_BUILD
Magnus Lilja8449f282009-07-01 01:07:55 +020031#define CONFIG_SKIP_LOWLEVEL_INIT
Magnus Liljad08e5ca2009-07-04 10:31:24 +020032#endif
Magnus Lilja8449f282009-07-01 01:07:55 +020033
34/*
35 * Size of malloc() pool
36 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010037#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +020038
39/*
40 * Hardware drivers
41 */
42
Fabio Estevame89f1f92011-04-26 11:04:37 +000043#define CONFIG_MXC_UART
Stefano Babic40f6fff2011-11-22 15:22:39 +010044#define CONFIG_MXC_UART_BASE UART1_BASE
Magnus Lilja8449f282009-07-01 01:07:55 +020045
Fabio Estevame89f1f92011-04-26 11:04:37 +000046#define CONFIG_HARD_SPI
Magnus Lilja8449f282009-07-01 01:07:55 +020047#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic9f481e92010-08-23 20:41:19 +020048#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Lilja8449f282009-07-01 01:07:55 +020049
Stefano Babic877a4382011-10-08 11:04:22 +020050/* PMIC Controller */
Łukasz Majewskibe3b51a2012-11-13 03:22:14 +000051#define CONFIG_POWER
52#define CONFIG_POWER_SPI
53#define CONFIG_POWER_FSL
Stefano Babicdfe5e142010-04-16 17:11:19 +020054#define CONFIG_FSL_PMIC_BUS 1
55#define CONFIG_FSL_PMIC_CS 2
56#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic9f481e92010-08-23 20:41:19 +020057#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic877a4382011-10-08 11:04:22 +020058#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000059#define CONFIG_RTC_MC13XXX
Magnus Lilja8449f282009-07-01 01:07:55 +020060
Magnus Lilja8449f282009-07-01 01:07:55 +020061/* allow to overwrite serial and ethaddr */
62#define CONFIG_ENV_OVERWRITE
Magnus Lilja8449f282009-07-01 01:07:55 +020063
Magnus Lilja8449f282009-07-01 01:07:55 +020064#define CONFIG_EXTRA_ENV_SETTINGS \
65 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
66 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
67 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
68 "bootcmd=run bootcmd_net\0" \
69 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010070 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000071 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010072 "nand erase 0x0 0x40000; " \
73 "nand write 0x81000000 0x0 0x40000\0"
Magnus Lilja8449f282009-07-01 01:07:55 +020074
Magnus Lilja8449f282009-07-01 01:07:55 +020075/*
76 * Miscellaneous configurable options
77 */
Magnus Lilja8449f282009-07-01 01:07:55 +020078
79/* memtest works on */
80#define CONFIG_SYS_MEMTEST_START 0x80000000
Fabio Estevam304e49e2012-02-09 14:25:07 +000081#define CONFIG_SYS_MEMTEST_END 0x80010000
Magnus Lilja8449f282009-07-01 01:07:55 +020082
83/* default load address */
84#define CONFIG_SYS_LOAD_ADDR 0x81000000
85
Magnus Lilja8449f282009-07-01 01:07:55 +020086/*-----------------------------------------------------------------------
Magnus Lilja8449f282009-07-01 01:07:55 +020087 * Physical Memory Map
88 */
Magnus Lilja8449f282009-07-01 01:07:55 +020089#define PHYS_SDRAM_1 CSD0_BASE
90#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
91
Fabio Estevamed3df722011-02-09 01:17:55 +000092#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
93#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
94#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Fabio Estevam026ca652011-07-04 09:29:46 +000095#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
96 GENERATED_GBL_DATA_SIZE)
97#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000098 CONFIG_SYS_INIT_RAM_SIZE)
Fabio Estevamed3df722011-02-09 01:17:55 +000099
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900100/*
101 * environment organization
Magnus Lilja8449f282009-07-01 01:07:55 +0200102 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100103#define CONFIG_ENV_OFFSET 0x40000
104#define CONFIG_ENV_OFFSET_REDUND 0x60000
105#define CONFIG_ENV_SIZE (128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +0200106
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100107/*
108 * NAND driver
109 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100110#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
111#define CONFIG_SYS_MAX_NAND_DEVICE 1
112#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
113#define CONFIG_MXC_NAND_HWECC
114#define CONFIG_SYS_NAND_LARGEPAGE
Magnus Lilja8449f282009-07-01 01:07:55 +0200115
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200116/* NAND configuration for the NAND_SPL */
117
Bin Menga1875592016-02-05 19:30:11 -0800118/* Start copying real U-Boot from the second page */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000119#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
120#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200121/* Load U-Boot to this address */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000122#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200123#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
124
125#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
126#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
127#define CONFIG_SYS_NAND_PAGE_COUNT 64
128#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
129#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
130
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200131/* Configuration of lowlevel_init.S (clocks and SDRAM) */
132#define CCM_CCMR_SETUP 0x074B0BF5
Benoît Thébaudeau9e0081d2012-08-14 08:43:07 +0000133#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
134 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
135 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
136 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
137#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200138 PLL_MFN(12))
139
140#define ESDMISC_MDDR_SETUP 0x00000004
141#define ESDMISC_MDDR_RESET_DL 0x0000000c
142#define ESDCFG0_MDDR_SETUP 0x006ac73a
143
144#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
145#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
146 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
147#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
148#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
149#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
150#define ESDCTL_RW ESDCTL_SETTINGS
151
Magnus Lilja8449f282009-07-01 01:07:55 +0200152#endif /* __CONFIG_H */