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Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05301/*
Jagan Teki86e99b92015-09-02 11:39:45 +05302 * (C) Copyright 2013 Xilinx, Inc.
Jagan Tekib1c82da2015-06-27 00:51:31 +05303 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +05304 *
5 * Xilinx Zynq PS SPI controller driver (master mode only)
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053010#include <common.h>
Jagan Tekib1c82da2015-06-27 00:51:31 +053011#include <dm.h>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053012#include <malloc.h>
13#include <spi.h>
14#include <asm/io.h>
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053015
Jagan Tekicdc9dd02015-06-27 00:51:34 +053016DECLARE_GLOBAL_DATA_PTR;
17
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053018/* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
Jagan Teki736b4df2015-10-22 20:40:16 +053019#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
20#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053021#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */
22#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
Jagan Teki736b4df2015-10-22 20:40:16 +053023#define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
24#define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
25#define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */
26#define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
27#define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053028#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
Jagan Teki736b4df2015-10-22 20:40:16 +053029#define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053030
Jagan Teki46ab8a62015-08-17 18:25:03 +053031#define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
32#define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
33#define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
34
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053035#define ZYNQ_SPI_FIFO_DEPTH 128
36#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT
37#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
38#endif
39
40/* zynq spi register set */
41struct zynq_spi_regs {
42 u32 cr; /* 0x00 */
43 u32 isr; /* 0x04 */
44 u32 ier; /* 0x08 */
45 u32 idr; /* 0x0C */
46 u32 imr; /* 0x10 */
47 u32 enr; /* 0x14 */
48 u32 dr; /* 0x18 */
49 u32 txdr; /* 0x1C */
50 u32 rxdr; /* 0x20 */
51};
52
Jagan Tekib1c82da2015-06-27 00:51:31 +053053
54/* zynq spi platform data */
55struct zynq_spi_platdata {
56 struct zynq_spi_regs *regs;
57 u32 frequency; /* input frequency */
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053058 u32 speed_hz;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053059};
60
Jagan Tekib1c82da2015-06-27 00:51:31 +053061/* zynq spi priv */
62struct zynq_spi_priv {
63 struct zynq_spi_regs *regs;
Jagan Teki19126992015-08-17 18:31:39 +053064 u8 cs;
Jagan Tekib1c82da2015-06-27 00:51:31 +053065 u8 mode;
66 u8 fifo_depth;
67 u32 freq; /* required frequency */
68};
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053069
Jagan Tekib1c82da2015-06-27 00:51:31 +053070static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053071{
Jagan Tekib1c82da2015-06-27 00:51:31 +053072 struct zynq_spi_platdata *plat = bus->platdata;
Jagan Tekicdc9dd02015-06-27 00:51:34 +053073 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -070074 int node = dev_of_offset(bus);
Jagan Tekib1c82da2015-06-27 00:51:31 +053075
Simon Glass4e9838c2015-08-11 08:33:29 -060076 plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
Jagan Tekicdc9dd02015-06-27 00:51:34 +053077
78 /* FIXME: Use 250MHz as a suitable default */
79 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
80 250000000);
Jagan Tekib1c82da2015-06-27 00:51:31 +053081 plat->speed_hz = plat->frequency / 2;
82
Michal Simek80fd9792015-07-21 07:54:11 +020083 debug("%s: regs=%p max-frequency=%d\n", __func__,
Jagan Tekicdc9dd02015-06-27 00:51:34 +053084 plat->regs, plat->frequency);
85
Jagan Tekib1c82da2015-06-27 00:51:31 +053086 return 0;
87}
88
89static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
90{
91 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053092 u32 confr;
93
94 /* Disable SPI */
Michal Simek5f647c22016-09-01 12:51:27 +020095 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
96 writel(~confr, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +053097
98 /* Disable Interrupts */
Jagan Tekib1c82da2015-06-27 00:51:31 +053099 writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530100
101 /* Clear RX FIFO */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530102 while (readl(&regs->isr) &
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530103 ZYNQ_SPI_IXR_RXNEMPTY_MASK)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530104 readl(&regs->rxdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530105
106 /* Clear Interrupts */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530107 writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530108
109 /* Manual slave select and Auto start */
110 confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
111 ZYNQ_SPI_CR_MSTREN_MASK;
112 confr &= ~ZYNQ_SPI_CR_MSA_MASK;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530113 writel(confr, &regs->cr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530114
115 /* Enable SPI */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530116 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530117}
118
Jagan Tekib1c82da2015-06-27 00:51:31 +0530119static int zynq_spi_probe(struct udevice *bus)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530120{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530121 struct zynq_spi_platdata *plat = dev_get_platdata(bus);
122 struct zynq_spi_priv *priv = dev_get_priv(bus);
123
124 priv->regs = plat->regs;
125 priv->fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
126
127 /* init the zynq spi hw */
128 zynq_spi_init_hw(priv);
129
130 return 0;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530131}
132
Jagan Teki19126992015-08-17 18:31:39 +0530133static void spi_cs_activate(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530134{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530135 struct udevice *bus = dev->parent;
136 struct zynq_spi_priv *priv = dev_get_priv(bus);
137 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530138 u32 cr;
139
Jagan Tekib1c82da2015-06-27 00:51:31 +0530140 clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
141 cr = readl(&regs->cr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530142 /*
143 * CS cal logic: CS[13:10]
144 * xxx0 - cs0
145 * xx01 - cs1
146 * x011 - cs2
147 */
Jagan Teki19126992015-08-17 18:31:39 +0530148 cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530149 writel(cr, &regs->cr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530150}
151
Jagan Tekib1c82da2015-06-27 00:51:31 +0530152static void spi_cs_deactivate(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530153{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530154 struct udevice *bus = dev->parent;
155 struct zynq_spi_priv *priv = dev_get_priv(bus);
156 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530157
Jagan Tekib1c82da2015-06-27 00:51:31 +0530158 setbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530159}
160
Jagan Tekib1c82da2015-06-27 00:51:31 +0530161static int zynq_spi_claim_bus(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530162{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530163 struct udevice *bus = dev->parent;
164 struct zynq_spi_priv *priv = dev_get_priv(bus);
165 struct zynq_spi_regs *regs = priv->regs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530166
Jagan Tekib1c82da2015-06-27 00:51:31 +0530167 writel(ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530168
169 return 0;
170}
171
Jagan Tekib1c82da2015-06-27 00:51:31 +0530172static int zynq_spi_release_bus(struct udevice *dev)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530173{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530174 struct udevice *bus = dev->parent;
175 struct zynq_spi_priv *priv = dev_get_priv(bus);
176 struct zynq_spi_regs *regs = priv->regs;
Michal Simek5f647c22016-09-01 12:51:27 +0200177 u32 confr;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530178
Michal Simek5f647c22016-09-01 12:51:27 +0200179 confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
180 writel(~confr, &regs->enr);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530181
182 return 0;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530183}
184
Jagan Tekib1c82da2015-06-27 00:51:31 +0530185static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen,
186 const void *dout, void *din, unsigned long flags)
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530187{
Jagan Tekib1c82da2015-06-27 00:51:31 +0530188 struct udevice *bus = dev->parent;
189 struct zynq_spi_priv *priv = dev_get_priv(bus);
190 struct zynq_spi_regs *regs = priv->regs;
191 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530192 u32 len = bitlen / 8;
193 u32 tx_len = len, rx_len = len, tx_tvl;
194 const u8 *tx_buf = dout;
195 u8 *rx_buf = din, buf;
196 u32 ts, status;
197
198 debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
Jagan Tekib1c82da2015-06-27 00:51:31 +0530199 bus->seq, slave_plat->cs, bitlen, len, flags);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530200
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530201 if (bitlen % 8) {
202 debug("spi_xfer: Non byte aligned SPI transfer\n");
203 return -1;
204 }
205
Jagan Teki19126992015-08-17 18:31:39 +0530206 priv->cs = slave_plat->cs;
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530207 if (flags & SPI_XFER_BEGIN)
Jagan Teki19126992015-08-17 18:31:39 +0530208 spi_cs_activate(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530209
210 while (rx_len > 0) {
211 /* Write the data into TX FIFO - tx threshold is fifo_depth */
212 tx_tvl = 0;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530213 while ((tx_tvl < priv->fifo_depth) && tx_len) {
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530214 if (tx_buf)
215 buf = *tx_buf++;
216 else
217 buf = 0;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530218 writel(buf, &regs->txdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530219 tx_len--;
220 tx_tvl++;
221 }
222
223 /* Check TX FIFO completion */
224 ts = get_timer(0);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530225 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530226 while (!(status & ZYNQ_SPI_IXR_TXOW_MASK)) {
227 if (get_timer(ts) > CONFIG_SYS_ZYNQ_SPI_WAIT) {
228 printf("spi_xfer: Timeout! TX FIFO not full\n");
229 return -1;
230 }
Jagan Tekib1c82da2015-06-27 00:51:31 +0530231 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530232 }
233
234 /* Read the data from RX FIFO */
Jagan Tekib1c82da2015-06-27 00:51:31 +0530235 status = readl(&regs->isr);
Lad, Prabhakard2998282016-07-30 22:28:24 +0100236 while ((status & ZYNQ_SPI_IXR_RXNEMPTY_MASK) && rx_len) {
Jagan Tekib1c82da2015-06-27 00:51:31 +0530237 buf = readl(&regs->rxdr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530238 if (rx_buf)
239 *rx_buf++ = buf;
Jagan Tekib1c82da2015-06-27 00:51:31 +0530240 status = readl(&regs->isr);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530241 rx_len--;
242 }
243 }
244
245 if (flags & SPI_XFER_END)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530246 spi_cs_deactivate(dev);
Jagannadha Sutradharudu Teki1465d052013-07-29 23:45:16 +0530247
248 return 0;
249}
Jagan Tekib1c82da2015-06-27 00:51:31 +0530250
251static int zynq_spi_set_speed(struct udevice *bus, uint speed)
252{
253 struct zynq_spi_platdata *plat = bus->platdata;
254 struct zynq_spi_priv *priv = dev_get_priv(bus);
255 struct zynq_spi_regs *regs = priv->regs;
256 uint32_t confr;
257 u8 baud_rate_val = 0;
258
259 if (speed > plat->frequency)
260 speed = plat->frequency;
261
262 /* Set the clock frequency */
263 confr = readl(&regs->cr);
264 if (speed == 0) {
265 /* Set baudrate x8, if the freq is 0 */
266 baud_rate_val = 0x2;
267 } else if (plat->speed_hz != speed) {
Jagan Teki46ab8a62015-08-17 18:25:03 +0530268 while ((baud_rate_val < ZYNQ_SPI_CR_BAUD_MAX) &&
Jagan Tekib1c82da2015-06-27 00:51:31 +0530269 ((plat->frequency /
270 (2 << baud_rate_val)) > speed))
271 baud_rate_val++;
272 plat->speed_hz = speed / (2 << baud_rate_val);
273 }
Jagan Tekidda62412015-08-17 18:27:47 +0530274 confr &= ~ZYNQ_SPI_CR_BAUD_MASK;
Jagan Teki46ab8a62015-08-17 18:25:03 +0530275 confr |= (baud_rate_val << ZYNQ_SPI_CR_BAUD_SHIFT);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530276
277 writel(confr, &regs->cr);
278 priv->freq = speed;
279
Jagan Tekia22bba82015-09-08 01:38:50 +0530280 debug("zynq_spi_set_speed: regs=%p, speed=%d\n",
281 priv->regs, priv->freq);
Jagan Tekib1c82da2015-06-27 00:51:31 +0530282
283 return 0;
284}
285
286static int zynq_spi_set_mode(struct udevice *bus, uint mode)
287{
288 struct zynq_spi_priv *priv = dev_get_priv(bus);
289 struct zynq_spi_regs *regs = priv->regs;
290 uint32_t confr;
291
292 /* Set the SPI Clock phase and polarities */
293 confr = readl(&regs->cr);
294 confr &= ~(ZYNQ_SPI_CR_CPHA_MASK | ZYNQ_SPI_CR_CPOL_MASK);
295
Jagan Tekia22bba82015-09-08 01:38:50 +0530296 if (mode & SPI_CPHA)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530297 confr |= ZYNQ_SPI_CR_CPHA_MASK;
Jagan Tekia22bba82015-09-08 01:38:50 +0530298 if (mode & SPI_CPOL)
Jagan Tekib1c82da2015-06-27 00:51:31 +0530299 confr |= ZYNQ_SPI_CR_CPOL_MASK;
300
301 writel(confr, &regs->cr);
302 priv->mode = mode;
303
304 debug("zynq_spi_set_mode: regs=%p, mode=%d\n", priv->regs, priv->mode);
305
306 return 0;
307}
308
309static const struct dm_spi_ops zynq_spi_ops = {
310 .claim_bus = zynq_spi_claim_bus,
311 .release_bus = zynq_spi_release_bus,
312 .xfer = zynq_spi_xfer,
313 .set_speed = zynq_spi_set_speed,
314 .set_mode = zynq_spi_set_mode,
315};
316
317static const struct udevice_id zynq_spi_ids[] = {
Michal Simek40b383f2015-07-22 10:47:33 +0200318 { .compatible = "xlnx,zynq-spi-r1p6" },
Michal Simek23ef5ae2015-12-07 13:06:54 +0100319 { .compatible = "cdns,spi-r1p6" },
Jagan Tekib1c82da2015-06-27 00:51:31 +0530320 { }
321};
322
323U_BOOT_DRIVER(zynq_spi) = {
324 .name = "zynq_spi",
325 .id = UCLASS_SPI,
326 .of_match = zynq_spi_ids,
327 .ops = &zynq_spi_ops,
328 .ofdata_to_platdata = zynq_spi_ofdata_to_platdata,
329 .platdata_auto_alloc_size = sizeof(struct zynq_spi_platdata),
330 .priv_auto_alloc_size = sizeof(struct zynq_spi_priv),
331 .probe = zynq_spi_probe,
332};