blob: 8785e6c84f3bd001d07c4efda92d47c7c510cc6f [file] [log] [blame]
stroesea65cb682003-09-12 08:41:39 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
stroese31193c22004-12-16 18:37:08 +000030
31extern void lxt971_no_sleep(void);
stroesea65cb682003-09-12 08:41:39 +000032
stroese47b1e3d2005-03-01 17:26:39 +000033int board_revision(void)
34{
35 unsigned long osrl_reg;
36 unsigned long isr1l_reg;
37 unsigned long tcr_reg;
38 unsigned long value;
39
40 /*
41 * Get version of HUB405 board from GPIO's
42 */
43
44 /*
45 * Setup GPIO pin(s) (IRQ6/GPIO23)
46 */
47 osrl_reg = in32(GPIO0_OSRH);
48 isr1l_reg = in32(GPIO0_ISR1H);
49 tcr_reg = in32(GPIO0_TCR);
50 out32(GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
51 out32(GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
52 out32(GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
53
54 udelay(1000); /* wait some time before reading input */
55 value = in32(GPIO0_IR) & 0x00000100; /* get config bits */
56
57 /*
58 * Restore GPIO settings
59 */
60 out32(GPIO0_OSRH, osrl_reg); /* output select */
61 out32(GPIO0_ISR1H, isr1l_reg); /* input select */
62 out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
63
64 if (value & 0x00000100) {
65 /* Revision 1.1 or 1.2 detected */
66 return 1;
67 }
68
69 /* Revision 1.0 */
70 return 0;
71}
72
73
wdenkc837dcb2004-01-20 23:12:12 +000074int board_early_init_f (void)
stroesea65cb682003-09-12 08:41:39 +000075{
76 /*
77 * IRQ 0-15 405GP internally generated; active high; level sensitive
78 * IRQ 16 405GP internally generated; active low; level sensitive
79 * IRQ 17-24 RESERVED
80 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
81 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
82 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
83 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
84 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
85 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
86 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
87 */
88 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
89 mtdcr(uicer, 0x00000000); /* disable all ints */
90 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
91 mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */
92 mtdcr(uictr, 0x10000000); /* set int trigger levels */
93 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
94 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
95
96 /*
97 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
98 */
99 mtebc (epcr, 0xa8400000); /* ebc always driven */
100
101 return 0;
102}
103
stroesea65cb682003-09-12 08:41:39 +0000104int misc_init_r (void)
105{
106 volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
107 volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
108 volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
109 volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
stroese31193c22004-12-16 18:37:08 +0000110 volatile unsigned char *led_reg = (unsigned char *)((ulong)DUART0_BA + 0x20);
111 unsigned long val;
112 int delay, flashcnt;
113 char *str;
stroese47b1e3d2005-03-01 17:26:39 +0000114 char hw_rev[4];
stroesea65cb682003-09-12 08:41:39 +0000115
116 /*
117 * Enable interrupts in exar duart mcr[3]
118 */
119 *duart0_mcr = 0x08;
120 *duart1_mcr = 0x08;
121 *duart2_mcr = 0x08;
122 *duart3_mcr = 0x08;
123
wdenkefe2a4d2004-12-16 21:44:03 +0000124 /*
stroese31193c22004-12-16 18:37:08 +0000125 * Set RS232/RS422 control (RS232 = high on GPIO)
126 */
127 val = in32(GPIO0_OR);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
stroese31193c22004-12-16 18:37:08 +0000129
130 str = getenv("phys0");
131 if (!str || (str && (str[0] == '0')))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 val |= CONFIG_SYS_UART2_RS232;
stroese31193c22004-12-16 18:37:08 +0000133
134 str = getenv("phys1");
135 if (!str || (str && (str[0] == '0')))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 val |= CONFIG_SYS_UART3_RS232;
stroese31193c22004-12-16 18:37:08 +0000137
138 str = getenv("phys2");
139 if (!str || (str && (str[0] == '0')))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 val |= CONFIG_SYS_UART4_RS232;
stroese31193c22004-12-16 18:37:08 +0000141
142 str = getenv("phys3");
143 if (!str || (str && (str[0] == '0')))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 val |= CONFIG_SYS_UART5_RS232;
stroese31193c22004-12-16 18:37:08 +0000145
146 out32(GPIO0_OR, val);
147
stroesea65cb682003-09-12 08:41:39 +0000148 /*
stroese31193c22004-12-16 18:37:08 +0000149 * check board type and setup AP power
150 */
151 str = getenv("bd_type"); /* this is only set on non prototype hardware */
152 if (str != NULL) {
stroese47b1e3d2005-03-01 17:26:39 +0000153 if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
stroese31193c22004-12-16 18:37:08 +0000154 unsigned char led_reg_default = 0;
155 str = getenv("ap_pwr");
156 if (!str || (str && (str[0] == '1')))
157 led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
158
159 /*
stroese47b1e3d2005-03-01 17:26:39 +0000160 * Flash LEDs
stroese31193c22004-12-16 18:37:08 +0000161 */
162 for (flashcnt = 0; flashcnt < 3; flashcnt++) {
163 *led_reg = led_reg_default; /* LED_A..D off */
164 for (delay = 0; delay < 100; delay++)
165 udelay(1000);
166 *led_reg = led_reg_default | 0xf0; /* LED_A..D on */
167 for (delay = 0; delay < 50; delay++)
168 udelay(1000);
169 }
170 *led_reg = led_reg_default;
171 }
172 }
173
174 /*
175 * Reset external DUARTs
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
stroese31193c22004-12-16 18:37:08 +0000178 udelay(10); /* wait 10us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
stroese31193c22004-12-16 18:37:08 +0000180 udelay(1000); /* wait 1ms */
181
stroese47b1e3d2005-03-01 17:26:39 +0000182 /*
183 * Store hardware revision in environment for further processing
184 */
185 sprintf(hw_rev, "1.%ld", gd->board_type);
186 setenv("hw_rev", hw_rev);
stroesea65cb682003-09-12 08:41:39 +0000187 return (0);
188}
189
190
191/*
192 * Check Board Identity:
193 */
stroesea65cb682003-09-12 08:41:39 +0000194int checkboard (void)
195{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200196 char str[64];
stroesea65cb682003-09-12 08:41:39 +0000197 int i = getenv_r ("serial#", str, sizeof(str));
198
199 puts ("Board: ");
200
201 if (i == -1) {
202 puts ("### No HW ID - assuming HUB405");
203 } else {
204 puts(str);
205 }
206
stroese47b1e3d2005-03-01 17:26:39 +0000207 if (getenv_r("bd_type", str, sizeof(str)) != -1) {
208 printf(" (%s", str);
209 } else {
210 puts(" (Missing bd_type!");
211 }
212
213 gd->board_type = board_revision();
214 printf(", Rev 1.%ld)\n", gd->board_type);
stroesea65cb682003-09-12 08:41:39 +0000215
stroese31193c22004-12-16 18:37:08 +0000216 /*
217 * Disable sleep mode in LXT971
218 */
219 lxt971_no_sleep();
220
stroesea65cb682003-09-12 08:41:39 +0000221 return 0;
222}