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Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 * John Otken, jotken@softadvances.com
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01007 */
8
9/************************************************************************
10 * luan.h - configuration for LUAN board
11 ***********************************************************************/
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
18#define CONFIG_LUAN 1 /* Board is Luan */
19#define CONFIG_440SP 1 /* Specific PPC440SP support */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010020#define CONFIG_440 1
21#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
22
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
24
Stefan Roese490f2042008-06-06 15:55:03 +020025/*
26 * Include common defines/options for all AMCC eval boards
27 */
28#define CONFIG_HOSTNAME luan
29#include "amcc-common.h"
30
Stefan Roese00cdb4c2007-03-08 10:13:16 +010031#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010032#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
33
34/*-----------------------------------------------------------------------
35 * Base addresses -- Note these are effective addresses where the
36 * actual resources get mapped (not physical addresses)
37 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
39#define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
40#define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
Wolfgang Denkbf560802010-09-10 23:04:05 +020041#define CONFIG_SYS_SRAM_SIZE (1 << 20)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010043
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
47#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
48#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010049
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
51#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LARGE_FLASH
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010052#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SMALL_FLASH
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010054#endif
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#if CONFIG_SYS_SRAM_BASE
57#define CONFIG_SYS_KBYTES_SDRAM 1024*2
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010058#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_KBYTES_SDRAM 1024
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010060#endif
61
62/*-----------------------------------------------------------------------
63 * Initial RAM & stack pointer (placed in SDRAM)
64 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +020066#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020067#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010069
70/*-----------------------------------------------------------------------
71 * Serial Port
72 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020073#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010075
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010076/*-----------------------------------------------------------------------
77 * Environment
78 *----------------------------------------------------------------------*/
79/*
80 * Define here the location of the environment variables (FLASH or EEPROM).
81 * Note: DENX encourages to use redundant environment in FLASH.
82 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020083#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010084
85/*-----------------------------------------------------------------------
86 * FLASH related
87 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
89#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
92#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ADDR0 0x555
97#define CONFIG_SYS_FLASH_ADDR1 0x2aa
98#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010099
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200100#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200101#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200103#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100104
105/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
107#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200108#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100109
110/*-----------------------------------------------------------------------
111 * DDR SDRAM
112 *----------------------------------------------------------------------*/
Stefan Roese00cdb4c2007-03-08 10:13:16 +0100113#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
114#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
Stefan Roesee4bbed22007-06-01 13:45:24 +0200115#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100116
117/*-----------------------------------------------------------------------
118 * I2C
119 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000120#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
123#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
124#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
125#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4f92ed52006-08-07 14:33:32 +0200126
Stefan Roese490f2042008-06-06 15:55:03 +0200127/*
128 * Default environment variables
129 */
130#define CONFIG_EXTRA_ENV_SETTINGS \
131 CONFIG_AMCC_DEF_ENV \
132 CONFIG_AMCC_DEF_ENV_PPC \
133 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100134 "kernel_addr=fc000000\0" \
135 "ramdisk_addr=fc100000\0" \
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100136 ""
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100137
Stefan Roesea00eccf2008-05-08 11:05:15 +0200138#define CONFIG_HAS_ETH0
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100139#define CONFIG_PHY_ADDR 1
140#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
141#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
142
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100143#ifdef DEBUG
144#define CONFIG_PANIC_HANG
145#else
146#define CONFIG_HW_WATCHDOG /* watchdog */
147#endif
148
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500149/*
Stefan Roese490f2042008-06-06 15:55:03 +0200150 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500151 */
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500152#define CONFIG_CMD_PCI
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500153#define CONFIG_CMD_SDRAM
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100154
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100155/*-----------------------------------------------------------------------
156 * PCI stuff
157 *-----------------------------------------------------------------------
158 */
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500159#if defined(CONFIG_CMD_PCI)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100160
161/* General PCI */
Gabor Juhos842033e2013-05-30 07:06:12 +0000162#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100163#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
164
165/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_PCI_TARGET_INIT
167#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
170#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100171
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500172#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100173
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100174#endif /* __CONFIG_H */