blob: cc9d68546f830acd7581ed94438e37c0559976a0 [file] [log] [blame]
Weijie Gaod24b6932018-11-15 10:08:04 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek SD/MMC Card Interface driver
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 */
8
9#include <clk.h>
10#include <common.h>
11#include <dm.h>
12#include <mmc.h>
13#include <errno.h>
14#include <malloc.h>
mingming lee3b0397d2019-12-31 11:29:24 +080015#include <mapmem.h>
Weijie Gaod24b6932018-11-15 10:08:04 +080016#include <stdbool.h>
17#include <asm/gpio.h>
Simon Glass336d4612020-02-03 07:36:16 -070018#include <dm/device_compat.h>
Weijie Gaod24b6932018-11-15 10:08:04 +080019#include <dm/pinctrl.h>
20#include <linux/bitops.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23
24/* MSDC_CFG */
25#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22)
26#define MSDC_CFG_CKMOD_EXT_M 0x300000
27#define MSDC_CFG_CKMOD_EXT_S 20
28#define MSDC_CFG_CKDIV_EXT_M 0xfff00
29#define MSDC_CFG_CKDIV_EXT_S 8
30#define MSDC_CFG_HS400_CK_MODE BIT(18)
31#define MSDC_CFG_CKMOD_M 0x30000
32#define MSDC_CFG_CKMOD_S 16
33#define MSDC_CFG_CKDIV_M 0xff00
34#define MSDC_CFG_CKDIV_S 8
35#define MSDC_CFG_CKSTB BIT(7)
36#define MSDC_CFG_PIO BIT(3)
37#define MSDC_CFG_RST BIT(2)
38#define MSDC_CFG_CKPDN BIT(1)
39#define MSDC_CFG_MODE BIT(0)
40
41/* MSDC_IOCON */
42#define MSDC_IOCON_W_DSPL BIT(8)
43#define MSDC_IOCON_DSPL BIT(2)
44#define MSDC_IOCON_RSPL BIT(1)
45
46/* MSDC_PS */
47#define MSDC_PS_DAT0 BIT(16)
48#define MSDC_PS_CDDBCE_M 0xf000
49#define MSDC_PS_CDDBCE_S 12
50#define MSDC_PS_CDSTS BIT(1)
51#define MSDC_PS_CDEN BIT(0)
52
53/* #define MSDC_INT(EN) */
54#define MSDC_INT_ACMDRDY BIT(3)
55#define MSDC_INT_ACMDTMO BIT(4)
56#define MSDC_INT_ACMDCRCERR BIT(5)
57#define MSDC_INT_CMDRDY BIT(8)
58#define MSDC_INT_CMDTMO BIT(9)
59#define MSDC_INT_RSPCRCERR BIT(10)
60#define MSDC_INT_XFER_COMPL BIT(12)
61#define MSDC_INT_DATTMO BIT(14)
62#define MSDC_INT_DATCRCERR BIT(15)
63
64/* MSDC_FIFOCS */
65#define MSDC_FIFOCS_CLR BIT(31)
66#define MSDC_FIFOCS_TXCNT_M 0xff0000
67#define MSDC_FIFOCS_TXCNT_S 16
68#define MSDC_FIFOCS_RXCNT_M 0xff
69#define MSDC_FIFOCS_RXCNT_S 0
70
71/* #define SDC_CFG */
72#define SDC_CFG_DTOC_M 0xff000000
73#define SDC_CFG_DTOC_S 24
74#define SDC_CFG_SDIOIDE BIT(20)
75#define SDC_CFG_SDIO BIT(19)
76#define SDC_CFG_BUSWIDTH_M 0x30000
77#define SDC_CFG_BUSWIDTH_S 16
78
79/* SDC_CMD */
80#define SDC_CMD_BLK_LEN_M 0xfff0000
81#define SDC_CMD_BLK_LEN_S 16
82#define SDC_CMD_STOP BIT(14)
83#define SDC_CMD_WR BIT(13)
84#define SDC_CMD_DTYPE_M 0x1800
85#define SDC_CMD_DTYPE_S 11
86#define SDC_CMD_RSPTYP_M 0x380
87#define SDC_CMD_RSPTYP_S 7
88#define SDC_CMD_CMD_M 0x3f
89#define SDC_CMD_CMD_S 0
90
91/* SDC_STS */
92#define SDC_STS_CMDBUSY BIT(1)
93#define SDC_STS_SDCBUSY BIT(0)
94
95/* SDC_ADV_CFG0 */
96#define SDC_RX_ENHANCE_EN BIT(20)
97
98/* PATCH_BIT0 */
99#define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380
100#define MSDC_INT_DAT_LATCH_CK_SEL_S 7
101
102/* PATCH_BIT1 */
103#define MSDC_PB1_STOP_DLY_M 0xf00
104#define MSDC_PB1_STOP_DLY_S 8
105
106/* PATCH_BIT2 */
107#define MSDC_PB2_CRCSTSENSEL_M 0xe0000000
108#define MSDC_PB2_CRCSTSENSEL_S 29
109#define MSDC_PB2_CFGCRCSTS BIT(28)
110#define MSDC_PB2_RESPSTSENSEL_M 0x70000
111#define MSDC_PB2_RESPSTSENSEL_S 16
112#define MSDC_PB2_CFGRESP BIT(15)
113#define MSDC_PB2_RESPWAIT_M 0x0c
114#define MSDC_PB2_RESPWAIT_S 2
115
116/* PAD_TUNE */
117#define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000
118#define MSDC_PAD_TUNE_CMDRRDLY_S 22
119#define MSDC_PAD_TUNE_CMD_SEL BIT(21)
120#define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000
121#define MSDC_PAD_TUNE_CMDRDLY_S 16
122#define MSDC_PAD_TUNE_RXDLYSEL BIT(15)
123#define MSDC_PAD_TUNE_RD_SEL BIT(13)
124#define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00
125#define MSDC_PAD_TUNE_DATRRDLY_S 8
126#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
127#define MSDC_PAD_TUNE_DATWRDLY_S 0
128
mingming lee69373bd2019-11-07 19:28:42 +0800129#define PAD_CMD_TUNE_RX_DLY3 0x3E
130#define PAD_CMD_TUNE_RX_DLY3_S 1
131
Weijie Gaod24b6932018-11-15 10:08:04 +0800132/* EMMC50_CFG0 */
133#define EMMC50_CFG_CFCSTS_SEL BIT(4)
134
135/* SDC_FIFO_CFG */
136#define SDC_FIFO_CFG_WRVALIDSEL BIT(24)
137#define SDC_FIFO_CFG_RDVALIDSEL BIT(25)
138
mingming lee3b0397d2019-12-31 11:29:24 +0800139/* EMMC_TOP_CONTROL mask */
140#define PAD_RXDLY_SEL BIT(0)
141#define DELAY_EN BIT(1)
142#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
143#define PAD_DAT_RD_RXDLY (0x1f << 7)
144#define PAD_DAT_RD_RXDLY_S 7
145#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
146#define PAD_DAT_RD_RXDLY_SEL BIT(13)
147#define DATA_K_VALUE_SEL BIT(14)
148#define SDC_RX_ENH_EN BIT(15)
149
150/* EMMC_TOP_CMD mask */
151#define PAD_CMD_RXDLY2 (0x1f << 0)
152#define PAD_CMD_RXDLY (0x1f << 5)
153#define PAD_CMD_RXDLY_S 5
154#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
155#define PAD_CMD_RD_RXDLY_SEL BIT(11)
156#define PAD_CMD_TX_DLY (0x1f << 12)
157
Weijie Gaod24b6932018-11-15 10:08:04 +0800158/* SDC_CFG_BUSWIDTH */
159#define MSDC_BUS_1BITS 0x0
160#define MSDC_BUS_4BITS 0x1
161#define MSDC_BUS_8BITS 0x2
162
163#define MSDC_FIFO_SIZE 128
164
165#define PAD_DELAY_MAX 32
166
167#define DEFAULT_CD_DEBOUNCE 8
168
169#define CMD_INTS_MASK \
170 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
171
172#define DATA_INTS_MASK \
173 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR)
174
175/* Register offset */
176struct mtk_sd_regs {
177 u32 msdc_cfg;
178 u32 msdc_iocon;
179 u32 msdc_ps;
180 u32 msdc_int;
181 u32 msdc_inten;
182 u32 msdc_fifocs;
183 u32 msdc_txdata;
184 u32 msdc_rxdata;
185 u32 reserved0[4];
186 u32 sdc_cfg;
187 u32 sdc_cmd;
188 u32 sdc_arg;
189 u32 sdc_sts;
190 u32 sdc_resp[4];
191 u32 sdc_blk_num;
192 u32 sdc_vol_chg;
193 u32 sdc_csts;
194 u32 sdc_csts_en;
195 u32 sdc_datcrc_sts;
196 u32 sdc_adv_cfg0;
197 u32 reserved1[2];
198 u32 emmc_cfg0;
199 u32 emmc_cfg1;
200 u32 emmc_sts;
201 u32 emmc_iocon;
202 u32 sd_acmd_resp;
203 u32 sd_acmd19_trg;
204 u32 sd_acmd19_sts;
205 u32 dma_sa_high4bit;
206 u32 dma_sa;
207 u32 dma_ca;
208 u32 dma_ctrl;
209 u32 dma_cfg;
210 u32 sw_dbg_sel;
211 u32 sw_dbg_out;
212 u32 dma_length;
213 u32 reserved2;
214 u32 patch_bit0;
215 u32 patch_bit1;
216 u32 patch_bit2;
217 u32 reserved3;
218 u32 dat0_tune_crc;
219 u32 dat1_tune_crc;
220 u32 dat2_tune_crc;
221 u32 dat3_tune_crc;
222 u32 cmd_tune_crc;
223 u32 sdio_tune_wind;
224 u32 reserved4[5];
225 u32 pad_tune;
226 u32 pad_tune0;
227 u32 pad_tune1;
228 u32 dat_rd_dly[4];
229 u32 reserved5[2];
230 u32 hw_dbg_sel;
231 u32 main_ver;
232 u32 eco_ver;
233 u32 reserved6[27];
234 u32 pad_ds_tune;
mingming lee69373bd2019-11-07 19:28:42 +0800235 u32 pad_cmd_tune;
236 u32 reserved7[30];
Weijie Gaod24b6932018-11-15 10:08:04 +0800237 u32 emmc50_cfg0;
238 u32 reserved8[7];
239 u32 sdc_fifo_cfg;
240};
241
mingming lee3b0397d2019-12-31 11:29:24 +0800242struct msdc_top_regs {
243 u32 emmc_top_control;
244 u32 emmc_top_cmd;
245 u32 emmc50_pad_ctl0;
246 u32 emmc50_pad_ds_tune;
247 u32 emmc50_pad_dat0_tune;
248 u32 emmc50_pad_dat1_tune;
249 u32 emmc50_pad_dat2_tune;
250 u32 emmc50_pad_dat3_tune;
251 u32 emmc50_pad_dat4_tune;
252 u32 emmc50_pad_dat5_tune;
253 u32 emmc50_pad_dat6_tune;
254 u32 emmc50_pad_dat7_tune;
255};
256
Weijie Gaod24b6932018-11-15 10:08:04 +0800257struct msdc_compatible {
258 u8 clk_div_bits;
Weijie Gao3c92a952019-09-25 17:45:37 +0800259 u8 sclk_cycle_shift;
Weijie Gaod24b6932018-11-15 10:08:04 +0800260 bool pad_tune0;
261 bool async_fifo;
262 bool data_tune;
263 bool busy_check;
264 bool stop_clk_fix;
265 bool enhance_rx;
266};
267
268struct msdc_delay_phase {
269 u8 maxlen;
270 u8 start;
271 u8 final_phase;
272};
273
274struct msdc_plat {
275 struct mmc_config cfg;
276 struct mmc mmc;
277};
278
279struct msdc_tune_para {
280 u32 iocon;
281 u32 pad_tune;
mingming lee69373bd2019-11-07 19:28:42 +0800282 u32 pad_cmd_tune;
Weijie Gaod24b6932018-11-15 10:08:04 +0800283};
284
285struct msdc_host {
286 struct mtk_sd_regs *base;
mingming lee3b0397d2019-12-31 11:29:24 +0800287 struct msdc_top_regs *top_base;
Weijie Gaod24b6932018-11-15 10:08:04 +0800288 struct mmc *mmc;
289
290 struct msdc_compatible *dev_comp;
291
292 struct clk src_clk; /* for SD/MMC bus clock */
Fabien Parentba077e52019-03-24 16:46:32 +0100293 struct clk src_clk_cg; /* optional, MSDC source clock control gate */
Weijie Gaod24b6932018-11-15 10:08:04 +0800294 struct clk h_clk; /* MSDC core clock */
295
296 u32 src_clk_freq; /* source clock */
297 u32 mclk; /* mmc framework required bus clock */
298 u32 sclk; /* actual calculated bus clock */
299
300 /* operation timeout clocks */
301 u32 timeout_ns;
302 u32 timeout_clks;
303
304 /* tuning options */
305 u32 hs400_ds_delay;
306 u32 hs200_cmd_int_delay;
307 u32 hs200_write_int_delay;
308 u32 latch_ck;
309 u32 r_smpl; /* sample edge */
310 bool hs400_mode;
311
312 /* whether to use gpio detection or built-in hw detection */
313 bool builtin_cd;
Weijie Gao77ebea22019-09-25 17:45:38 +0800314 bool cd_active_high;
Weijie Gaod24b6932018-11-15 10:08:04 +0800315
316 /* card detection / write protection GPIOs */
Fabien Parentb5096f12019-03-24 16:46:34 +0100317#if CONFIG_IS_ENABLED(DM_GPIO)
Weijie Gaod24b6932018-11-15 10:08:04 +0800318 struct gpio_desc gpio_wp;
319 struct gpio_desc gpio_cd;
320#endif
321
322 uint last_resp_type;
323 uint last_data_write;
324
325 enum bus_mode timing;
326
327 struct msdc_tune_para def_tune_para;
328 struct msdc_tune_para saved_tune_para;
329};
330
331static void msdc_reset_hw(struct msdc_host *host)
332{
333 u32 reg;
334
335 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST);
336
337 readl_poll_timeout(&host->base->msdc_cfg, reg,
338 !(reg & MSDC_CFG_RST), 1000000);
339}
340
341static void msdc_fifo_clr(struct msdc_host *host)
342{
343 u32 reg;
344
345 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR);
346
347 readl_poll_timeout(&host->base->msdc_fifocs, reg,
348 !(reg & MSDC_FIFOCS_CLR), 1000000);
349}
350
351static u32 msdc_fifo_rx_bytes(struct msdc_host *host)
352{
353 return (readl(&host->base->msdc_fifocs) &
354 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S;
355}
356
357static u32 msdc_fifo_tx_bytes(struct msdc_host *host)
358{
359 return (readl(&host->base->msdc_fifocs) &
360 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S;
361}
362
363static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd)
364{
365 u32 resp;
366
367 switch (cmd->resp_type) {
368 /* Actually, R1, R5, R6, R7 are the same */
369 case MMC_RSP_R1:
370 resp = 0x1;
371 break;
372 case MMC_RSP_R1b:
373 resp = 0x7;
374 break;
375 case MMC_RSP_R2:
376 resp = 0x2;
377 break;
378 case MMC_RSP_R3:
379 resp = 0x3;
380 break;
381 case MMC_RSP_NONE:
382 default:
383 resp = 0x0;
384 break;
385 }
386
387 return resp;
388}
389
390static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
391 struct mmc_cmd *cmd,
392 struct mmc_data *data)
393{
394 u32 opcode = cmd->cmdidx;
395 u32 resp_type = msdc_cmd_find_resp(host, cmd);
396 uint blocksize = 0;
397 u32 dtype = 0;
398 u32 rawcmd = 0;
399
400 switch (opcode) {
401 case MMC_CMD_WRITE_MULTIPLE_BLOCK:
402 case MMC_CMD_READ_MULTIPLE_BLOCK:
403 dtype = 2;
404 break;
405 case MMC_CMD_WRITE_SINGLE_BLOCK:
406 case MMC_CMD_READ_SINGLE_BLOCK:
407 case SD_CMD_APP_SEND_SCR:
mingming lee69373bd2019-11-07 19:28:42 +0800408 case MMC_CMD_SEND_TUNING_BLOCK:
409 case MMC_CMD_SEND_TUNING_BLOCK_HS200:
Weijie Gaod24b6932018-11-15 10:08:04 +0800410 dtype = 1;
411 break;
412 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
413 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */
414 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */
415 if (data)
416 dtype = 1;
417 }
418
419 if (data) {
420 if (data->flags == MMC_DATA_WRITE)
421 rawcmd |= SDC_CMD_WR;
422
423 if (data->blocks > 1)
424 dtype = 2;
425
426 blocksize = data->blocksize;
427 }
428
429 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) |
430 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) |
431 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) |
432 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M);
433
434 if (opcode == MMC_CMD_STOP_TRANSMISSION)
435 rawcmd |= SDC_CMD_STOP;
436
437 return rawcmd;
438}
439
440static int msdc_cmd_done(struct msdc_host *host, int events,
441 struct mmc_cmd *cmd)
442{
443 u32 *rsp = cmd->response;
444 int ret = 0;
445
446 if (cmd->resp_type & MMC_RSP_PRESENT) {
447 if (cmd->resp_type & MMC_RSP_136) {
448 rsp[0] = readl(&host->base->sdc_resp[3]);
449 rsp[1] = readl(&host->base->sdc_resp[2]);
450 rsp[2] = readl(&host->base->sdc_resp[1]);
451 rsp[3] = readl(&host->base->sdc_resp[0]);
452 } else {
453 rsp[0] = readl(&host->base->sdc_resp[0]);
454 }
455 }
456
457 if (!(events & MSDC_INT_CMDRDY)) {
458 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
459 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
460 /*
461 * should not clear fifo/interrupt as the tune data
462 * may have alreay come.
463 */
464 msdc_reset_hw(host);
465
466 if (events & MSDC_INT_CMDTMO)
467 ret = -ETIMEDOUT;
468 else
469 ret = -EIO;
470 }
471
472 return ret;
473}
474
475static bool msdc_cmd_is_ready(struct msdc_host *host)
476{
477 int ret;
478 u32 reg;
479
480 /* The max busy time we can endure is 20ms */
481 ret = readl_poll_timeout(&host->base->sdc_sts, reg,
482 !(reg & SDC_STS_CMDBUSY), 20000);
483
484 if (ret) {
485 pr_err("CMD bus busy detected\n");
486 msdc_reset_hw(host);
487 return false;
488 }
489
490 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) {
491 ret = readl_poll_timeout(&host->base->msdc_ps, reg,
492 reg & MSDC_PS_DAT0, 1000000);
493
494 if (ret) {
495 pr_err("Card stuck in programming state!\n");
496 msdc_reset_hw(host);
497 return false;
498 }
499 }
500
501 return true;
502}
503
504static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd,
505 struct mmc_data *data)
506{
507 u32 rawcmd;
508 u32 status;
509 u32 blocks = 0;
510 int ret;
511
512 if (!msdc_cmd_is_ready(host))
513 return -EIO;
514
mingming lee69373bd2019-11-07 19:28:42 +0800515 if ((readl(&host->base->msdc_fifocs) &
516 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
517 (readl(&host->base->msdc_fifocs) &
518 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
519 pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
520 msdc_reset_hw(host);
521 }
522
Weijie Gaod24b6932018-11-15 10:08:04 +0800523 msdc_fifo_clr(host);
524
525 host->last_resp_type = cmd->resp_type;
526 host->last_data_write = 0;
527
528 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data);
529
530 if (data)
531 blocks = data->blocks;
532
533 writel(CMD_INTS_MASK, &host->base->msdc_int);
mingming leefb80eaa2019-12-31 11:29:25 +0800534 writel(DATA_INTS_MASK, &host->base->msdc_int);
Weijie Gaod24b6932018-11-15 10:08:04 +0800535 writel(blocks, &host->base->sdc_blk_num);
536 writel(cmd->cmdarg, &host->base->sdc_arg);
537 writel(rawcmd, &host->base->sdc_cmd);
538
539 ret = readl_poll_timeout(&host->base->msdc_int, status,
540 status & CMD_INTS_MASK, 1000000);
541
542 if (ret)
543 status = MSDC_INT_CMDTMO;
544
545 return msdc_cmd_done(host, status, cmd);
546}
547
548static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size)
549{
550 u32 *wbuf;
551
552 while ((size_t)buf % 4) {
553 *buf++ = readb(&host->base->msdc_rxdata);
554 size--;
555 }
556
557 wbuf = (u32 *)buf;
558 while (size >= 4) {
559 *wbuf++ = readl(&host->base->msdc_rxdata);
560 size -= 4;
561 }
562
563 buf = (u8 *)wbuf;
564 while (size) {
565 *buf++ = readb(&host->base->msdc_rxdata);
566 size--;
567 }
568}
569
570static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size)
571{
572 const u32 *wbuf;
573
574 while ((size_t)buf % 4) {
575 writeb(*buf++, &host->base->msdc_txdata);
576 size--;
577 }
578
579 wbuf = (const u32 *)buf;
580 while (size >= 4) {
581 writel(*wbuf++, &host->base->msdc_txdata);
582 size -= 4;
583 }
584
585 buf = (const u8 *)wbuf;
586 while (size) {
587 writeb(*buf++, &host->base->msdc_txdata);
588 size--;
589 }
590}
591
592static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size)
593{
594 u32 status;
595 u32 chksz;
596 int ret = 0;
597
598 while (1) {
599 status = readl(&host->base->msdc_int);
600 writel(status, &host->base->msdc_int);
601 status &= DATA_INTS_MASK;
602
603 if (status & MSDC_INT_DATCRCERR) {
604 ret = -EIO;
605 break;
606 }
607
608 if (status & MSDC_INT_DATTMO) {
609 ret = -ETIMEDOUT;
610 break;
611 }
612
Fabien Parent924ed342019-01-17 18:06:00 +0100613 chksz = min(size, (u32)MSDC_FIFO_SIZE);
614
615 if (msdc_fifo_rx_bytes(host) >= chksz) {
616 msdc_fifo_read(host, ptr, chksz);
617 ptr += chksz;
618 size -= chksz;
619 }
620
Weijie Gaod24b6932018-11-15 10:08:04 +0800621 if (status & MSDC_INT_XFER_COMPL) {
622 if (size) {
623 pr_err("data not fully read\n");
624 ret = -EIO;
625 }
626
627 break;
628 }
Fabien Parent924ed342019-01-17 18:06:00 +0100629}
Weijie Gaod24b6932018-11-15 10:08:04 +0800630
631 return ret;
632}
633
634static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size)
635{
636 u32 status;
637 u32 chksz;
638 int ret = 0;
639
640 while (1) {
641 status = readl(&host->base->msdc_int);
642 writel(status, &host->base->msdc_int);
643 status &= DATA_INTS_MASK;
644
645 if (status & MSDC_INT_DATCRCERR) {
646 ret = -EIO;
647 break;
648 }
649
650 if (status & MSDC_INT_DATTMO) {
651 ret = -ETIMEDOUT;
652 break;
653 }
654
655 if (status & MSDC_INT_XFER_COMPL) {
656 if (size) {
657 pr_err("data not fully written\n");
658 ret = -EIO;
659 }
660
661 break;
662 }
663
664 chksz = min(size, (u32)MSDC_FIFO_SIZE);
665
666 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) {
667 msdc_fifo_write(host, ptr, chksz);
668 ptr += chksz;
669 size -= chksz;
670 }
671 }
672
673 return ret;
674}
675
676static int msdc_start_data(struct msdc_host *host, struct mmc_data *data)
677{
678 u32 size;
679 int ret;
680
681 if (data->flags == MMC_DATA_WRITE)
682 host->last_data_write = 1;
683
Weijie Gaod24b6932018-11-15 10:08:04 +0800684 size = data->blocks * data->blocksize;
685
686 if (data->flags == MMC_DATA_WRITE)
687 ret = msdc_pio_write(host, (const u8 *)data->src, size);
688 else
689 ret = msdc_pio_read(host, (u8 *)data->dest, size);
690
691 if (ret) {
692 msdc_reset_hw(host);
693 msdc_fifo_clr(host);
694 }
695
696 return ret;
697}
698
699static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
700 struct mmc_data *data)
701{
702 struct msdc_host *host = dev_get_priv(dev);
mingming lee69373bd2019-11-07 19:28:42 +0800703 int cmd_ret, data_ret;
Weijie Gaod24b6932018-11-15 10:08:04 +0800704
mingming lee69373bd2019-11-07 19:28:42 +0800705 cmd_ret = msdc_start_command(host, cmd, data);
706 if (cmd_ret &&
707 !(cmd_ret == -EIO &&
708 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
709 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
710 return cmd_ret;
Weijie Gaod24b6932018-11-15 10:08:04 +0800711
mingming lee69373bd2019-11-07 19:28:42 +0800712 if (data) {
713 data_ret = msdc_start_data(host, data);
714 if (cmd_ret)
715 return cmd_ret;
716 else
717 return data_ret;
718 }
Weijie Gaod24b6932018-11-15 10:08:04 +0800719
720 return 0;
721}
722
723static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
724{
Weijie Gao3c92a952019-09-25 17:45:37 +0800725 u32 timeout, clk_ns, shift;
Weijie Gaod24b6932018-11-15 10:08:04 +0800726 u32 mode = 0;
727
728 host->timeout_ns = ns;
729 host->timeout_clks = clks;
730
731 if (host->sclk == 0) {
732 timeout = 0;
733 } else {
Weijie Gao3c92a952019-09-25 17:45:37 +0800734 shift = host->dev_comp->sclk_cycle_shift;
Weijie Gaod24b6932018-11-15 10:08:04 +0800735 clk_ns = 1000000000UL / host->sclk;
736 timeout = (ns + clk_ns - 1) / clk_ns + clks;
737 /* unit is 1048576 sclk cycles */
Weijie Gao3c92a952019-09-25 17:45:37 +0800738 timeout = (timeout + (0x1 << shift) - 1) >> shift;
Weijie Gaod24b6932018-11-15 10:08:04 +0800739 if (host->dev_comp->clk_div_bits == 8)
740 mode = (readl(&host->base->msdc_cfg) &
741 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S;
742 else
743 mode = (readl(&host->base->msdc_cfg) &
744 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S;
745 /* DDR mode will double the clk cycles for data timeout */
746 timeout = mode >= 2 ? timeout * 2 : timeout;
747 timeout = timeout > 1 ? timeout - 1 : 0;
748 timeout = timeout > 255 ? 255 : timeout;
749 }
750
751 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
752 timeout << SDC_CFG_DTOC_S);
753}
754
755static void msdc_set_buswidth(struct msdc_host *host, u32 width)
756{
757 u32 val = readl(&host->base->sdc_cfg);
758
759 val &= ~SDC_CFG_BUSWIDTH_M;
760
761 switch (width) {
762 default:
763 case 1:
764 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S);
765 break;
766 case 4:
767 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S);
768 break;
769 case 8:
770 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S);
771 break;
772 }
773
774 writel(val, &host->base->sdc_cfg);
775}
776
Sean Andersone1ce7902020-09-15 10:44:47 -0400777static void msdc_set_mclk(struct udevice *dev,
778 struct msdc_host *host, enum bus_mode timing, u32 hz)
Weijie Gaod24b6932018-11-15 10:08:04 +0800779{
780 u32 mode;
781 u32 div;
782 u32 sclk;
783 u32 reg;
784
785 if (!hz) {
786 host->mclk = 0;
787 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
788 return;
789 }
790
791 if (host->dev_comp->clk_div_bits == 8)
792 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE);
793 else
794 clrbits_le32(&host->base->msdc_cfg,
795 MSDC_CFG_HS400_CK_MODE_EXT);
796
797 if (timing == UHS_DDR50 || timing == MMC_DDR_52 ||
798 timing == MMC_HS_400) {
799 if (timing == MMC_HS_400)
800 mode = 0x3;
801 else
802 mode = 0x2; /* ddr mode and use divisor */
803
804 if (hz >= (host->src_clk_freq >> 2)) {
805 div = 0; /* mean div = 1/4 */
806 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
807 } else {
808 div = (host->src_clk_freq + ((hz << 2) - 1)) /
809 (hz << 2);
810 sclk = (host->src_clk_freq >> 2) / div;
811 div = (div >> 1);
812 }
813
814 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) {
815 if (host->dev_comp->clk_div_bits == 8)
816 setbits_le32(&host->base->msdc_cfg,
817 MSDC_CFG_HS400_CK_MODE);
818 else
819 setbits_le32(&host->base->msdc_cfg,
820 MSDC_CFG_HS400_CK_MODE_EXT);
821
822 sclk = host->src_clk_freq >> 1;
823 div = 0; /* div is ignore when bit18 is set */
824 }
825 } else if (hz >= host->src_clk_freq) {
826 mode = 0x1; /* no divisor */
827 div = 0;
828 sclk = host->src_clk_freq;
829 } else {
830 mode = 0x0; /* use divisor */
831 if (hz >= (host->src_clk_freq >> 1)) {
832 div = 0; /* mean div = 1/2 */
833 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
834 } else {
835 div = (host->src_clk_freq + ((hz << 2) - 1)) /
836 (hz << 2);
837 sclk = (host->src_clk_freq >> 2) / div;
838 }
839 }
840
841 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
842
843 if (host->dev_comp->clk_div_bits == 8) {
844 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S));
845 clrsetbits_le32(&host->base->msdc_cfg,
846 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M,
847 (mode << MSDC_CFG_CKMOD_S) |
848 (div << MSDC_CFG_CKDIV_S));
849 } else {
850 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >>
851 MSDC_CFG_CKDIV_EXT_S));
852 clrsetbits_le32(&host->base->msdc_cfg,
853 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M,
854 (mode << MSDC_CFG_CKMOD_EXT_S) |
855 (div << MSDC_CFG_CKDIV_EXT_S));
856 }
857
858 readl_poll_timeout(&host->base->msdc_cfg, reg,
859 reg & MSDC_CFG_CKSTB, 1000000);
860
861 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN);
862 host->sclk = sclk;
863 host->mclk = hz;
864 host->timing = timing;
865
866 /* needed because clk changed. */
867 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
868
869 /*
870 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
871 * tune result of hs200/200Mhz is not suitable for 50Mhz
872 */
873 if (host->sclk <= 52000000) {
874 writel(host->def_tune_para.iocon, &host->base->msdc_iocon);
875 writel(host->def_tune_para.pad_tune,
876 &host->base->pad_tune);
877 } else {
878 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon);
879 writel(host->saved_tune_para.pad_tune,
880 &host->base->pad_tune);
881 }
882
883 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing);
884}
885
886static int msdc_ops_set_ios(struct udevice *dev)
887{
Simon Glassc69cda22020-12-03 16:55:20 -0700888 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +0800889 struct msdc_host *host = dev_get_priv(dev);
890 struct mmc *mmc = &plat->mmc;
891 uint clock = mmc->clock;
892
893 msdc_set_buswidth(host, mmc->bus_width);
894
895 if (mmc->clk_disable)
896 clock = 0;
897 else if (clock < mmc->cfg->f_min)
898 clock = mmc->cfg->f_min;
899
900 if (host->mclk != clock || host->timing != mmc->selected_mode)
Sean Andersone1ce7902020-09-15 10:44:47 -0400901 msdc_set_mclk(dev, host, mmc->selected_mode, clock);
Weijie Gaod24b6932018-11-15 10:08:04 +0800902
903 return 0;
904}
905
906static int msdc_ops_get_cd(struct udevice *dev)
907{
908 struct msdc_host *host = dev_get_priv(dev);
909 u32 val;
910
911 if (host->builtin_cd) {
912 val = readl(&host->base->msdc_ps);
Weijie Gao77ebea22019-09-25 17:45:38 +0800913 val = !!(val & MSDC_PS_CDSTS);
914
915 return !val ^ host->cd_active_high;
Weijie Gaod24b6932018-11-15 10:08:04 +0800916 }
917
Fabien Parentb5096f12019-03-24 16:46:34 +0100918#if CONFIG_IS_ENABLED(DM_GPIO)
Weijie Gaod24b6932018-11-15 10:08:04 +0800919 if (!host->gpio_cd.dev)
920 return 1;
921
922 return dm_gpio_get_value(&host->gpio_cd);
923#else
924 return 1;
925#endif
926}
927
928static int msdc_ops_get_wp(struct udevice *dev)
929{
Fabien Parentb5096f12019-03-24 16:46:34 +0100930#if CONFIG_IS_ENABLED(DM_GPIO)
Weijie Gaod24b6932018-11-15 10:08:04 +0800931 struct msdc_host *host = dev_get_priv(dev);
932
Weijie Gaod24b6932018-11-15 10:08:04 +0800933 if (!host->gpio_wp.dev)
934 return 0;
935
936 return !dm_gpio_get_value(&host->gpio_wp);
937#else
938 return 0;
939#endif
940}
941
942#ifdef MMC_SUPPORTS_TUNING
943static u32 test_delay_bit(u32 delay, u32 bit)
944{
945 bit %= PAD_DELAY_MAX;
946 return delay & (1 << bit);
947}
948
949static int get_delay_len(u32 delay, u32 start_bit)
950{
951 int i;
952
953 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
954 if (test_delay_bit(delay, start_bit + i) == 0)
955 return i;
956 }
957
958 return PAD_DELAY_MAX - start_bit;
959}
960
Sean Andersone1ce7902020-09-15 10:44:47 -0400961static struct msdc_delay_phase get_best_delay(struct udevice *dev,
962 struct msdc_host *host, u32 delay)
Weijie Gaod24b6932018-11-15 10:08:04 +0800963{
964 int start = 0, len = 0;
965 int start_final = 0, len_final = 0;
966 u8 final_phase = 0xff;
967 struct msdc_delay_phase delay_phase = { 0, };
968
969 if (delay == 0) {
970 dev_err(dev, "phase error: [map:%x]\n", delay);
971 delay_phase.final_phase = final_phase;
972 return delay_phase;
973 }
974
975 while (start < PAD_DELAY_MAX) {
976 len = get_delay_len(delay, start);
977 if (len_final < len) {
978 start_final = start;
979 len_final = len;
980 }
981
982 start += len ? len : 1;
983 if (len >= 12 && start_final < 4)
984 break;
985 }
986
987 /* The rule is to find the smallest delay cell */
988 if (start_final == 0)
989 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
990 else
991 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
992
993 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
994 delay, len_final, final_phase);
995
996 delay_phase.maxlen = len_final;
997 delay_phase.start = start_final;
998 delay_phase.final_phase = final_phase;
999 return delay_phase;
1000}
1001
mingming lee3b0397d2019-12-31 11:29:24 +08001002static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1003{
1004 void __iomem *tune_reg = &host->base->pad_tune;
1005
1006 if (host->dev_comp->pad_tune0)
1007 tune_reg = &host->base->pad_tune0;
1008
1009 if (host->top_base)
1010 clrsetbits_le32(&host->top_base->emmc_top_cmd, PAD_CMD_RXDLY,
1011 value << PAD_CMD_RXDLY_S);
1012 else
1013 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1014 value << MSDC_PAD_TUNE_CMDRDLY_S);
1015}
1016
1017static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1018{
1019 void __iomem *tune_reg = &host->base->pad_tune;
1020
1021 if (host->dev_comp->pad_tune0)
1022 tune_reg = &host->base->pad_tune0;
1023
1024 if (host->top_base)
1025 clrsetbits_le32(&host->top_base->emmc_top_control,
1026 PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
1027 else
1028 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1029 value << MSDC_PAD_TUNE_DATRRDLY_S);
1030}
1031
mingming lee69373bd2019-11-07 19:28:42 +08001032static int hs400_tune_response(struct udevice *dev, u32 opcode)
1033{
Simon Glassc69cda22020-12-03 16:55:20 -07001034 struct msdc_plat *plat = dev_get_plat(dev);
mingming lee69373bd2019-11-07 19:28:42 +08001035 struct msdc_host *host = dev_get_priv(dev);
1036 struct mmc *mmc = &plat->mmc;
1037 u32 cmd_delay = 0;
1038 struct msdc_delay_phase final_cmd_delay = { 0, };
1039 u8 final_delay;
1040 void __iomem *tune_reg = &host->base->pad_cmd_tune;
1041 int cmd_err;
1042 int i, j;
1043
1044 setbits_le32(&host->base->pad_cmd_tune, BIT(0));
1045
1046 if (mmc->selected_mode == MMC_HS_200 ||
1047 mmc->selected_mode == UHS_SDR104)
1048 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1049 host->hs200_cmd_int_delay <<
1050 MSDC_PAD_TUNE_CMDRRDLY_S);
1051
1052 if (host->r_smpl)
1053 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1054 else
1055 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1056
1057 for (i = 0; i < PAD_DELAY_MAX; i++) {
1058 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1059 i << PAD_CMD_TUNE_RX_DLY3_S);
1060
1061 for (j = 0; j < 3; j++) {
1062 mmc_send_tuning(mmc, opcode, &cmd_err);
1063 if (!cmd_err) {
1064 cmd_delay |= (1 << i);
1065 } else {
1066 cmd_delay &= ~(1 << i);
1067 break;
1068 }
1069 }
1070 }
1071
Sean Andersone1ce7902020-09-15 10:44:47 -04001072 final_cmd_delay = get_best_delay(dev, host, cmd_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001073 clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
1074 final_cmd_delay.final_phase <<
1075 PAD_CMD_TUNE_RX_DLY3_S);
1076 final_delay = final_cmd_delay.final_phase;
1077
mingming lee3b0397d2019-12-31 11:29:24 +08001078 dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001079 return final_delay == 0xff ? -EIO : 0;
1080}
1081
Weijie Gaod24b6932018-11-15 10:08:04 +08001082static int msdc_tune_response(struct udevice *dev, u32 opcode)
1083{
Simon Glassc69cda22020-12-03 16:55:20 -07001084 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001085 struct msdc_host *host = dev_get_priv(dev);
1086 struct mmc *mmc = &plat->mmc;
1087 u32 rise_delay = 0, fall_delay = 0;
1088 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1089 struct msdc_delay_phase internal_delay_phase;
1090 u8 final_delay, final_maxlen;
1091 u32 internal_delay = 0;
1092 void __iomem *tune_reg = &host->base->pad_tune;
1093 int cmd_err;
1094 int i, j;
1095
1096 if (host->dev_comp->pad_tune0)
1097 tune_reg = &host->base->pad_tune0;
1098
1099 if (mmc->selected_mode == MMC_HS_200 ||
1100 mmc->selected_mode == UHS_SDR104)
1101 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1102 host->hs200_cmd_int_delay <<
1103 MSDC_PAD_TUNE_CMDRRDLY_S);
1104
1105 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1106
1107 for (i = 0; i < PAD_DELAY_MAX; i++) {
1108 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1109 i << MSDC_PAD_TUNE_CMDRDLY_S);
1110
1111 for (j = 0; j < 3; j++) {
1112 mmc_send_tuning(mmc, opcode, &cmd_err);
1113 if (!cmd_err) {
1114 rise_delay |= (1 << i);
1115 } else {
1116 rise_delay &= ~(1 << i);
1117 break;
1118 }
1119 }
1120 }
1121
Sean Andersone1ce7902020-09-15 10:44:47 -04001122 final_rise_delay = get_best_delay(dev, host, rise_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001123 /* if rising edge has enough margin, do not scan falling edge */
1124 if (final_rise_delay.maxlen >= 12 ||
1125 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1126 goto skip_fall;
1127
1128 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1129 for (i = 0; i < PAD_DELAY_MAX; i++) {
1130 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1131 i << MSDC_PAD_TUNE_CMDRDLY_S);
1132
1133 for (j = 0; j < 3; j++) {
1134 mmc_send_tuning(mmc, opcode, &cmd_err);
1135 if (!cmd_err) {
1136 fall_delay |= (1 << i);
1137 } else {
1138 fall_delay &= ~(1 << i);
1139 break;
1140 }
1141 }
1142 }
1143
Sean Andersone1ce7902020-09-15 10:44:47 -04001144 final_fall_delay = get_best_delay(dev, host, fall_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001145
1146skip_fall:
1147 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1148 if (final_maxlen == final_rise_delay.maxlen) {
1149 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1150 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1151 final_rise_delay.final_phase <<
1152 MSDC_PAD_TUNE_CMDRDLY_S);
1153 final_delay = final_rise_delay.final_phase;
1154 } else {
1155 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1156 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
1157 final_fall_delay.final_phase <<
1158 MSDC_PAD_TUNE_CMDRDLY_S);
1159 final_delay = final_fall_delay.final_phase;
1160 }
1161
1162 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1163 goto skip_internal;
1164
1165 for (i = 0; i < PAD_DELAY_MAX; i++) {
1166 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1167 i << MSDC_PAD_TUNE_CMDRRDLY_S);
1168
1169 mmc_send_tuning(mmc, opcode, &cmd_err);
1170 if (!cmd_err)
1171 internal_delay |= (1 << i);
1172 }
1173
Fabien Parent0d675762020-10-15 18:38:18 +02001174 dev_dbg(dev, "Final internal delay: 0x%x\n", internal_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001175
Sean Andersone1ce7902020-09-15 10:44:47 -04001176 internal_delay_phase = get_best_delay(dev, host, internal_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001177 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
1178 internal_delay_phase.final_phase <<
1179 MSDC_PAD_TUNE_CMDRRDLY_S);
1180
1181skip_internal:
Fabien Parent0d675762020-10-15 18:38:18 +02001182 dev_dbg(dev, "Final cmd pad delay: %x\n", final_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001183 return final_delay == 0xff ? -EIO : 0;
1184}
1185
1186static int msdc_tune_data(struct udevice *dev, u32 opcode)
1187{
Simon Glassc69cda22020-12-03 16:55:20 -07001188 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001189 struct msdc_host *host = dev_get_priv(dev);
1190 struct mmc *mmc = &plat->mmc;
1191 u32 rise_delay = 0, fall_delay = 0;
1192 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1193 u8 final_delay, final_maxlen;
1194 void __iomem *tune_reg = &host->base->pad_tune;
1195 int cmd_err;
1196 int i, ret;
1197
1198 if (host->dev_comp->pad_tune0)
1199 tune_reg = &host->base->pad_tune0;
1200
1201 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1202 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1203
1204 for (i = 0; i < PAD_DELAY_MAX; i++) {
1205 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1206 i << MSDC_PAD_TUNE_DATRRDLY_S);
1207
1208 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1209 if (!ret) {
1210 rise_delay |= (1 << i);
1211 } else if (cmd_err) {
1212 /* in this case, retune response is needed */
1213 ret = msdc_tune_response(dev, opcode);
1214 if (ret)
1215 break;
1216 }
1217 }
1218
Sean Andersone1ce7902020-09-15 10:44:47 -04001219 final_rise_delay = get_best_delay(dev, host, rise_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001220 if (final_rise_delay.maxlen >= 12 ||
1221 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1222 goto skip_fall;
1223
1224 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1225 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1226
1227 for (i = 0; i < PAD_DELAY_MAX; i++) {
1228 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1229 i << MSDC_PAD_TUNE_DATRRDLY_S);
1230
1231 ret = mmc_send_tuning(mmc, opcode, &cmd_err);
1232 if (!ret) {
1233 fall_delay |= (1 << i);
1234 } else if (cmd_err) {
1235 /* in this case, retune response is needed */
1236 ret = msdc_tune_response(dev, opcode);
1237 if (ret)
1238 break;
1239 }
1240 }
1241
Sean Andersone1ce7902020-09-15 10:44:47 -04001242 final_fall_delay = get_best_delay(dev, host, fall_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001243
1244skip_fall:
1245 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1246 if (final_maxlen == final_rise_delay.maxlen) {
1247 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1248 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1249 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1250 final_rise_delay.final_phase <<
1251 MSDC_PAD_TUNE_DATRRDLY_S);
1252 final_delay = final_rise_delay.final_phase;
1253 } else {
1254 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1255 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1256 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
1257 final_fall_delay.final_phase <<
1258 MSDC_PAD_TUNE_DATRRDLY_S);
1259 final_delay = final_fall_delay.final_phase;
1260 }
1261
1262 if (mmc->selected_mode == MMC_HS_200 ||
1263 mmc->selected_mode == UHS_SDR104)
1264 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M,
1265 host->hs200_write_int_delay <<
1266 MSDC_PAD_TUNE_DATWRDLY_S);
1267
Fabien Parent0d675762020-10-15 18:38:18 +02001268 dev_dbg(dev, "Final data pad delay: %x\n", final_delay);
Weijie Gaod24b6932018-11-15 10:08:04 +08001269
1270 return final_delay == 0xff ? -EIO : 0;
1271}
1272
mingming lee69373bd2019-11-07 19:28:42 +08001273/*
1274 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1275 * together, which can save the tuning time.
1276 */
1277static int msdc_tune_together(struct udevice *dev, u32 opcode)
1278{
Simon Glassc69cda22020-12-03 16:55:20 -07001279 struct msdc_plat *plat = dev_get_plat(dev);
mingming lee69373bd2019-11-07 19:28:42 +08001280 struct msdc_host *host = dev_get_priv(dev);
1281 struct mmc *mmc = &plat->mmc;
1282 u32 rise_delay = 0, fall_delay = 0;
1283 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
1284 u8 final_delay, final_maxlen;
mingming lee69373bd2019-11-07 19:28:42 +08001285 int i, ret;
1286
mingming lee69373bd2019-11-07 19:28:42 +08001287 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1288 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1289
1290 for (i = 0; i < PAD_DELAY_MAX; i++) {
mingming lee3b0397d2019-12-31 11:29:24 +08001291 msdc_set_cmd_delay(host, i);
1292 msdc_set_data_delay(host, i);
mingming lee69373bd2019-11-07 19:28:42 +08001293 ret = mmc_send_tuning(mmc, opcode, NULL);
1294 if (!ret)
1295 rise_delay |= (1 << i);
1296 }
1297
Sean Andersone1ce7902020-09-15 10:44:47 -04001298 final_rise_delay = get_best_delay(dev, host, rise_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001299 if (final_rise_delay.maxlen >= 12 ||
1300 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1301 goto skip_fall;
1302
1303 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1304 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
1305
1306 for (i = 0; i < PAD_DELAY_MAX; i++) {
mingming lee3b0397d2019-12-31 11:29:24 +08001307 msdc_set_cmd_delay(host, i);
1308 msdc_set_data_delay(host, i);
mingming lee69373bd2019-11-07 19:28:42 +08001309 ret = mmc_send_tuning(mmc, opcode, NULL);
1310 if (!ret)
1311 fall_delay |= (1 << i);
1312 }
1313
Sean Andersone1ce7902020-09-15 10:44:47 -04001314 final_fall_delay = get_best_delay(dev, host, fall_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001315
1316skip_fall:
1317 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1318 if (final_maxlen == final_rise_delay.maxlen) {
1319 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1320 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
mingming lee69373bd2019-11-07 19:28:42 +08001321 final_delay = final_rise_delay.final_phase;
1322 } else {
1323 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL);
1324 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL);
mingming lee69373bd2019-11-07 19:28:42 +08001325 final_delay = final_fall_delay.final_phase;
1326 }
1327
mingming lee3b0397d2019-12-31 11:29:24 +08001328 msdc_set_cmd_delay(host, final_delay);
1329 msdc_set_data_delay(host, final_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001330
mingming lee3b0397d2019-12-31 11:29:24 +08001331 dev_info(dev, "Final pad delay: %x\n", final_delay);
mingming lee69373bd2019-11-07 19:28:42 +08001332 return final_delay == 0xff ? -EIO : 0;
1333}
1334
Weijie Gaod24b6932018-11-15 10:08:04 +08001335static int msdc_execute_tuning(struct udevice *dev, uint opcode)
1336{
Simon Glassc69cda22020-12-03 16:55:20 -07001337 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001338 struct msdc_host *host = dev_get_priv(dev);
1339 struct mmc *mmc = &plat->mmc;
mingming lee69373bd2019-11-07 19:28:42 +08001340 int ret = 0;
Weijie Gaod24b6932018-11-15 10:08:04 +08001341
mingming lee69373bd2019-11-07 19:28:42 +08001342 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
1343 ret = msdc_tune_together(dev, opcode);
1344 if (ret == -EIO) {
1345 dev_err(dev, "Tune fail!\n");
1346 return ret;
1347 }
1348
1349 if (mmc->selected_mode == MMC_HS_400) {
1350 clrbits_le32(&host->base->msdc_iocon,
1351 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1352 clrsetbits_le32(&host->base->pad_tune,
1353 MSDC_PAD_TUNE_DATRRDLY_M, 0);
1354
1355 writel(host->hs400_ds_delay, &host->base->pad_ds_tune);
1356 /* for hs400 mode it must be set to 0 */
1357 clrbits_le32(&host->base->patch_bit2,
1358 MSDC_PB2_CFGCRCSTS);
1359 host->hs400_mode = true;
1360 }
1361 goto tune_done;
Weijie Gaod24b6932018-11-15 10:08:04 +08001362 }
1363
mingming lee69373bd2019-11-07 19:28:42 +08001364 if (mmc->selected_mode == MMC_HS_400)
1365 ret = hs400_tune_response(dev, opcode);
1366 else
1367 ret = msdc_tune_response(dev, opcode);
Weijie Gaod24b6932018-11-15 10:08:04 +08001368 if (ret == -EIO) {
1369 dev_err(dev, "Tune response fail!\n");
1370 return ret;
1371 }
1372
mingming lee69373bd2019-11-07 19:28:42 +08001373 if (mmc->selected_mode != MMC_HS_400) {
Weijie Gaod24b6932018-11-15 10:08:04 +08001374 ret = msdc_tune_data(dev, opcode);
mingming lee69373bd2019-11-07 19:28:42 +08001375 if (ret == -EIO) {
Weijie Gaod24b6932018-11-15 10:08:04 +08001376 dev_err(dev, "Tune data fail!\n");
mingming lee69373bd2019-11-07 19:28:42 +08001377 return ret;
1378 }
Weijie Gaod24b6932018-11-15 10:08:04 +08001379 }
1380
mingming lee69373bd2019-11-07 19:28:42 +08001381tune_done:
Weijie Gaod24b6932018-11-15 10:08:04 +08001382 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon);
1383 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune);
mingming lee69373bd2019-11-07 19:28:42 +08001384 host->saved_tune_para.pad_cmd_tune = readl(&host->base->pad_cmd_tune);
Weijie Gaod24b6932018-11-15 10:08:04 +08001385
1386 return ret;
1387}
1388#endif
1389
1390static void msdc_init_hw(struct msdc_host *host)
1391{
1392 u32 val;
1393 void __iomem *tune_reg = &host->base->pad_tune;
1394
1395 if (host->dev_comp->pad_tune0)
1396 tune_reg = &host->base->pad_tune0;
1397
1398 /* Configure to MMC/SD mode, clock free running */
1399 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE);
1400
1401 /* Use PIO mode */
1402 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO);
1403
1404 /* Reset */
1405 msdc_reset_hw(host);
1406
1407 /* Enable/disable hw card detection according to fdt option */
1408 if (host->builtin_cd)
1409 clrsetbits_le32(&host->base->msdc_ps,
1410 MSDC_PS_CDDBCE_M,
1411 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) |
1412 MSDC_PS_CDEN);
1413 else
1414 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN);
1415
1416 /* Clear all interrupts */
1417 val = readl(&host->base->msdc_int);
1418 writel(val, &host->base->msdc_int);
1419
1420 /* Enable data & cmd interrupts */
1421 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
1422
1423 writel(0, tune_reg);
1424 writel(0, &host->base->msdc_iocon);
1425
1426 if (host->r_smpl)
1427 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1428 else
1429 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL);
1430
1431 writel(0x403c0046, &host->base->patch_bit0);
1432 writel(0xffff4089, &host->base->patch_bit1);
1433
1434 if (host->dev_comp->stop_clk_fix)
1435 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
1436 3 << MSDC_PB1_STOP_DLY_S);
1437
1438 if (host->dev_comp->busy_check)
1439 clrbits_le32(&host->base->patch_bit1, (1 << 7));
1440
1441 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL);
1442
1443 if (host->dev_comp->async_fifo) {
1444 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M,
1445 3 << MSDC_PB2_RESPWAIT_S);
1446
1447 if (host->dev_comp->enhance_rx) {
mingming lee3b0397d2019-12-31 11:29:24 +08001448 if (host->top_base)
1449 setbits_le32(&host->top_base->emmc_top_control,
1450 SDC_RX_ENH_EN);
1451 else
1452 setbits_le32(&host->base->sdc_adv_cfg0,
1453 SDC_RX_ENHANCE_EN);
Weijie Gaod24b6932018-11-15 10:08:04 +08001454 } else {
1455 clrsetbits_le32(&host->base->patch_bit2,
1456 MSDC_PB2_RESPSTSENSEL_M,
1457 2 << MSDC_PB2_RESPSTSENSEL_S);
1458 clrsetbits_le32(&host->base->patch_bit2,
1459 MSDC_PB2_CRCSTSENSEL_M,
1460 2 << MSDC_PB2_CRCSTSENSEL_S);
1461 }
1462
1463 /* use async fifo to avoid tune internal delay */
1464 clrbits_le32(&host->base->patch_bit2,
1465 MSDC_PB2_CFGRESP);
1466 clrbits_le32(&host->base->patch_bit2,
1467 MSDC_PB2_CFGCRCSTS);
1468 }
1469
1470 if (host->dev_comp->data_tune) {
1471 setbits_le32(tune_reg,
1472 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
1473 clrsetbits_le32(&host->base->patch_bit0,
1474 MSDC_INT_DAT_LATCH_CK_SEL_M,
1475 host->latch_ck <<
1476 MSDC_INT_DAT_LATCH_CK_SEL_S);
1477 } else {
1478 /* choose clock tune */
1479 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
1480 }
1481
1482 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */
1483 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO);
1484
1485 /* disable detecting SDIO device interrupt function */
1486 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE);
1487
1488 /* Configure to default data timeout */
1489 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
1490 3 << SDC_CFG_DTOC_S);
1491
1492 if (host->dev_comp->stop_clk_fix) {
1493 clrbits_le32(&host->base->sdc_fifo_cfg,
1494 SDC_FIFO_CFG_WRVALIDSEL);
1495 clrbits_le32(&host->base->sdc_fifo_cfg,
1496 SDC_FIFO_CFG_RDVALIDSEL);
1497 }
1498
1499 host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
1500 host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
1501}
1502
1503static void msdc_ungate_clock(struct msdc_host *host)
1504{
1505 clk_enable(&host->src_clk);
1506 clk_enable(&host->h_clk);
Fabien Parentba077e52019-03-24 16:46:32 +01001507 if (host->src_clk_cg.dev)
1508 clk_enable(&host->src_clk_cg);
Weijie Gaod24b6932018-11-15 10:08:04 +08001509}
1510
1511static int msdc_drv_probe(struct udevice *dev)
1512{
1513 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -07001514 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001515 struct msdc_host *host = dev_get_priv(dev);
1516 struct mmc_config *cfg = &plat->cfg;
1517
1518 cfg->name = dev->name;
1519
1520 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev);
1521
1522 host->src_clk_freq = clk_get_rate(&host->src_clk);
1523
1524 if (host->dev_comp->clk_div_bits == 8)
1525 cfg->f_min = host->src_clk_freq / (4 * 255);
1526 else
1527 cfg->f_min = host->src_clk_freq / (4 * 4095);
Weijie Gaod24b6932018-11-15 10:08:04 +08001528
1529 cfg->b_max = 1024;
1530 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1531
1532 host->mmc = &plat->mmc;
1533 host->timeout_ns = 100000000;
Weijie Gao3c92a952019-09-25 17:45:37 +08001534 host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
Weijie Gaod24b6932018-11-15 10:08:04 +08001535
1536#ifdef CONFIG_PINCTRL
1537 pinctrl_select_state(dev, "default");
1538#endif
1539
1540 msdc_ungate_clock(host);
1541 msdc_init_hw(host);
1542
1543 upriv->mmc = &plat->mmc;
1544
1545 return 0;
1546}
1547
1548static int msdc_ofdata_to_platdata(struct udevice *dev)
1549{
Simon Glassc69cda22020-12-03 16:55:20 -07001550 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001551 struct msdc_host *host = dev_get_priv(dev);
1552 struct mmc_config *cfg = &plat->cfg;
mingming lee3b0397d2019-12-31 11:29:24 +08001553 fdt_addr_t base, top_base;
Weijie Gaod24b6932018-11-15 10:08:04 +08001554 int ret;
1555
mingming lee3b0397d2019-12-31 11:29:24 +08001556 base = dev_read_addr(dev);
1557 if (base == FDT_ADDR_T_NONE)
Weijie Gaod24b6932018-11-15 10:08:04 +08001558 return -EINVAL;
mingming lee3b0397d2019-12-31 11:29:24 +08001559 host->base = map_sysmem(base, 0);
1560
1561 top_base = dev_read_addr_index(dev, 1);
1562 if (top_base == FDT_ADDR_T_NONE)
1563 host->top_base = NULL;
1564 else
1565 host->top_base = map_sysmem(top_base, 0);
Weijie Gaod24b6932018-11-15 10:08:04 +08001566
1567 ret = mmc_of_parse(dev, cfg);
1568 if (ret)
1569 return ret;
1570
1571 ret = clk_get_by_name(dev, "source", &host->src_clk);
1572 if (ret < 0)
1573 return ret;
1574
1575 ret = clk_get_by_name(dev, "hclk", &host->h_clk);
1576 if (ret < 0)
1577 return ret;
1578
Fabien Parentba077e52019-03-24 16:46:32 +01001579 clk_get_by_name(dev, "source_cg", &host->src_clk_cg); /* optional */
1580
Fabien Parentb5096f12019-03-24 16:46:34 +01001581#if CONFIG_IS_ENABLED(DM_GPIO)
Weijie Gaod24b6932018-11-15 10:08:04 +08001582 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
1583 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
1584#endif
1585
1586 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0);
1587 host->hs200_cmd_int_delay =
1588 dev_read_u32_default(dev, "cmd_int_delay", 0);
1589 host->hs200_write_int_delay =
1590 dev_read_u32_default(dev, "write_int_delay", 0);
1591 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0);
1592 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0);
1593 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0);
Weijie Gao77ebea22019-09-25 17:45:38 +08001594 host->cd_active_high = dev_read_bool(dev, "cd-active-high");
Weijie Gaod24b6932018-11-15 10:08:04 +08001595
1596 return 0;
1597}
1598
1599static int msdc_drv_bind(struct udevice *dev)
1600{
Simon Glassc69cda22020-12-03 16:55:20 -07001601 struct msdc_plat *plat = dev_get_plat(dev);
Weijie Gaod24b6932018-11-15 10:08:04 +08001602
1603 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1604}
1605
1606static const struct dm_mmc_ops msdc_ops = {
1607 .send_cmd = msdc_ops_send_cmd,
1608 .set_ios = msdc_ops_set_ios,
1609 .get_cd = msdc_ops_get_cd,
1610 .get_wp = msdc_ops_get_wp,
1611#ifdef MMC_SUPPORTS_TUNING
1612 .execute_tuning = msdc_execute_tuning,
1613#endif
1614};
1615
Weijie Gao3c92a952019-09-25 17:45:37 +08001616static const struct msdc_compatible mt7620_compat = {
1617 .clk_div_bits = 8,
1618 .sclk_cycle_shift = 16,
1619 .pad_tune0 = false,
1620 .async_fifo = false,
1621 .data_tune = false,
1622 .busy_check = false,
1623 .stop_clk_fix = false,
1624 .enhance_rx = false
1625};
1626
Sam Shih25273db2020-01-10 16:30:32 +08001627static const struct msdc_compatible mt7622_compat = {
1628 .clk_div_bits = 12,
1629 .pad_tune0 = true,
1630 .async_fifo = true,
1631 .data_tune = true,
1632 .busy_check = true,
1633 .stop_clk_fix = true,
1634};
1635
Weijie Gaod24b6932018-11-15 10:08:04 +08001636static const struct msdc_compatible mt7623_compat = {
1637 .clk_div_bits = 12,
Weijie Gao3c92a952019-09-25 17:45:37 +08001638 .sclk_cycle_shift = 20,
Weijie Gaod24b6932018-11-15 10:08:04 +08001639 .pad_tune0 = true,
1640 .async_fifo = true,
1641 .data_tune = true,
1642 .busy_check = false,
1643 .stop_clk_fix = false,
1644 .enhance_rx = false
1645};
1646
mingming lee3b0397d2019-12-31 11:29:24 +08001647static const struct msdc_compatible mt8512_compat = {
1648 .clk_div_bits = 12,
1649 .sclk_cycle_shift = 20,
1650 .pad_tune0 = true,
1651 .async_fifo = true,
1652 .data_tune = true,
1653 .busy_check = true,
1654 .stop_clk_fix = true,
1655};
1656
Fabien Parenta9332662019-03-24 16:46:33 +01001657static const struct msdc_compatible mt8516_compat = {
1658 .clk_div_bits = 12,
Weijie Gao3c92a952019-09-25 17:45:37 +08001659 .sclk_cycle_shift = 20,
Fabien Parenta9332662019-03-24 16:46:33 +01001660 .pad_tune0 = true,
1661 .async_fifo = true,
1662 .data_tune = true,
1663 .busy_check = true,
1664 .stop_clk_fix = true,
1665};
1666
Fabien Parent908d0062019-08-12 20:26:58 +02001667static const struct msdc_compatible mt8183_compat = {
1668 .clk_div_bits = 12,
Weijie Gao3c92a952019-09-25 17:45:37 +08001669 .sclk_cycle_shift = 20,
Fabien Parent908d0062019-08-12 20:26:58 +02001670 .pad_tune0 = true,
1671 .async_fifo = true,
1672 .data_tune = true,
1673 .busy_check = true,
1674 .stop_clk_fix = true,
1675};
1676
Weijie Gaod24b6932018-11-15 10:08:04 +08001677static const struct udevice_id msdc_ids[] = {
Weijie Gao3c92a952019-09-25 17:45:37 +08001678 { .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
Sam Shih25273db2020-01-10 16:30:32 +08001679 { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
Weijie Gaod24b6932018-11-15 10:08:04 +08001680 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
mingming lee3b0397d2019-12-31 11:29:24 +08001681 { .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
Fabien Parenta9332662019-03-24 16:46:33 +01001682 { .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
Fabien Parent908d0062019-08-12 20:26:58 +02001683 { .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
Weijie Gaod24b6932018-11-15 10:08:04 +08001684 {}
1685};
1686
1687U_BOOT_DRIVER(mtk_sd_drv) = {
1688 .name = "mtk_sd",
1689 .id = UCLASS_MMC,
1690 .of_match = msdc_ids,
1691 .ofdata_to_platdata = msdc_ofdata_to_platdata,
1692 .bind = msdc_drv_bind,
1693 .probe = msdc_drv_probe,
1694 .ops = &msdc_ops,
Simon Glasscaa4daa2020-12-03 16:55:18 -07001695 .plat_auto = sizeof(struct msdc_plat),
Simon Glass41575d82020-12-03 16:55:17 -07001696 .priv_auto = sizeof(struct msdc_host),
Weijie Gaod24b6932018-11-15 10:08:04 +08001697};