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wdenka522fa02004-01-04 22:51:12 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenka522fa02004-01-04 22:51:12 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1c437712004-01-16 00:30:56 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka522fa02004-01-04 22:51:12 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
wdenkc40b2952004-03-13 23:29:43 +000036#define CONFIG_HMI10
wdenka522fa02004-01-04 22:51:12 +000037#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
38#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
39
40#define CONFIG_LCD
41#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
42
43#ifdef CONFIG_LCD /* with LCD controller ? */
wdenk1c437712004-01-16 00:30:56 +000044#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenka522fa02004-01-04 22:51:12 +000045#endif
46
wdenk1c437712004-01-16 00:30:56 +000047#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenka522fa02004-01-04 22:51:12 +000048#undef CONFIG_8xx_CONS_SMC2
49#undef CONFIG_8xx_CONS_NONE
50#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
51
wdenk1c437712004-01-16 00:30:56 +000052#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
wdenkc837dcb2004-01-20 23:12:12 +000053#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
wdenk1c437712004-01-16 00:30:56 +000054#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
wdenk1c437712004-01-16 00:30:56 +000056
57#define CONFIG_BOOTCOUNT_LIMIT
wdenka522fa02004-01-04 22:51:12 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
63#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
64
65#undef CONFIG_BOOTARGS
66
wdenk1c437712004-01-16 00:30:56 +000067#define CONFIG_EXTRA_ENV_SETTINGS \
wdenka522fa02004-01-04 22:51:12 +000068 "netdev=eth0\0" \
69 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "nfsroot=${serverip}:${rootpath}\0" \
wdenka522fa02004-01-04 22:51:12 +000071 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "addip=setenv bootargs ${bootargs} " \
73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
74 ":${hostname}:${netdev}:off panic=1\0" \
wdenka522fa02004-01-04 22:51:12 +000075 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "bootm ${kernel_addr}\0" \
wdenka522fa02004-01-04 22:51:12 +000077 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenka522fa02004-01-04 22:51:12 +000080 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenkc40b2952004-03-13 23:29:43 +000081 "bootfile=/tftpboot/HMI10/uImage\0" \
wdenka522fa02004-01-04 22:51:12 +000082 "kernel_addr=40040000\0" \
83 "ramdisk_addr=40100000\0" \
84 ""
85#define CONFIG_BOOTCOMMAND "run flash_self"
86
wdenkc837dcb2004-01-20 23:12:12 +000087#define CONFIG_BOARD_EARLY_INIT_R 1
88#define CONFIG_MISC_INIT_R 1
wdenk1c437712004-01-16 00:30:56 +000089
wdenka522fa02004-01-04 22:51:12 +000090#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
91#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
92
93/* enable I2C and select the hardware/software driver */
94#undef CONFIG_HARD_I2C /* I2C with hardware support */
95#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96
97#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
98#define CFG_I2C_SLAVE 0xFE
99
100/* Software (bit-bang) I2C driver configuration */
101#define PB_SCL 0x00000020 /* PB 26 */
102#define PB_SDA 0x00000010 /* PB 27 */
103
104#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
105#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
106#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
107#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
108#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenk1c437712004-01-16 00:30:56 +0000109 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenka522fa02004-01-04 22:51:12 +0000110#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenk1c437712004-01-16 00:30:56 +0000111 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenka522fa02004-01-04 22:51:12 +0000112#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
113
114#undef CONFIG_WATCHDOG /* watchdog disabled */
115
116#define CONFIG_STATUS_LED 1 /* Status LED enabled */
117
118#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
119
Jon Loeliger7be044e2007-07-09 21:24:19 -0500120/*
121 * BOOTP options
122 */
123#define CONFIG_BOOTP_SUBNETMASK
124#define CONFIG_BOOTP_GATEWAY
125#define CONFIG_BOOTP_HOSTNAME
126#define CONFIG_BOOTP_BOOTPATH
127#define CONFIG_BOOTP_BOOTFILESIZE
128
wdenka522fa02004-01-04 22:51:12 +0000129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
133#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
134#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
135
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500136
137/*
138 * Command line configuration.
139 */
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DATE
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_FAT
146#define CONFIG_CMD_I2C
147#define CONFIG_CMD_IDE
148#define CONFIG_CMD_NFS
149#define CONFIG_CMD_SNTP
150
wdenka522fa02004-01-04 22:51:12 +0000151#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500152 #define CONFIG_CMD_BMP
wdenka522fa02004-01-04 22:51:12 +0000153#endif
154
wdenka522fa02004-01-04 22:51:12 +0000155
156/*
157 * Miscellaneous configurable options
158 */
wdenk1c437712004-01-16 00:30:56 +0000159#define CFG_LONGHELP /* undef to save memory */
160#define CFG_PROMPT "=> " /* Monitor Command Prompt */
wdenka522fa02004-01-04 22:51:12 +0000161
162#if 0
wdenk1c437712004-01-16 00:30:56 +0000163#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
wdenka522fa02004-01-04 22:51:12 +0000164#endif
165#ifdef CFG_HUSH_PARSER
wdenk1c437712004-01-16 00:30:56 +0000166#define CFG_PROMPT_HUSH_PS2 "> "
wdenka522fa02004-01-04 22:51:12 +0000167#endif
168
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500169#if defined(CONFIG_CMD_KGDB)
wdenk1c437712004-01-16 00:30:56 +0000170#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka522fa02004-01-04 22:51:12 +0000171#else
wdenk1c437712004-01-16 00:30:56 +0000172#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenka522fa02004-01-04 22:51:12 +0000173#endif
wdenk1c437712004-01-16 00:30:56 +0000174#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
175#define CFG_MAXARGS 16 /* max number of command args */
wdenka522fa02004-01-04 22:51:12 +0000176#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
177
178#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
179#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
180
wdenk1c437712004-01-16 00:30:56 +0000181#define CFG_LOAD_ADDR 0x100000 /* default load address */
wdenka522fa02004-01-04 22:51:12 +0000182
wdenk1c437712004-01-16 00:30:56 +0000183#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenka522fa02004-01-04 22:51:12 +0000184
185#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
186
187/*
188 * Low Level Configuration Settings
189 * (address mappings, register initial values, etc.)
190 * You should know what you are doing if you make changes here.
191 */
192/*-----------------------------------------------------------------------
193 * Internal Memory Mapped Register
194 */
195#define CFG_IMMR 0xFFF00000
196
197/*-----------------------------------------------------------------------
198 * Definitions for initial stack pointer and data area (in DPRAM)
199 */
200#define CFG_INIT_RAM_ADDR CFG_IMMR
wdenk1c437712004-01-16 00:30:56 +0000201#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
202#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
wdenka522fa02004-01-04 22:51:12 +0000203#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk1c437712004-01-16 00:30:56 +0000204#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
wdenka522fa02004-01-04 22:51:12 +0000205
206/*-----------------------------------------------------------------------
207 * Start addresses for the final memory configuration
208 * (Set up by the startup code)
209 * Please note that CFG_SDRAM_BASE _must_ start at 0
210 */
wdenk1c437712004-01-16 00:30:56 +0000211#define CFG_SDRAM_BASE 0x00000000
wdenka522fa02004-01-04 22:51:12 +0000212#define CFG_FLASH_BASE 0x40000000
wdenk1c437712004-01-16 00:30:56 +0000213#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenka522fa02004-01-04 22:51:12 +0000214#define CFG_MONITOR_BASE CFG_FLASH_BASE
wdenk1c437712004-01-16 00:30:56 +0000215#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenka522fa02004-01-04 22:51:12 +0000216
217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
221 */
wdenk1c437712004-01-16 00:30:56 +0000222#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka522fa02004-01-04 22:51:12 +0000223
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
227#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
228#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
229
230#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
231#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
232
wdenk1c437712004-01-16 00:30:56 +0000233#define CFG_ENV_IS_IN_FLASH 1
234#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
235#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenka522fa02004-01-04 22:51:12 +0000236
237/* Address and size of Redundant Environment Sector */
238#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
239#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
240
241/*-----------------------------------------------------------------------
242 * Hardware Information Block
243 */
244#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
wdenk1c437712004-01-16 00:30:56 +0000245#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
wdenka522fa02004-01-04 22:51:12 +0000246#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
247
248/*-----------------------------------------------------------------------
249 * Cache Configuration
250 */
251#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500252#if defined(CONFIG_CMD_KGDB)
wdenka522fa02004-01-04 22:51:12 +0000253#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
254#endif
255
256/*-----------------------------------------------------------------------
257 * SYPCR - System Protection Control 11-9
258 * SYPCR can only be written once after reset!
259 *-----------------------------------------------------------------------
260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
261 */
262#if defined(CONFIG_WATCHDOG)
263#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
265#else
266#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
267#endif
268
269/*-----------------------------------------------------------------------
270 * SIUMCR - SIU Module Configuration 11-6
271 *-----------------------------------------------------------------------
272 * PCMCIA config., multi-function pin tri-state
273 */
wdenk1c437712004-01-16 00:30:56 +0000274#ifndef CONFIG_CAN_DRIVER
wdenka522fa02004-01-04 22:51:12 +0000275#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
276#else /* we must activate GPL5 in the SIUMCR for CAN */
277#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
278#endif /* CONFIG_CAN_DRIVER */
279
280/*-----------------------------------------------------------------------
281 * TBSCR - Time Base Status and Control 11-26
282 *-----------------------------------------------------------------------
283 * Clear Reference Interrupt Status, Timebase freezing enabled
284 */
285#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
286
287/*-----------------------------------------------------------------------
288 * RTCSC - Real-Time Clock Status and Control Register 11-27
289 *-----------------------------------------------------------------------
290 */
291#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
292
293/*-----------------------------------------------------------------------
294 * PISCR - Periodic Interrupt Status and Control 11-31
295 *-----------------------------------------------------------------------
296 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
297 */
298#define CFG_PISCR (PISCR_PS | PISCR_PITF)
299
300/*-----------------------------------------------------------------------
301 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
302 *-----------------------------------------------------------------------
303 * Reset PLL lock status sticky bit, timer expired status bit and timer
304 * interrupt status bit
305 *
306 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
307 */
wdenka522fa02004-01-04 22:51:12 +0000308#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenka522fa02004-01-04 22:51:12 +0000309
310/*-----------------------------------------------------------------------
311 * SCCR - System Clock and reset Control Register 15-27
312 *-----------------------------------------------------------------------
313 * Set clock output, timebase and RTC source and divider,
314 * power management and some other internal clocks
315 */
316#define SCCR_MASK SCCR_EBDF11
wdenkc3f4d172004-06-25 23:35:58 +0000317#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenka522fa02004-01-04 22:51:12 +0000318 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
319 SCCR_DFALCD00)
wdenka522fa02004-01-04 22:51:12 +0000320
321/*-----------------------------------------------------------------------
322 * PCMCIA stuff
323 *-----------------------------------------------------------------------
324 *
325 */
wdenka522fa02004-01-04 22:51:12 +0000326#define CFG_PCMCIA_MEM_ADDR (0xE0100000)
327#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
328#define CFG_PCMCIA_DMA_ADDR (0xE4100000)
329#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
330#define CFG_PCMCIA_ATTRB_ADDR (0xE8100000)
331#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
332#define CFG_PCMCIA_IO_ADDR (0xEC100000)
333#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk68766092004-01-29 09:22:58 +0000334#define PCMCIA_MEM_WIN_NO 5
wdenk1c437712004-01-16 00:30:56 +0000335#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
wdenka522fa02004-01-04 22:51:12 +0000336
337/*-----------------------------------------------------------------------
338 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
339 *-----------------------------------------------------------------------
340 */
341
wdenk1c437712004-01-16 00:30:56 +0000342#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenka522fa02004-01-04 22:51:12 +0000343
wdenk1c437712004-01-16 00:30:56 +0000344#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
wdenka522fa02004-01-04 22:51:12 +0000345#undef CONFIG_IDE_RESET /* reset for ide not supported */
wdenk1c437712004-01-16 00:30:56 +0000346#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
347#define CONFIG_IDE_LED 1 /* LED for ide supported */
348#endif
wdenka522fa02004-01-04 22:51:12 +0000349
350#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
351#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
352
353#define CFG_ATA_IDE0_OFFSET 0x0000
354
355#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
356
357/* Offset for data I/O */
358#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
359
360/* Offset for normal register accesses */
361#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
362
363/* Offset for alternate registers */
364#define CFG_ATA_ALT_OFFSET 0x0100
365
366/*-----------------------------------------------------------------------
367 *
368 *-----------------------------------------------------------------------
369 *
370 */
wdenk1c437712004-01-16 00:30:56 +0000371#define CFG_DER 0
wdenka522fa02004-01-04 22:51:12 +0000372
373/*
374 * Init Memory Controller:
375 *
376 * BR0/1 and OR0/1 (FLASH)
377 */
378
379#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
380#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
381
382/* used to re-map FLASH both when starting from SRAM or FLASH:
383 * restrict access enough to keep SRAM working (if any)
384 * but not too much to meddle with FLASH accesses
385 */
386#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
387#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
388
389/*
390 * FLASH timing:
391 */
wdenka522fa02004-01-04 22:51:12 +0000392#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
393 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenka522fa02004-01-04 22:51:12 +0000394
395#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
396#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
397#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
398
399#define CFG_OR1_REMAP CFG_OR0_REMAP
400#define CFG_OR1_PRELIM CFG_OR0_PRELIM
401#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
402
403/*
404 * BR2/3 and OR2/3 (SDRAM)
405 *
406 */
407#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
408#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenk1c437712004-01-16 00:30:56 +0000409#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
wdenka522fa02004-01-04 22:51:12 +0000410
411/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
412#define CFG_OR_TIMING_SDRAM 0x00000A00
413
414#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
415#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
416
wdenk1c437712004-01-16 00:30:56 +0000417#ifndef CONFIG_CAN_DRIVER
418#define CFG_OR3_PRELIM CFG_OR2_PRELIM
wdenka522fa02004-01-04 22:51:12 +0000419#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
420#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
wdenk1c437712004-01-16 00:30:56 +0000421#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
wdenka522fa02004-01-04 22:51:12 +0000422#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
423#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
424#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
425 BR_PS_8 | BR_MS_UPMB | BR_V )
426#endif /* CONFIG_CAN_DRIVER */
427
428/*
429 * Memory Periodic Timer Prescaler
430 *
431 * The Divider for PTA (refresh timer) configuration is based on an
432 * example SDRAM configuration (64 MBit, one bank). The adjustment to
433 * the number of chip selects (NCS) and the actually needed refresh
434 * rate is done by setting MPTPR.
435 *
436 * PTA is calculated from
437 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
438 *
439 * gclk CPU clock (not bus clock!)
440 * Trefresh Refresh cycle * 4 (four word bursts used)
441 *
wdenk1c437712004-01-16 00:30:56 +0000442 * 4096 Rows from SDRAM example configuration
443 * 1000 factor s -> ms
444 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
445 * 4 Number of refresh cycles per period
446 * 64 Refresh cycle in ms per number of rows
wdenka522fa02004-01-04 22:51:12 +0000447 * --------------------------------------------
448 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
449 *
450 * 50 MHz => 50.000.000 / Divider = 98
451 * 66 Mhz => 66.000.000 / Divider = 129
452 * 80 Mhz => 80.000.000 / Divider = 156
453 */
wdenkc3f4d172004-06-25 23:35:58 +0000454
455#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
456#define CFG_MAMR_PTA 98
wdenka522fa02004-01-04 22:51:12 +0000457
458/*
459 * For 16 MBit, refresh rates could be 31.3 us
460 * (= 64 ms / 2K = 125 / quad bursts).
461 * For a simpler initialization, 15.6 us is used instead.
462 *
463 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
464 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
465 */
466#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
467#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
468
469/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
470#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
471#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
472
473/*
474 * MAMR settings for SDRAM
475 */
476
477/* 8 column SDRAM */
478#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
479 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481/* 9 column SDRAM */
482#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
483 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
484 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
485
486
487/*
488 * Internal Definitions
489 *
490 * Boot Flags
491 */
wdenk1c437712004-01-16 00:30:56 +0000492#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenka522fa02004-01-04 22:51:12 +0000493#define BOOTFLAG_WARM 0x02 /* Software reboot */
494
495#endif /* __CONFIG_H */