blob: 2f64ec238c652ef3e3862d8aa53ca4aa50a47d43 [file] [log] [blame]
wdenk8966f332002-10-31 23:30:59 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Config header file for Hymod board
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_HYMOD 1 /* ...on a Hymod board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk8966f332002-10-31 23:30:59 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
41
wdenk8966f332002-10-31 23:30:59 +000042#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
43
44/*
45 * select serial console configuration
46 *
47 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
49 * for SCC).
50 *
51 * if CONFIG_CONS_NONE is defined, then the serial console routines must
52 * defined elsewhere (for example, on the cogent platform, there are serial
53 * ports on the motherboard which are used for the serial console - see
54 * cogent/cma101/serial.[ch]).
55 */
56#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
57#define CONFIG_CONS_ON_SCC /* define if console on SCC */
58#undef CONFIG_CONS_NONE /* define if console on something else*/
59#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
60#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
61#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
62#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
63
64/*
65 * select ethernet configuration
66 *
67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * for FCC)
70 *
71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050072 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk8966f332002-10-31 23:30:59 +000073 */
74#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76#undef CONFIG_ETHER_NONE /* define if ether on something else */
77#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
wdenk6dd652f2003-06-19 23:40:20 +000078#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
79
80#ifdef CONFIG_ETHER_ON_FCC
wdenk8966f332002-10-31 23:30:59 +000081
82#if (CONFIG_ETHER_INDEX == 1)
83
84/*
85 * - Rx-CLK is CLK10
86 * - Tx-CLK is CLK11
87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
88 * - Enable Full Duplex in FSMR
89 */
90# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
91# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
92# define CFG_CPMFCR_RAMTYPE 0
93# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
94
wdenk6dd652f2003-06-19 23:40:20 +000095# define MDIO_PORT 0 /* Port A */
96# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
97# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
98
wdenk8966f332002-10-31 23:30:59 +000099#elif (CONFIG_ETHER_INDEX == 2)
100
101/*
102 * - Rx-CLK is CLK13
103 * - Tx-CLK is CLK14
104 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
105 * - Enable Full Duplex in FSMR
106 */
107# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
108# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
109# define CFG_CPMFCR_RAMTYPE 0
110# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
111
wdenk6dd652f2003-06-19 23:40:20 +0000112# define MDIO_PORT 0 /* Port A */
113# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
114# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
115
wdenk8966f332002-10-31 23:30:59 +0000116#elif (CONFIG_ETHER_INDEX == 3)
117
118/*
119 * - Rx-CLK is CLK15
120 * - Tx-CLK is CLK16
121 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
122 * - Enable Full Duplex in FSMR
123 */
124# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
125# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
126# define CFG_CPMFCR_RAMTYPE 0
127# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
128
wdenk6dd652f2003-06-19 23:40:20 +0000129# define MDIO_PORT 0 /* Port A */
130# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
131# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
132
wdenk8966f332002-10-31 23:30:59 +0000133#endif /* CONFIG_ETHER_INDEX */
134
wdenk6dd652f2003-06-19 23:40:20 +0000135#define CONFIG_MII /* MII PHY management */
136#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
137
138#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
139#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
140#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
141
142#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
143 else iop->pdat &= ~MDIO_DATA_PINMASK
144
145#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
146 else iop->pdat &= ~MDIO_CLCK_PINMASK
147
148#define MIIDELAY udelay(1)
149
150#endif /* CONFIG_ETHER_ON_FCC */
151
wdenk8966f332002-10-31 23:30:59 +0000152
153/* other options */
154#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
wdenk6dd652f2003-06-19 23:40:20 +0000155#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
wdenk8966f332002-10-31 23:30:59 +0000156
157/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
158#ifdef DEBUG
159#define CONFIG_8260_CLKIN 33333333 /* in Hz */
160#else
161#define CONFIG_8260_CLKIN 66666666 /* in Hz */
162#endif
163
164#if defined(CONFIG_CONS_USE_EXTC)
165#define CONFIG_BAUDRATE 115200
166#else
wdenk6dd652f2003-06-19 23:40:20 +0000167#define CONFIG_BAUDRATE 9600
wdenk8966f332002-10-31 23:30:59 +0000168#endif
169
170/* default ip addresses - these will be overridden */
171#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
172#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
173
wdenk6dd652f2003-06-19 23:40:20 +0000174#define CONFIG_LAST_STAGE_INIT
175
Jon Loeliger48d5d102007-07-04 22:32:25 -0500176/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500177 * BOOTP options
178 */
179#define CONFIG_BOOTP_BOOTFILESIZE
180#define CONFIG_BOOTP_BOOTPATH
181#define CONFIG_BOOTP_GATEWAY
182#define CONFIG_BOOTP_HOSTNAME
183
184
185/*
Jon Loeliger48d5d102007-07-04 22:32:25 -0500186 * Command line configuration.
187 */
188#include <config_cmd_all.h>
wdenk8966f332002-10-31 23:30:59 +0000189
Jon Loeliger48d5d102007-07-04 22:32:25 -0500190#undef CONFIG_CMD_BEDBUG
191#undef CONFIG_CMD_BMP
192#undef CONFIG_CMD_DISPLAY
193#undef CONFIG_CMD_DOC
194#undef CONFIG_CMD_EXT2
195#undef CONFIG_CMD_FDC
196#undef CONFIG_CMD_FDOS
197#undef CONFIG_CMD_FPGA
198#undef CONFIG_CMD_HWFLOW
199#undef CONFIG_CMD_IDE
200#undef CONFIG_CMD_JFFS2
201#undef CONFIG_CMD_NAND
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200202#undef CONFIG_CMD_MFSL
Jon Loeliger48d5d102007-07-04 22:32:25 -0500203#undef CONFIG_CMD_MMC
204#undef CONFIG_CMD_PCMCIA
205#undef CONFIG_CMD_PCI
206#undef CONFIG_CMD_USB
207#undef CONFIG_CMD_REISER
208#undef CONFIG_CMD_SCSI
209#undef CONFIG_CMD_SPI
210#undef CONFIG_CMD_UNIVERSE
211#undef CONFIG_CMD_VFD
212#undef CONFIG_CMD_XIMG
213
wdenk8966f332002-10-31 23:30:59 +0000214
215#ifdef DEBUG
216#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenk6dd652f2003-06-19 23:40:20 +0000217#else
218#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
219#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
220#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
221/* Be selective on what keys can delay or stop the autoboot process
222 * To stop use: " "
223 */
224#define CONFIG_AUTOBOOT_KEYED
225#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
226 "press <SPACE> to stop\n"
227#define CONFIG_AUTOBOOT_STOP_STR " "
228#undef CONFIG_AUTOBOOT_DELAY_STR
229#define DEBUG_BOOTKEYS 0
wdenk8966f332002-10-31 23:30:59 +0000230#endif
231
Jon Loeliger48d5d102007-07-04 22:32:25 -0500232#if defined(CONFIG_CMD_KGDB)
wdenk8966f332002-10-31 23:30:59 +0000233#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
234#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
235#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
236#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
237#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
238#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
239#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
240# if defined(CONFIG_KGDB_USE_EXTC)
wdenk592c5ca2003-06-21 00:17:24 +0000241#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000242# else
wdenk6dd652f2003-06-19 23:40:20 +0000243#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000244# endif
245#endif
246
247#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
248
249#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
250
251/*
252 * Hymod specific configurable options
253 */
254#undef CFG_HYMOD_DBLEDS /* walk mezz board LEDs */
255
256/*
257 * Miscellaneous configurable options
258 */
259#define CFG_LONGHELP /* undef to save memory */
260#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500261#if defined(CONFIG_CMD_KGDB)
wdenk8966f332002-10-31 23:30:59 +0000262#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
263#else
264#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
265#endif
266#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
267#define CFG_MAXARGS 16 /* max number of command args */
268#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
269
270#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
271#define CFG_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
272
wdenk6dd652f2003-06-19 23:40:20 +0000273#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
274
wdenk8966f332002-10-31 23:30:59 +0000275#define CFG_LOAD_ADDR 0x100000 /* default load address */
276
277#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
278
279#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
280
281#define CFG_I2C_SPEED 50000
282#define CFG_I2C_SLAVE 0x7e
283
284/* these are for the ST M24C02 2kbit serial i2c eeprom */
285#define CFG_I2C_EEPROM_ADDR 0x50 /* base address */
286#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenk6dd652f2003-06-19 23:40:20 +0000287/* mask of address bits that overflow into the "EEPROM chip address" */
288#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
289
290#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* write eeprom in pages */
291#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
292#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
293
294#define CFG_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
295
wdenk8966f332002-10-31 23:30:59 +0000296#define CFG_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
297
298/*
wdenk6dd652f2003-06-19 23:40:20 +0000299 * standard dtt sensor configuration - bottom bit will determine local or
300 * remote sensor of the ADM1021, the rest determines index into
301 * CFG_DTT_ADM1021 array below.
302 *
303 * On HYMOD board, the remote sensor should be connected to the MPC8260
304 * temperature diode thingy, but an errata said this didn't work and
305 * should be disabled - so it isn't connected.
306 */
307#if 0
308#define CONFIG_DTT_SENSORS { 0, 1 }
309#else
310#define CONFIG_DTT_SENSORS { 0 }
311#endif
312
313/*
314 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
315 * there will be one entry in this array for each two (dummy) sensors in
316 * CONFIG_DTT_SENSORS.
317 *
318 * For HYMOD board:
319 * - only one ADM1021
320 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
321 * - conversion rate 0x02 = 0.25 conversions/second
322 * - ALERT ouput disabled
323 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
324 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
325 */
326#define CFG_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
327
328/*
wdenk8966f332002-10-31 23:30:59 +0000329 * Low Level Configuration Settings
330 * (address mappings, register initial values, etc.)
331 * You should know what you are doing if you make changes here.
332 */
333
334/*-----------------------------------------------------------------------
335 * Hard Reset Configuration Words
336 *
337 * if you change bits in the HRCW, you must also change the CFG_*
338 * defines for the various registers affected by the HRCW e.g. changing
339 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
340 */
341#ifdef DEBUG
342#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
343 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
344 HRCW_MODCK_H0010)
345#else
346#define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
347 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
348 HRCW_MODCK_H0101)
349#endif
350/* no slaves so just duplicate the master hrcw */
351#define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
352#define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
353#define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
354#define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
355#define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
356#define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
357#define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
358
359/*-----------------------------------------------------------------------
360 * Internal Memory Mapped Register
361 */
362#define CFG_IMMR 0xF0000000
363
364/*-----------------------------------------------------------------------
365 * Definitions for initial stack pointer and data area (in DPRAM)
366 */
367#define CFG_INIT_RAM_ADDR CFG_IMMR
368#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
369#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
370#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
371#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
372
373/*-----------------------------------------------------------------------
374 * Start addresses for the final memory configuration
375 * (Set up by the startup code)
376 * Please note that CFG_SDRAM_BASE _must_ start at 0
377 */
378#define CFG_SDRAM_BASE 0x00000000
379#define CFG_FLASH_BASE TEXT_BASE
380#define CFG_MONITOR_BASE TEXT_BASE
381#define CFG_FPGA_BASE 0x80000000
382/*
383 * unfortunately, CFG_MONITOR_LEN must include the
384 * (very large i.e. 256kB) environment flash sector
385 */
386#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
387#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
388
389/*
390 * For booting Linux, the board info and command line data
391 * have to be in the first 8 MB of memory, since this is
392 * the maximum mapped by the Linux kernel during initialization.
393 */
394#define CFG_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
395
396/*-----------------------------------------------------------------------
397 * FLASH organization
398 */
399#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
400#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
401
402#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
403#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
404
wdenk8966f332002-10-31 23:30:59 +0000405#define CFG_ENV_IS_IN_FLASH 1
wdenk592c5ca2003-06-21 00:17:24 +0000406#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk8966f332002-10-31 23:30:59 +0000407#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
408#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
409
410/*-----------------------------------------------------------------------
411 * Cache Configuration
412 */
413#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500414#if defined(CONFIG_CMD_KGDB)
wdenk8966f332002-10-31 23:30:59 +0000415#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
416#endif
417
418/*-----------------------------------------------------------------------
419 * HIDx - Hardware Implementation-dependent Registers 2-11
420 *-----------------------------------------------------------------------
421 * HID0 also contains cache control - initially enable both caches and
422 * invalidate contents, then the final state leaves only the instruction
423 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
424 * but Soft reset does not.
425 *
426 * HID1 has only read-only information - nothing to set.
427 */
428#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
429 HID0_IFEM|HID0_ABE)
430#ifdef DEBUG
431#define CFG_HID0_FINAL 0
432#else
433#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
434#endif
435#define CFG_HID2 0
436
437/*-----------------------------------------------------------------------
438 * RMR - Reset Mode Register 5-5
439 *-----------------------------------------------------------------------
440 * turn on Checkstop Reset Enable
441 */
442#ifdef DEBUG
443#define CFG_RMR 0
444#else
445#define CFG_RMR RMR_CSRE
446#endif
447
448/*-----------------------------------------------------------------------
449 * BCR - Bus Configuration 4-25
450 *-----------------------------------------------------------------------
451 */
452#define CFG_BCR (BCR_ETM)
453
454/*-----------------------------------------------------------------------
455 * SIUMCR - SIU Module Configuration 4-31
456 *-----------------------------------------------------------------------
457 */
458#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
459 SIUMCR_APPC10|SIUMCR_MMR11)
460
461/*-----------------------------------------------------------------------
462 * SYPCR - System Protection Control 4-35
463 * SYPCR can only be written once after reset!
464 *-----------------------------------------------------------------------
465 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
466 */
467#if defined(CONFIG_WATCHDOG)
468#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
469 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
470#else
471#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
472 SYPCR_SWRI|SYPCR_SWP)
473#endif /* CONFIG_WATCHDOG */
474
475/*-----------------------------------------------------------------------
476 * TMCNTSC - Time Counter Status and Control 4-40
477 *-----------------------------------------------------------------------
478 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
479 * and enable Time Counter
480 */
481#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
482
483/*-----------------------------------------------------------------------
484 * PISCR - Periodic Interrupt Status and Control 4-42
485 *-----------------------------------------------------------------------
486 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
487 * Periodic timer
488 */
489#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
490
491/*-----------------------------------------------------------------------
492 * SCCR - System Clock Control 9-8
493 *-----------------------------------------------------------------------
494 * Ensure DFBRG is Divide by 16
495 */
496#define CFG_SCCR (SCCR_DFBRG01)
497
498/*-----------------------------------------------------------------------
499 * RCCR - RISC Controller Configuration 13-7
500 *-----------------------------------------------------------------------
501 */
502#define CFG_RCCR 0
503
504/*
505 * Init Memory Controller:
506 *
507 * Bank Bus Machine PortSz Device
508 * ---- --- ------- ------ ------
509 * 0 60x GPCM 32 bit FLASH
510 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
511 * 2 60x SDRAM 64 bit SDRAM
512 * 3 Local UPMC 8 bit Main Xilinx configuration
513 * 4 Local GPCM 32 bit Main Xilinx register mode
514 * 5 Local UPMB 32 bit Main Xilinx port mode
515 * 6 Local UPMC 8 bit Mezz Xilinx configuration
516 */
517
518/*
519 * Bank 0 - FLASH
520 *
521 * Quotes from the HYMOD IO Board Reference manual:
522 *
523 * "The flash memory is two Intel StrataFlash chips, each configured for
524 * 16 bit operation and connected to give a 32 bit wide port."
525 *
526 * "The chip select logic is configured to respond to both *CS0 and *CS1.
527 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
528 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
529 * FLASH will then appear as ROM during boot."
530 *
531 * Initially, we are only going to use bank 0 in read/write mode.
532 */
533
534/* 32 bit, read-write, GPCM on 60x bus */
535#define CFG_BR0_PRELIM ((CFG_FLASH_BASE&BRx_BA_MSK)|\
536 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
537/* up to 32 Mb */
538#define CFG_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
539
540/*
541 * Bank 2 - SDRAM
542 *
543 * Quotes from the HYMOD IO Board Reference manual:
544 *
545 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
546 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
547 * dynamic random access memory organised as 4 banks by 4096 rows by 512
548 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
549 *
550 * "The locations in SDRAM are accessed using multiplexed address pins to
551 * specify row and column. The pins also act to specify commands. The state
552 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
553 * pin may function as a row address or as the AUTO PRECHARGE control line,
554 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
555 * address lines to be configured to the required multiplexing scheme."
556 */
557
558#define CFG_SDRAM_SIZE 64
559
560/* 64 bit, read-write, SDRAM on 60x bus */
561#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
562 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
563/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
564#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM_SIZE)|\
565 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
566
567/*
568 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
569 *
570 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
571 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
572 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
573 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
574 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
575 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
576 * command is 2 clocks, earliest timing for PRECHARGE after last data
577 * was read is 1 clock, earliest timing for PRECHARGE after last data
578 * was written is 1 clock, CAS Latency is 2.
579 */
580
581#define CFG_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
582 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
583 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
584 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
585 PSDMR_WRC_1C|PSDMR_CL_2)
586
587/*
588 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
589 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
590 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
591 * Prescaler, hence the P instead of the R). The refresh timer period is given
592 * by (note that there was a change in the 8260 UM Errata):
593 *
594 * TimerPeriod = (PSRT + 1) / Fmptc
595 *
596 * where Fmptc is the BusClock divided by PTP. i.e.
597 *
598 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
599 *
600 * or
601 *
602 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
603 *
604 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
605 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
606 * = 15.625 usecs.
607 *
608 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
609 * appear to be reasonable.
610 */
611
612#ifdef DEBUG
613#define CFG_PSRT 39
614#define CFG_MPTPR MPTPR_PTP_DIV8
615#else
616#define CFG_PSRT 31
617#define CFG_MPTPR MPTPR_PTP_DIV32
618#endif
619
620/*
621 * Banks 3,4,5 and 6 - FPGA access
622 *
623 * Quotes from the HYMOD IO Board Reference manual:
624 *
625 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
626 * for configuring an optional FPGA on the mezzanine interface.
627 *
628 * Access to the FPGAs may be divided into several catagories:
629 *
630 * 1. Configuration
631 * 2. Register mode access
632 * 3. Port mode access
633 *
634 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
635 * configured only (mode 1). Consequently there are four access types.
636 *
637 * To improve interface performance and simplify software design, the four
638 * possible access types are separately mapped to different memory banks.
639 *
640 * All are accessed using the local bus."
641 *
642 * Device Mode Memory Bank Machine Port Size Access
643 *
644 * Main Configuration 3 UPMC 8bit R/W
645 * Main Register 4 GPCM 32bit R/W
646 * Main Port 5 UPMB 32bit R/W
647 * Mezzanine Configuration 6 UPMC 8bit W/O
648 *
649 * "Note that mezzanine mode 1 access is write-only."
650 */
651
652/* all the bank sizes must be a power of two, greater or equal to 32768 */
653#define FPGA_MAIN_CFG_BASE (CFG_FPGA_BASE)
654#define FPGA_MAIN_CFG_SIZE 32768
655#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
656#define FPGA_MAIN_REG_SIZE 32768
657#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
658#define FPGA_MAIN_PORT_SIZE 32768
659#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
660#define FPGA_MEZZ_CFG_SIZE 32768
661
662/* 8 bit, read-write, UPMC */
663#define CFG_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
664/* up to 32Kbyte, burst inhibit */
665#define CFG_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
666
667/* 32 bit, read-write, GPCM */
668#define CFG_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
669/* up to 32Kbyte */
670#define CFG_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
671
672/* 32 bit, read-write, UPMB */
673#define CFG_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
674/* up to 32Kbyte */
675#define CFG_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
676
677/* 8 bit, write-only, UPMC */
678#define CFG_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
679/* up to 32Kbyte, burst inhibit */
680#define CFG_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
681
682/*-----------------------------------------------------------------------
683 * MBMR - Machine B Mode 10-27
684 *-----------------------------------------------------------------------
685 */
686#define CFG_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
687
688/*-----------------------------------------------------------------------
689 * MCMR - Machine C Mode 10-27
690 *-----------------------------------------------------------------------
691 */
692#define CFG_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
693
694/*
695 * FPGA I/O Port/Bit information
696 */
697
698#define FPGA_MAIN_PROG_PORT IOPIN_PORTA
699#define FPGA_MAIN_PROG_PIN 4 /* PA4 */
700#define FPGA_MAIN_INIT_PORT IOPIN_PORTA
701#define FPGA_MAIN_INIT_PIN 5 /* PA5 */
702#define FPGA_MAIN_DONE_PORT IOPIN_PORTA
703#define FPGA_MAIN_DONE_PIN 6 /* PA6 */
704
705#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
706#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
707#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
708#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
709#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
710#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
711#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
712#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
713
714/*
wdenk6dd652f2003-06-19 23:40:20 +0000715 * FPGA Interrupt configuration
716 */
717#define FPGA_MAIN_IRQ SIU_INT_IRQ2
718
719/*
wdenk8966f332002-10-31 23:30:59 +0000720 * Internal Definitions
721 *
722 * Boot Flags
723 */
724#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
725#define BOOTFLAG_WARM 0x02 /* Software reboot */
726
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200727/*
728 * JFFS2 partitions
729 *
730 */
731/* No command line, one static partition, whole device */
732#undef CONFIG_JFFS2_CMDLINE
733#define CONFIG_JFFS2_DEV "nor0"
734#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
735#define CONFIG_JFFS2_PART_OFFSET 0x00000000
736
737/* mtdparts command line support */
738/*
739#define CONFIG_JFFS2_CMDLINE
740#define MTDIDS_DEFAULT ""
741#define MTDPARTS_DEFAULT ""
742*/
743
wdenk8966f332002-10-31 23:30:59 +0000744#endif /* __CONFIG_H */