blob: 90d1065deb23eb591703226952436d9e09e7824d [file] [log] [blame]
Kumar Galaa09b9b62010-12-30 12:09:53 -06001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#include <common.h>
21#include <config.h>
22#include <asm/fsl_law.h>
23#include <asm/fsl_serdes.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000024#include <asm/fsl_srio.h>
Liu Gangd59c5572012-09-28 21:26:19 +000025#include <asm/errno.h>
Liu Gang5ffa88e2012-03-08 00:33:17 +000026
Liu Gangc8b28152013-05-07 16:30:46 +080027#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gang5ffa88e2012-03-08 00:33:17 +000028#define SRIO_PORT_ACCEPT_ALL 0x10000001
29#define SRIO_IB_ATMU_AR 0x80f55000
Liu Gang5056c8e2012-03-08 00:33:21 +000030#define SRIO_OB_ATMU_AR_MAINT 0x80077000
31#define SRIO_OB_ATMU_AR_RW 0x80045000
32#define SRIO_LCSBA1CSR_OFFSET 0x5c
33#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
34#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
35#define SRIO_LCSBA1CSR 0x60000000
Liu Gang19e4a002012-10-14 20:55:17 +000036#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -060037
38#if defined(CONFIG_FSL_CORENET)
York Sun9e758752012-10-08 07:44:19 +000039#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
40 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
41 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
42#else
Kumar Galaa09b9b62010-12-30 12:09:53 -060043 #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
44 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
York Sun9e758752012-10-08 07:44:19 +000045#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -060046 #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
47 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
48#elif defined(CONFIG_MPC85xx)
49 #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO
50 #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO
51 #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG
52 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
53#elif defined(CONFIG_MPC86xx)
54 #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO
55 #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO
56 #define _DEVDISR_RMU MPC86xx_DEVDISR_RMSG
57 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
58 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
59#else
60#error "No defines for DEVDISR_SRIO"
61#endif
62
Liu Gangd59c5572012-09-28 21:26:19 +000063#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
64/*
65 * Erratum A-004034
66 * Affects: SRIO
67 * Description: During port initialization, the SRIO port performs
68 * lane synchronization (detecting valid symbols on a lane) and
69 * lane alignment (coordinating multiple lanes to receive valid data
70 * across lanes). Internal errors in lane synchronization and lane
71 * alignment may cause failure to achieve link initialization at
72 * the configured port width.
73 * An SRIO port configured as a 4x port may see one of these scenarios:
74 * 1. One or more lanes fails to achieve lane synchronization. Depending
75 * on which lanes fail, this may result in downtraining from 4x to 1x
76 * on lane 0, 4x to 1x on lane R (redundant lane).
77 * 2. The link may fail to achieve lane alignment as a 4x, even though
78 * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
79 * An SRIO port configured as a 1x port may fail to complete port
80 * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
81 * Impact: SRIO port may downtrain to 1x, or may fail to complete
82 * link initialization. Once a port completes link initialization
83 * successfully, it will operate normally.
84 */
85static int srio_erratum_a004034(u8 port)
86{
87 serdes_corenet_t *srds_regs;
88 u32 conf_lane;
89 u32 init_lane;
90 int idx, first, last;
91 u32 i;
92 unsigned long long end_tick;
93 struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
94
95 srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
96 conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
97 >> (12 - port * 4)) & 0x3;
98 init_lane = (in_be32((void *)&srio_regs->lp_serial
99 .port[port].pccsr) >> 27) & 0x7;
100
101 /*
102 * Start a counter set to ~2 ms after the SERDES reset is
103 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
104 * corresponding to the SERDES bank/PLL for the SRIO port).
105 */
106 if (in_be32((void *)&srds_regs->bank[0].rstctl)
107 & SRDS_RSTCTL_RSTDONE) {
108 /*
109 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
110 * PO=1 or the counter expires. If the counter expires, the
111 * port has failed initialization: go to recover steps. If PO=1
112 * and the desired port width is 1x, go to normal steps. If
113 * PO = 1 and the desired port width is 4x, go to recover steps.
114 */
115 end_tick = usec2ticks(2000) + get_ticks();
116 do {
117 if (in_be32((void *)&srio_regs->lp_serial
118 .port[port].pescsr) & 0x2) {
119 if (conf_lane == 0x1)
120 goto host_ok;
121 else {
122 if (init_lane == 0x2)
123 goto host_ok;
124 else
125 break;
126 }
127 }
128 } while (end_tick > get_ticks());
129
130 /* recover at most 3 times */
131 for (i = 0; i < 3; i++) {
132 /* Set SRIO PnCCSR[PD]=1 */
133 setbits_be32((void *)&srio_regs->lp_serial
134 .port[port].pccsr,
135 0x800000);
136 /*
137 * Set SRIO PnPCR[OBDEN] on the host to
138 * enable the discarding of any pending packets.
139 */
140 setbits_be32((void *)&srio_regs->impl.port[port].pcr,
141 0x04);
142 /* Wait 50 us */
143 udelay(50);
144 /* Run sync command */
145 isync();
146
147 if (port)
148 first = serdes_get_first_lane(SRIO2);
149 else
150 first = serdes_get_first_lane(SRIO1);
151 if (unlikely(first < 0))
152 return -ENODEV;
153 if (conf_lane == 0x1)
154 last = first;
155 else
156 last = first + 3;
157 /*
158 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
159 * bank n and lane m.
160 */
161 for (idx = first; idx <= last; idx++)
162 clrbits_be32(&srds_regs->lane[idx].gcr0,
163 SRDS_GCR0_RRST);
164 /*
165 * Read SERDES BnGCRm0 for each SRIO
166 * bank n and lane m
167 */
168 for (idx = first; idx <= last; idx++)
169 in_be32(&srds_regs->lane[idx].gcr0);
170 /* Run sync command */
171 isync();
172 /* Wait >= 100 ns */
173 udelay(1);
174 /*
175 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
176 * bank n and lane m.
177 */
178 for (idx = first; idx <= last; idx++)
179 setbits_be32(&srds_regs->lane[idx].gcr0,
180 SRDS_GCR0_RRST);
181 /*
182 * Read SERDES BnGCRm0 for each SRIO
183 * bank n and lane m
184 */
185 for (idx = first; idx <= last; idx++)
186 in_be32(&srds_regs->lane[idx].gcr0);
187 /* Run sync command */
188 isync();
189 /* Wait >= 300 ns */
190 udelay(1);
191
192 /* Write 1 to clear all bits in SRIO PnSLCSR */
193 out_be32((void *)&srio_regs->impl.port[port].slcsr,
194 0xffffffff);
195 /* Clear SRIO PnPCR[OBDEN] on the host */
196 clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
197 0x04);
198 /* Set SRIO PnCCSR[PD]=0 */
199 clrbits_be32((void *)&srio_regs->lp_serial
200 .port[port].pccsr,
201 0x800000);
202 /* Wait >= 24 ms */
203 udelay(24000);
204 /* Poll the state of the port again */
205 init_lane =
206 (in_be32((void *)&srio_regs->lp_serial
207 .port[port].pccsr) >> 27) & 0x7;
208 if (in_be32((void *)&srio_regs->lp_serial
209 .port[port].pescsr) & 0x2) {
210 if (conf_lane == 0x1)
211 goto host_ok;
212 else {
213 if (init_lane == 0x2)
214 goto host_ok;
215 }
216 }
217 if (i == 2)
218 return -ENODEV;
219 }
220 } else
221 return -ENODEV;
222
223host_ok:
224 /* Poll PnESCSR[OES] on the host until it is clear */
225 end_tick = usec2ticks(1000000) + get_ticks();
226 do {
227 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
228 & 0x10000)) {
229 out_be32(((void *)&srio_regs->lp_serial
230 .port[port].pescsr), 0xffffffff);
231 out_be32(((void *)&srio_regs->phys_err
232 .port[port].edcsr), 0);
233 out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
234 return 0;
235 }
236 } while (end_tick > get_ticks());
237
238 return -ENODEV;
239}
240#endif
241
Kumar Galaa09b9b62010-12-30 12:09:53 -0600242void srio_init(void)
243{
244 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
245 int srio1_used = 0, srio2_used = 0;
York Sun9e758752012-10-08 07:44:19 +0000246 u32 *devdisr;
Kumar Galaa09b9b62010-12-30 12:09:53 -0600247
York Sun9e758752012-10-08 07:44:19 +0000248#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
249 devdisr = &gur->devdisr3;
250#else
251 devdisr = &gur->devdisr;
252#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600253 if (is_serdes_configured(SRIO1)) {
254 set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
255 law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
256 LAW_TRGT_IF_RIO_1);
257 srio1_used = 1;
Liu Gangd59c5572012-09-28 21:26:19 +0000258#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
259 if (srio_erratum_a004034(0) < 0)
260 printf("SRIO1: enabled but port error\n");
261 else
262#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600263 printf("SRIO1: enabled\n");
264 } else {
265 printf("SRIO1: disabled\n");
266 }
267
268#ifdef CONFIG_SRIO2
269 if (is_serdes_configured(SRIO2)) {
270 set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
271 law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
272 LAW_TRGT_IF_RIO_2);
273 srio2_used = 1;
Liu Gangd59c5572012-09-28 21:26:19 +0000274#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
275 if (srio_erratum_a004034(1) < 0)
276 printf("SRIO2: enabled but port error\n");
277 else
278#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600279 printf("SRIO2: enabled\n");
Liu Gangd59c5572012-09-28 21:26:19 +0000280
Kumar Galaa09b9b62010-12-30 12:09:53 -0600281 } else {
282 printf("SRIO2: disabled\n");
283 }
284#endif
285
286#ifdef CONFIG_FSL_CORENET
287 /* On FSL_CORENET devices we can disable individual ports */
288 if (!srio1_used)
York Sun9e758752012-10-08 07:44:19 +0000289 setbits_be32(devdisr, _DEVDISR_SRIO1);
Kumar Galaa09b9b62010-12-30 12:09:53 -0600290 if (!srio2_used)
York Sun9e758752012-10-08 07:44:19 +0000291 setbits_be32(devdisr, _DEVDISR_SRIO2);
Kumar Galaa09b9b62010-12-30 12:09:53 -0600292#endif
293
294 /* neither port is used - disable everything */
295 if (!srio1_used && !srio2_used) {
York Sun9e758752012-10-08 07:44:19 +0000296 setbits_be32(devdisr, _DEVDISR_SRIO1);
297 setbits_be32(devdisr, _DEVDISR_SRIO2);
298 setbits_be32(devdisr, _DEVDISR_RMU);
Kumar Galaa09b9b62010-12-30 12:09:53 -0600299 }
300}
Liu Gang5ffa88e2012-03-08 00:33:17 +0000301
Liu Gangc8b28152013-05-07 16:30:46 +0800302#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
Liu Gangff65f122012-08-09 05:09:59 +0000303void srio_boot_master(int port)
Liu Gang5ffa88e2012-03-08 00:33:17 +0000304{
305 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
306
307 /* set port accept-all */
Liu Gangff65f122012-08-09 05:09:59 +0000308 out_be32((void *)&srio->impl.port[port - 1].ptaacr,
Liu Gang5ffa88e2012-03-08 00:33:17 +0000309 SRIO_PORT_ACCEPT_ALL);
310
Liu Gangff65f122012-08-09 05:09:59 +0000311 debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", port);
Liu Gang3f1af812012-03-08 00:33:19 +0000312 /* configure inbound window for slave's u-boot image */
313 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
Liu Gang5ffa88e2012-03-08 00:33:17 +0000314 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
Liu Gangb5f7c872012-08-09 05:10:02 +0000315 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
316 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
317 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
Liu Gangff65f122012-08-09 05:09:59 +0000318 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000319 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000320 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000321 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000322 out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
Liu Gang5ffa88e2012-03-08 00:33:17 +0000323 SRIO_IB_ATMU_AR
Liu Gangb5f7c872012-08-09 05:10:02 +0000324 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
Liu Gang5ffa88e2012-03-08 00:33:17 +0000325
Liu Gang3f1af812012-03-08 00:33:19 +0000326 /* configure inbound window for slave's u-boot image */
327 debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
Liu Gang5ffa88e2012-03-08 00:33:17 +0000328 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
Liu Gangb5f7c872012-08-09 05:10:02 +0000329 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
330 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
331 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
Liu Gangff65f122012-08-09 05:09:59 +0000332 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000333 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000334 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000335 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000336 out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
Liu Gang5ffa88e2012-03-08 00:33:17 +0000337 SRIO_IB_ATMU_AR
Liu Gangb5f7c872012-08-09 05:10:02 +0000338 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
Liu Gang3f1af812012-03-08 00:33:19 +0000339
Liu Gangff65f122012-08-09 05:09:59 +0000340 /* configure inbound window for slave's ucode and ENV */
341 debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
Liu Gang3f1af812012-03-08 00:33:19 +0000342 "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
Liu Gangb5f7c872012-08-09 05:10:02 +0000343 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
344 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
345 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
Liu Gangff65f122012-08-09 05:09:59 +0000346 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000347 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000348 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
Liu Gangb5f7c872012-08-09 05:10:02 +0000349 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000350 out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
Liu Gang3f1af812012-03-08 00:33:19 +0000351 SRIO_IB_ATMU_AR
Liu Gangb5f7c872012-08-09 05:10:02 +0000352 | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
Liu Gang5ffa88e2012-03-08 00:33:17 +0000353}
Liu Gang5056c8e2012-03-08 00:33:21 +0000354
Liu Gangff65f122012-08-09 05:09:59 +0000355void srio_boot_master_release_slave(int port)
Liu Gang5056c8e2012-03-08 00:33:21 +0000356{
357 struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
358 u32 escsr;
359 debug("SRIOBOOT - MASTER: "
360 "Check the port status and release slave core ...\n");
361
Liu Gangff65f122012-08-09 05:09:59 +0000362 escsr = in_be32((void *)&srio->lp_serial.port[port - 1].pescsr);
Liu Gang5056c8e2012-03-08 00:33:21 +0000363 if (escsr & 0x2) {
364 if (escsr & 0x10100) {
365 debug("SRIOBOOT - MASTER: Port [ %d ] is error.\n",
Liu Gangff65f122012-08-09 05:09:59 +0000366 port);
Liu Gang5056c8e2012-03-08 00:33:21 +0000367 } else {
368 debug("SRIOBOOT - MASTER: "
Liu Gangff65f122012-08-09 05:09:59 +0000369 "Port [ %d ] is ready, now release slave's core ...\n",
370 port);
Liu Gang5056c8e2012-03-08 00:33:21 +0000371 /*
372 * configure outbound window
373 * with maintenance attribute to set slave's LCSBA1CSR
374 */
Liu Gangff65f122012-08-09 05:09:59 +0000375 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000376 .outbw[1].rowtar, 0);
Liu Gangff65f122012-08-09 05:09:59 +0000377 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000378 .outbw[1].rowtear, 0);
Liu Gangff65f122012-08-09 05:09:59 +0000379 if (port - 1)
380 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000381 .outbw[1].rowbar,
382 CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
383 else
Liu Gangff65f122012-08-09 05:09:59 +0000384 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000385 .outbw[1].rowbar,
386 CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000387 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000388 .outbw[1].rowar,
389 SRIO_OB_ATMU_AR_MAINT
390 | atmu_size_mask(SRIO_MAINT_WIN_SIZE));
391
392 /*
393 * configure outbound window
394 * with R/W attribute to set slave's BRR
395 */
Liu Gangff65f122012-08-09 05:09:59 +0000396 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000397 .outbw[2].rowtar,
398 SRIO_LCSBA1CSR >> 9);
Liu Gangff65f122012-08-09 05:09:59 +0000399 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000400 .outbw[2].rowtear, 0);
Liu Gangff65f122012-08-09 05:09:59 +0000401 if (port - 1)
402 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000403 .outbw[2].rowbar,
404 (CONFIG_SYS_SRIO2_MEM_PHYS
405 + SRIO_MAINT_WIN_SIZE) >> 12);
406 else
Liu Gangff65f122012-08-09 05:09:59 +0000407 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000408 .outbw[2].rowbar,
409 (CONFIG_SYS_SRIO1_MEM_PHYS
410 + SRIO_MAINT_WIN_SIZE) >> 12);
Liu Gangff65f122012-08-09 05:09:59 +0000411 out_be32((void *)&srio->atmu.port[port - 1]
Liu Gang5056c8e2012-03-08 00:33:21 +0000412 .outbw[2].rowar,
413 SRIO_OB_ATMU_AR_RW
414 | atmu_size_mask(SRIO_RW_WIN_SIZE));
415
416 /*
417 * Set the LCSBA1CSR register in slave
418 * by the maint-outbound window
419 */
Liu Gangff65f122012-08-09 05:09:59 +0000420 if (port - 1) {
Liu Gang5056c8e2012-03-08 00:33:21 +0000421 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
422 + SRIO_LCSBA1CSR_OFFSET,
423 SRIO_LCSBA1CSR);
424 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
425 + SRIO_LCSBA1CSR_OFFSET)
426 != SRIO_LCSBA1CSR)
427 ;
428 /*
429 * And then set the BRR register
430 * to release slave core
431 */
432 out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
433 + SRIO_MAINT_WIN_SIZE
Liu Gangb5f7c872012-08-09 05:10:02 +0000434 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
435 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
Liu Gang5056c8e2012-03-08 00:33:21 +0000436 } else {
437 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
438 + SRIO_LCSBA1CSR_OFFSET,
439 SRIO_LCSBA1CSR);
440 while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
441 + SRIO_LCSBA1CSR_OFFSET)
442 != SRIO_LCSBA1CSR)
443 ;
444 /*
445 * And then set the BRR register
446 * to release slave core
447 */
448 out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
449 + SRIO_MAINT_WIN_SIZE
Liu Gangb5f7c872012-08-09 05:10:02 +0000450 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
451 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
Liu Gang5056c8e2012-03-08 00:33:21 +0000452 }
453 debug("SRIOBOOT - MASTER: "
454 "Release slave successfully! Now the slave should start up!\n");
455 }
456 } else
Liu Gangff65f122012-08-09 05:09:59 +0000457 debug("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", port);
Liu Gang5056c8e2012-03-08 00:33:21 +0000458}
459#endif