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Larry Johnson87dc0962007-12-22 15:16:25 -05001/*
Larry Johnsona87fb1b2009-01-28 15:30:37 -05002 * (C) Copyright 2007-2009
Larry Johnson87dc0962007-12-22 15:16:25 -05003 * Larry Johnson, lrj@acm.org
4 *
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Larry Johnson214398d2008-01-18 21:49:05 -050028/*
Larry Johnson87dc0962007-12-22 15:16:25 -050029 * korat.h - configuration for Korat board
Larry Johnson214398d2008-01-18 21:49:05 -050030 */
Larry Johnson87dc0962007-12-22 15:16:25 -050031#ifndef __CONFIG_H
32#define __CONFIG_H
33
Larry Johnson214398d2008-01-18 21:49:05 -050034/*
Larry Johnson87dc0962007-12-22 15:16:25 -050035 * High Level Configuration Options
Larry Johnson214398d2008-01-18 21:49:05 -050036 */
37#define CONFIG_440EPX 1 /* Specific PPC440EPx */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
Larry Johnson87dc0962007-12-22 15:16:25 -050039#define CONFIG_SYS_CLK_FREQ 33333333
40
Larry Johnson214398d2008-01-18 21:49:05 -050041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Larry Johnson87dc0962007-12-22 15:16:25 -050043
Larry Johnson214398d2008-01-18 21:49:05 -050044/*
Larry Johnson87dc0962007-12-22 15:16:25 -050045 * Manufacturer's information serial EEPROM parameters
Larry Johnson214398d2008-01-18 21:49:05 -050046 */
47#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
Larry Johnson6433fa22008-03-17 11:10:35 -050048#define MAN_INFO_FIELD 2
49#define MAN_INFO_LENGTH 9
Larry Johnson87dc0962007-12-22 15:16:25 -050050#define MAN_MAC_ADDR_FIELD 3
Larry Johnson6433fa22008-03-17 11:10:35 -050051#define MAN_MAC_ADDR_LENGTH 12
Larry Johnson87dc0962007-12-22 15:16:25 -050052
Larry Johnson214398d2008-01-18 21:49:05 -050053/*
54 * Base addresses -- Note these are effective addresses where the actual
55 * resources get mapped (not physical addresses).
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
58#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
Larry Johnson87dc0962007-12-22 15:16:25 -050059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
61#define CONFIG_SYS_FLASH0_SIZE 0x01000000
62#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
63#define CONFIG_SYS_FLASH1_TOP 0xF8000000
64#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
65#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
66#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
67#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
68#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
69#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
70#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
71#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Larry Johnson87dc0962007-12-22 15:16:25 -050072
73/* Don't change either of these */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
Larry Johnson87dc0962007-12-22 15:16:25 -050075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_USB2D0_BASE 0xe0000100
77#define CONFIG_SYS_USB_DEVICE 0xe0000000
78#define CONFIG_SYS_USB_HOST 0xe0000400
79#define CONFIG_SYS_CPLD_BASE 0xc0000000
Larry Johnson87dc0962007-12-22 15:16:25 -050080
Larry Johnson214398d2008-01-18 21:49:05 -050081/*
Larry Johnson87dc0962007-12-22 15:16:25 -050082 * Initial RAM & stack pointer
Larry Johnson214398d2008-01-18 21:49:05 -050083 */
Larry Johnson87dc0962007-12-22 15:16:25 -050084/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_INIT_RAM_DCACHE
86#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
87#define CONFIG_SYS_INIT_RAM_END (4 << 10)
88#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
89#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
90#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
Larry Johnson87dc0962007-12-22 15:16:25 -050091
Larry Johnson214398d2008-01-18 21:49:05 -050092/*
Larry Johnson87dc0962007-12-22 15:16:25 -050093 * Serial Port
Larry Johnson214398d2008-01-18 21:49:05 -050094 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
Larry Johnson87dc0962007-12-22 15:16:25 -050096#define CONFIG_BAUDRATE 115200
97#define CONFIG_SERIAL_MULTI 1
98/* define this if you want console on UART1 */
99#undef CONFIG_UART1_CONSOLE
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_BAUDRATE_TABLE \
Larry Johnson87dc0962007-12-22 15:16:25 -0500102 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
103
Larry Johnson214398d2008-01-18 21:49:05 -0500104/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500105 * Environment
Larry Johnson214398d2008-01-18 21:49:05 -0500106 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200107#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
Larry Johnson87dc0962007-12-22 15:16:25 -0500108
Larry Johnson214398d2008-01-18 21:49:05 -0500109/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500110 * FLASH related
Larry Johnson214398d2008-01-18 21:49:05 -0500111 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200113#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Larry Johnson6433fa22008-03-17 11:10:35 -0500114#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
Larry Johnson87dc0962007-12-22 15:16:25 -0500117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
119#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
Larry Johnson87dc0962007-12-22 15:16:25 -0500120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
122#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Larry Johnson87dc0962007-12-22 15:16:25 -0500123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
125#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Larry Johnson87dc0962007-12-22 15:16:25 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
128#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Larry Johnson87dc0962007-12-22 15:16:25 -0500129
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200130#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200132#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Larry Johnson87dc0962007-12-22 15:16:25 -0500133
Larry Johnson6433fa22008-03-17 11:10:35 -0500134/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200135#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
136#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Larry Johnson87dc0962007-12-22 15:16:25 -0500137
Larry Johnson214398d2008-01-18 21:49:05 -0500138/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500139 * DDR SDRAM
Larry Johnson214398d2008-01-18 21:49:05 -0500140 */
Larry Johnson214398d2008-01-18 21:49:05 -0500141#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
142#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
143#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
144#define CONFIG_DDR_ECC /* Use ECC when available */
Larry Johnson87dc0962007-12-22 15:16:25 -0500145#define SPD_EEPROM_ADDRESS {0x50}
146#define CONFIG_PROG_SDRAM_TLB
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500147#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
148 /* per 440EPx Errata CHIP_11 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500149
Larry Johnson214398d2008-01-18 21:49:05 -0500150/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500151 * I2C
Larry Johnson214398d2008-01-18 21:49:05 -0500152 */
153#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
154#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
156#define CONFIG_SYS_I2C_SLAVE 0x7F
Larry Johnson87dc0962007-12-22 15:16:25 -0500157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_I2C_MULTI_EEPROMS
159#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
161#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
162#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Larry Johnson87dc0962007-12-22 15:16:25 -0500163
164/* I2C RTC */
165#define CONFIG_RTC_M41T60 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Larry Johnson87dc0962007-12-22 15:16:25 -0500167
168/* I2C SYSMON (LM73) */
Larry Johnson214398d2008-01-18 21:49:05 -0500169#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
170#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_DTT_MAX_TEMP 70
172#define CONFIG_SYS_DTT_MIN_TEMP -30
Larry Johnson87dc0962007-12-22 15:16:25 -0500173
174#define CONFIG_PREBOOT "echo;" \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500175 "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500176 "echo"
177
178#undef CONFIG_BOOTARGS
179
180/* Setup some board specific values for the default environment variables */
181#define CONFIG_HOSTNAME korat
Larry Johnson87dc0962007-12-22 15:16:25 -0500182
Larry Johnson6433fa22008-03-17 11:10:35 -0500183/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
Larry Johnson47ce4a22008-06-14 16:53:02 -0400184#define CONFIG_EXTRA_ENV_SETTINGS \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500185 "u_boot=korat/u-boot.bin\0" \
186 "load=tftp 200000 ${u_boot}\0" \
187 "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
188 "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
189 "F7F60000 F7FBFFFF\0" \
190 "upd=run load update\0" \
191 "bootfile=korat/uImage\0" \
192 "dtb=korat/korat.dtb\0" \
193 "kernel_addr=F4000000\0" \
194 "ramdisk_addr=F4400000\0" \
195 "dtb_addr=F41E0000\0" \
196 "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
197 "cp.b ${fileaddr} F4000000 ${filesize}\0" \
198 "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
199 "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
200 "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
201 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
202 "${dtb}\0" \
203 "rd_size=73728\0" \
204 "ramargs=setenv bootargs root=/dev/ram rw " \
205 "ramdisk_size=${rd_size}\0" \
206 "usbdev=sda1\0" \
207 "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
208 "rootpath=/opt/eldk/ppc_4xxFP\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500209 "netdev=eth0\0" \
210 "nfsargs=setenv bootargs root=/dev/nfs rw " \
211 "nfsroot=${serverip}:${rootpath}\0" \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500212 "pciclk=33\0" \
213 "addide=setenv bootargs ${bootargs} ide=reverse " \
214 "idebus=${pciclk}\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500215 "addip=setenv bootargs ${bootargs} " \
216 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
217 ":${hostname}:${netdev}:off panic=1\0" \
218 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500219 "flash_cf=run usbargs addide addip addtty; " \
220 "bootm ${kernel_addr} - ${dtb_addr}\0" \
221 "flash_nfs=run nfsargs addide addip addtty; " \
222 "bootm ${kernel_addr} - ${dtb_addr}\0" \
223 "flash_self=run ramargs addip addtty; " \
224 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
Larry Johnson87dc0962007-12-22 15:16:25 -0500225 ""
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500226
227#define CONFIG_BOOTCOMMAND "run flash_cf"
Larry Johnson87dc0962007-12-22 15:16:25 -0500228
Larry Johnson214398d2008-01-18 21:49:05 -0500229#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Larry Johnson87dc0962007-12-22 15:16:25 -0500230
Larry Johnson214398d2008-01-18 21:49:05 -0500231#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Larry Johnson87dc0962007-12-22 15:16:25 -0500233
Ben Warren96e21f82008-10-27 23:50:15 -0700234#define CONFIG_PPC4xx_EMAC
Larry Johnson47ce4a22008-06-14 16:53:02 -0400235#define CONFIG_IBM_EMAC4_V4 1
Larry Johnson214398d2008-01-18 21:49:05 -0500236#define CONFIG_MII 1 /* MII PHY management */
237#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
Larry Johnson87dc0962007-12-22 15:16:25 -0500238#define CONFIG_PHY_DYNAMIC_ANEG 1
239
Larry Johnson6433fa22008-03-17 11:10:35 -0500240#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
Larry Johnson87dc0962007-12-22 15:16:25 -0500241#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
242
243#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
Larry Johnson214398d2008-01-18 21:49:05 -0500245 /* buffers & descriptors */
Larry Johnson87dc0962007-12-22 15:16:25 -0500246#define CONFIG_NET_MULTI 1
Larry Johnson214398d2008-01-18 21:49:05 -0500247#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Larry Johnson87dc0962007-12-22 15:16:25 -0500248#define CONFIG_PHY1_ADDR 3
249
250/* USB */
251#define CONFIG_USB_OHCI
252#define CONFIG_USB_STORAGE
253
254/* Comment this out to enable USB 1.1 device */
255#define USB_2_0_DEVICE
256
257/* Partitions */
258#define CONFIG_MAC_PARTITION
259#define CONFIG_DOS_PARTITION
260#define CONFIG_ISO_PARTITION
261
262/*
263 * BOOTP options
264 */
265#define CONFIG_BOOTP_BOOTFILESIZE
266#define CONFIG_BOOTP_BOOTPATH
267#define CONFIG_BOOTP_GATEWAY
268#define CONFIG_BOOTP_HOSTNAME
269#define CONFIG_BOOTP_SUBNETMASK
270
271/*
272 * Command line configuration.
273 */
274#include <config_cmd_default.h>
275
276#define CONFIG_CMD_ASKENV
277#define CONFIG_CMD_DATE
278#define CONFIG_CMD_DHCP
279#define CONFIG_CMD_DTT
280#define CONFIG_CMD_DIAG
281#define CONFIG_CMD_EEPROM
282#define CONFIG_CMD_ELF
283#define CONFIG_CMD_FAT
284#define CONFIG_CMD_I2C
285#define CONFIG_I2C_CMD_TREE
286#define CONFIG_CMD_IRQ
287#define CONFIG_CMD_MII
288#define CONFIG_CMD_NET
289#define CONFIG_CMD_NFS
290#define CONFIG_CMD_PCI
291#define CONFIG_CMD_PING
292#define CONFIG_CMD_REGINFO
293#define CONFIG_CMD_SDRAM
294#define CONFIG_CMD_USB
295
296/* POST support */
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500297#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
298 CONFIG_SYS_POST_CPU | \
299 CONFIG_SYS_POST_ECC | \
300 CONFIG_SYS_POST_ETHER | \
301 CONFIG_SYS_POST_FPU | \
302 CONFIG_SYS_POST_I2C | \
303 CONFIG_SYS_POST_MEMORY | \
304 CONFIG_SYS_POST_RTC | \
305 CONFIG_SYS_POST_SPR | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306 CONFIG_SYS_POST_UART)
Larry Johnson87dc0962007-12-22 15:16:25 -0500307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Larry Johnson87dc0962007-12-22 15:16:25 -0500309#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
Larry Johnson87dc0962007-12-22 15:16:25 -0500311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Larry Johnson87dc0962007-12-22 15:16:25 -0500313
314#define CONFIG_SUPPORT_VFAT
315
Larry Johnson214398d2008-01-18 21:49:05 -0500316/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500317 * Miscellaneous configurable options
Larry Johnson214398d2008-01-18 21:49:05 -0500318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_LONGHELP /* undef to save memory */
320#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Larry Johnson87dc0962007-12-22 15:16:25 -0500321#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500323#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500325#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200327 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
329#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Larry Johnson87dc0962007-12-22 15:16:25 -0500330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
332#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Larry Johnson87dc0962007-12-22 15:16:25 -0500333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
335#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Larry Johnson87dc0962007-12-22 15:16:25 -0500336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Larry Johnson87dc0962007-12-22 15:16:25 -0500338
Larry Johnson214398d2008-01-18 21:49:05 -0500339#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
340#define CONFIG_LOOPW 1 /* enable loopw command */
341#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
342#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
343#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
Larry Johnson87dc0962007-12-22 15:16:25 -0500344
Larry Johnson214398d2008-01-18 21:49:05 -0500345/*
Larry Johnson6433fa22008-03-17 11:10:35 -0500346 * Korat-specific options
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
Larry Johnson6433fa22008-03-17 11:10:35 -0500349
350/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500351 * PCI stuff
Larry Johnson214398d2008-01-18 21:49:05 -0500352 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500353/* General PCI */
Larry Johnson214398d2008-01-18 21:49:05 -0500354#define CONFIG_PCI /* include pci support */
355#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
Larry Johnson214398d2008-01-18 21:49:05 -0500357#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
359 /* CONFIG_SYS_PCI_MEMBASE */
Larry Johnson87dc0962007-12-22 15:16:25 -0500360/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_PCI_TARGET_INIT
362#define CONFIG_SYS_PCI_MASTER_INIT
Larry Johnson87dc0962007-12-22 15:16:25 -0500363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
365#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Larry Johnson87dc0962007-12-22 15:16:25 -0500366
367/*
Larry Johnson214398d2008-01-18 21:49:05 -0500368 * For booting Linux, the board info and command line data have to be in the
369 * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
370 * during initialization.
Larry Johnson87dc0962007-12-22 15:16:25 -0500371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Larry Johnson87dc0962007-12-22 15:16:25 -0500373
Larry Johnson214398d2008-01-18 21:49:05 -0500374/*
Larry Johnson87dc0962007-12-22 15:16:25 -0500375 * External Bus Controller (EBC) Setup
Larry Johnson214398d2008-01-18 21:49:05 -0500376 */
Larry Johnson87dc0962007-12-22 15:16:25 -0500377
378/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
380#define CONFIG_SYS_EBC_PB0AP 0x04017300
381#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
382#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
383#define CONFIG_SYS_EBC_PB0AP 0x04017300
384#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
Larry Johnson6433fa22008-03-17 11:10:35 -0500385#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
Larry Johnson6433fa22008-03-17 11:10:35 -0500387#endif
Larry Johnson87dc0962007-12-22 15:16:25 -0500388
389/* Memory Bank 1 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
391#define CONFIG_SYS_EBC_PB1AP 0x04017300
392#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
Larry Johnson6433fa22008-03-17 11:10:35 -0500393#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
Larry Johnson6433fa22008-03-17 11:10:35 -0500395#endif
Larry Johnson87dc0962007-12-22 15:16:25 -0500396
397/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_EBC_PB2AP 0x04017300
399#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
Larry Johnson87dc0962007-12-22 15:16:25 -0500400
Larry Johnson214398d2008-01-18 21:49:05 -0500401/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500402 * GPIO Setup
403 *
404 * Korat GPIO usage:
405 *
406 * Init.
407 * Pin Source I/O value Function
408 * ------ ------ --- ----- ---------------------------------
409 * GPIO00 Alt1 I/O x PerAddr07
410 * GPIO01 Alt1 I/O x PerAddr06
411 * GPIO02 Alt1 I/O x PerAddr05
412 * GPIO03 GPIO x x GPIO03 to expansion bus connector
413 * GPIO04 GPIO x x GPIO04 to expansion bus connector
414 * GPIO05 GPIO x x GPIO05 to expansion bus connector
415 * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
416 * GPIO07 Alt1 O x PerCS2 (CPLD)
417 * GPIO08 Alt1 O x PerCS3 to expansion bus connector
418 * GPIO09 Alt1 O x PerCS4 to expansion bus connector
419 * GPIO10 Alt1 O x PerCS5 to expansion bus connector
420 * GPIO11 Alt1 I x PerErr
421 * GPIO12 GPIO O 0 ATMega !Reset
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500422 * GPIO13 GPIO x x Test Point 2 (TP2)
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500423 * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
424 * GPIO15 GPIO O 0 CPU Run LED !On
425 * GPIO16 Alt1 O x GMC1TxD0
426 * GPIO17 Alt1 O x GMC1TxD1
427 * GPIO18 Alt1 O x GMC1TxD2
428 * GPIO19 Alt1 O x GMC1TxD3
429 * GPIO20 Alt1 I x RejectPkt0
430 * GPIO21 Alt1 I x RejectPkt1
431 * GPIO22 GPIO I x PGOOD_DDR
432 * GPIO23 Alt1 O x SCPD0
433 * GPIO24 Alt1 O x GMC0TxD2
434 * GPIO25 Alt1 O x GMC0TxD3
435 * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
436 * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
437 * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
438 * GPIO29 GPIO I x Test jumper !Present
439 * GPIO30 GPIO I x SFP module #0 !Present
440 * GPIO31 GPIO I x SFP module #1 !Present
441 *
442 * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
443 * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
444 * GPIO34 Alt2 I x !UART1_CTS
445 * GPIO35 Alt2 O x !UART1_RTS
446 * GPIO36 Alt1 I x !UART0_CTS
447 * GPIO37 Alt1 O x !UART0_RTS
448 * GPIO38 Alt2 O x UART1_Tx
449 * GPIO39 Alt2 I x UART1_Rx
450 * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
451 * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
452 * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
453 * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
454 * GPIO44 xxxx x x (grounded through pulldown)
455 * GPIO45 GPIO O 0 PHY #0 Enable
456 * GPIO46 GPIO O 0 PHY #1 Enable
457 * GPIO47 GPIO I x Reset switch !Pressed
458 * GPIO48 GPIO I x Shutdown switch !Pressed
459 * GPIO49 xxxx x x (reserved for trace port)
460 * . . . . .
461 * . . . . .
462 * . . . . .
463 * GPIO63 xxxx x x (reserved for trace port)
Larry Johnson214398d2008-01-18 21:49:05 -0500464 */
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
467#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
468#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
469#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
470#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
471#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
472#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
473#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
474#define CONFIG_SYS_GPIO_PHY0_EN 45
475#define CONFIG_SYS_GPIO_PHY1_EN 46
476#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500477
Larry Johnson214398d2008-01-18 21:49:05 -0500478/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500479 * PPC440 GPIO Configuration
480 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500482{ \
483/* GPIO Core 0 */ \
484{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
485{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
486{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
487{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
488{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
489{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
490{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
491{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
492{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
493{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
494{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
495{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
496{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
Larry Johnsona87fb1b2009-01-28 15:30:37 -0500497{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500498{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
499{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
500{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
501{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
502{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
503{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
504{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
505{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
506{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
507{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
508{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
509{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
510{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
511{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
512{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
513{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
514{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
515{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
516}, \
517{ \
518/* GPIO Core 1 */ \
519{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
520{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
521{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
522{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
523{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
524{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
525{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
526{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
527{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
528{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
529{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
530{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
531{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
532{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
533{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
534{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
536{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
537{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
549{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
550{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
551} \
552}
553
Larry Johnson87dc0962007-12-22 15:16:25 -0500554/*
555 * Internal Definitions
556 *
557 * Boot Flags
558 */
Larry Johnson214398d2008-01-18 21:49:05 -0500559#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
560#define BOOTFLAG_WARM 0x02 /* Software reboot */
Larry Johnson87dc0962007-12-22 15:16:25 -0500561
562#if defined(CONFIG_CMD_KGDB)
Larry Johnson214398d2008-01-18 21:49:05 -0500563#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
564#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
Larry Johnson87dc0962007-12-22 15:16:25 -0500565#endif
Larry Johnson214398d2008-01-18 21:49:05 -0500566
Larry Johnson47ce4a22008-06-14 16:53:02 -0400567/* Pass open firmware flat tree */
568#define CONFIG_OF_LIBFDT 1
569#define CONFIG_OF_BOARD_SETUP 1
570
Larry Johnson87dc0962007-12-22 15:16:25 -0500571#endif /* __CONFIG_H */