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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c9ffd839b1ada502c86f88edaf1534426b6688ce / . / cpu / mpc85xx / release.S
blob: ec5e4daf88f1b09838f4a425f4742fe7acb1024e [file] [log] [blame]
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]1#include <config.h>
2#include <mpc85xx.h>
3#include <version.h>
4
5#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
6
7#include <ppc_asm.tmpl>
8#include <ppc_defs.h>
9
10#include <asm/cache.h>
11#include <asm/mmu.h>
12
13/* To boot secondary cpus, we need a place for them to start up.
14 * Normally, they start at 0xfffffffc, but that's usually the
15 * firmware, and we don't want to have to run the firmware again.
16 * Instead, the primary cpu will set the BPTR to point here to
17 * this page. We then set up the core, and head to
18 * start_secondary. Note that this means that the code below
19 * must never exceed 1023 instructions (the branch at the end
20 * would then be the 1024th).
21 */
22 .globl __secondary_start_page
23 .align 12
24__secondary_start_page:
25/* First do some preliminary setup */
26 lis r3, HID0_EMCP@h /* enable machine check */
27 ori r3,r3,HID0_TBEN@l /* enable Timebase */
28#ifdef CONFIG_PHYS_64BIT
29 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
30#endif
31 mtspr SPRN_HID0,r3
32
33 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
34 mtspr SPRN_HID1,r3
35
36 /* Enable branch prediction */
37 li r3,0x201
38 mtspr SPRN_BUCSR,r3
39
Kumar Galae0ff3d32008-09-08 08:51:29 -0500[diff] [blame]40 /* Ensure TB is 0 */
41 li r3,0
42 mttbl r3
43 mttbu r3
44
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]45 /* Enable/invalidate the I-Cache */
46 mfspr r0,SPRN_L1CSR1
47 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
48 mtspr SPRN_L1CSR1,r0
49 isync
50
51 /* Enable/invalidate the D-Cache */
52 mfspr r0,SPRN_L1CSR0
53 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
54 msync
55 isync
56 mtspr SPRN_L1CSR0,r0
57 isync
58
59#define toreset(x) (x - __secondary_start_page + 0xfffff000)
60
61 /* get our PIR to figure out our table entry */
62 lis r3,toreset(__spin_table)@h
63 ori r3,r3,toreset(__spin_table)@l
64
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]65 /* r10 has the base address for the entry */
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]66 mfspr r0,SPRN_PIR
67 mr r4,r0
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]68 slwi r8,r4,5
69 add r10,r3,r8
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]70
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]71#define EPAPR_MAGIC (0x45504150)
72#define ENTRY_ADDR_UPPER 0
73#define ENTRY_ADDR_LOWER 4
74#define ENTRY_R3_UPPER 8
75#define ENTRY_R3_LOWER 12
76#define ENTRY_RESV 16
77#define ENTRY_PIR 20
78#define ENTRY_R6_UPPER 24
79#define ENTRY_R6_LOWER 28
80#define ENTRY_SIZE 32
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]81
82 /* setup the entry */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]83 li r3,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]84 li r8,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]85 stw r0,ENTRY_PIR(r10)
86 stw r3,ENTRY_ADDR_UPPER(r10)
87 stw r8,ENTRY_ADDR_LOWER(r10)
88 stw r3,ENTRY_R3_UPPER(r10)
89 stw r4,ENTRY_R3_LOWER(r10)
90 stw r3,ENTRY_R6_UPPER(r10)
91 stw r3,ENTRY_R6_LOWER(r10)
92
93 /* setup mapping for AS = 1, and jump there */
94 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
95 mtspr SPRN_MAS0,r11
96 lis r11,(MAS1_VALID|MAS1_IPROT)@h
97 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
98 mtspr SPRN_MAS1,r11
99 lis r11,(0xfffff000|MAS2_I)@h
100 ori r11,r11,(0xfffff000|MAS2_I)@l
101 mtspr SPRN_MAS2,r11
102 lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
103 ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
104 mtspr SPRN_MAS3,r11
105 tlbwe
106
107 bl 1f
1081: mflr r11
109 addi r11,r11,28
110 mfmsr r13
111 ori r12,r13,MSR_IS|MSR_DS@l
112
113 mtspr SPRN_SRR0,r11
114 mtspr SPRN_SRR1,r12
115 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]116
117 /* spin waiting for addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]1182:
119 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]120 andi. r11,r4,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]121 bne 2b
Kumar Galacf6cc012008-04-28 02:24:04 -0500[diff] [blame]122 isync
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]123
124 /* get the upper bits of the addr */
125 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]126
127 /* setup branch addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]128 mtspr SPRN_SRR0,r4
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]129
130 /* mark the entry as released */
131 li r8,3
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]132 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]133
134 /* mask by ~64M to setup our tlb we will jump to */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]135 rlwinm r12,r4,0,0,5
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]136
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]137 /* setup r3, r4, r5, r6, r7, r8, r9 */
138 lwz r3,ENTRY_R3_LOWER(r10)
139 li r4,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]140 li r5,0
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]141 lwz r6,ENTRY_R6_LOWER(r10)
142 lis r7,(64*1024*1024)@h
143 li r8,0
144 li r9,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]145
146 /* load up the pir */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]147 lwz r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]148 mtspr SPRN_PIR,r0
149 mfspr r0,SPRN_PIR
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]150 stw r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]151
152/*
153 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
154 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
155 * second mapping that maps addr 1:1 for 64M, and then we jump to
156 * addr
157 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]158 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
159 mtspr SPRN_MAS0,r10
160 lis r10,(MAS1_VALID|MAS1_IPROT)@h
161 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
162 mtspr SPRN_MAS1,r10
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]163 /* WIMGE = 0b00000 for now */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]164 mtspr SPRN_MAS2,r12
165 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
166 mtspr SPRN_MAS3,r12
167#ifdef CONFIG_ENABLE_36BIT_PHYS
168 mtspr SPRN_MAS7,r11
169#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]170 tlbwe
171
172/* Now we have another mapping for this page, so we jump to that
173 * mapping
174 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]175 mtspr SPRN_SRR1,r13
176 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]177
Kumar Galacf6cc012008-04-28 02:24:04 -0500[diff] [blame]178 .align L1_CACHE_SHIFT
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]179 .globl __spin_table
180__spin_table:
Kumar Gala902ca092008-08-11 11:29:28 -0500[diff] [blame]181 .space CONFIG_NUM_CPUS*ENTRY_SIZE
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]182
183 /* Fill in the empty space. The actual reset vector is
184 * the last word of the page */
185__secondary_start_code_end:
186 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
187__secondary_reset_vector:
188 b __secondary_start_page