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wdenk2d39b712000-12-14 10:04:19 +00001/*
wdenk180d3f72004-01-04 16:28:35 +00002 * (C) Copyright 2000-2004
wdenk2d39b712000-12-14 10:04:19 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenk180d3f72004-01-04 16:28:35 +00005 * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
6 * and Dan Malek
7 *
8 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
9 *
10 * This header file contains values common to all FADS family boards.
11 *
wdenk2d39b712000-12-14 10:04:19 +000012 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/****************************************************************************
wdenk180d3f72004-01-04 16:28:35 +000032 * Flash Memory Map as used by U-Boot:
wdenk2d39b712000-12-14 10:04:19 +000033 *
34 * Start Address Length
35 * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
wdenk180d3f72004-01-04 16:28:35 +000036 * | | 0xFE00_0100 Reset Vector
37 * + + 0xFE0?_????
38 * | U-Boot code |
39 * | |
40 * +-----------------------+ 0xFE04_0000 (sector border)
41 * | |
42 * | |
43 * | U-Boot environment |
44 * | | ^
45 * | | | U-Boot
46 * +=======================+ 0xFE08_0000 (sector border) -----------------
47 * | Available | | Applications
wdenk2d39b712000-12-14 10:04:19 +000048 * | ... | v
49 *
50 *****************************************************************************/
wdenk180d3f72004-01-04 16:28:35 +000051
52#if 0
53#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54#else
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56#endif
57
Wolfgang Denk8ff02082006-03-12 01:55:43 +010058#define CONFIG_ENV_OVERWRITE
59
60#define CONFIG_NFSBOOTCOMMAND \
wdenk180d3f72004-01-04 16:28:35 +000061 "dhcp;" \
Wolfgang Denk8ff02082006-03-12 01:55:43 +010062 "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
63 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
wdenk180d3f72004-01-04 16:28:35 +000064 "bootm"
65
Wolfgang Denk8ff02082006-03-12 01:55:43 +010066#define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
68 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
69 "bootm fe080000"
70
71#undef CONFIG_BOOTARGS
72
wdenk180d3f72004-01-04 16:28:35 +000073#undef CONFIG_WATCHDOG /* watchdog disabled */
Scott Wood78f9fef2007-08-15 15:46:46 -050074
75#if !defined(CONFIG_MPC885ADS)
wdenk11142572004-06-06 21:35:06 +000076#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
Scott Wood78f9fef2007-08-15 15:46:46 -050077#endif
wdenk180d3f72004-01-04 16:28:35 +000078
79/*
Wolfgang Denk8ff02082006-03-12 01:55:43 +010080 * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
wdenk180d3f72004-01-04 16:28:35 +000081 * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
82 * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
83 * got FEC so FEC is the default.
84 */
85#ifndef CONFIG_ADS
86#undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
87#define CONFIG_FEC_ENET /* Use FEC ethernet */
88#else /* Old ADS has not got FEC option */
89#define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
90#undef CONFIG_FEC_ENET /* No FEC ethernet */
91#endif /* !CONFIG_ADS */
92
93#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
94#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
95#endif
96
97#ifdef CONFIG_FEC_ENET
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_DISCOVER_PHY
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050099#define CONFIG_MII_INIT 1
wdenk180d3f72004-01-04 16:28:35 +0000100#endif
101
Jon Loeliger079a1362007-07-10 10:12:10 -0500102
103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110
111
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500112#if !defined(FADS_COMMANDS_ALREADY_DEFINED)
113/*
114 * Command line configuration.
115 */
116#include <config_cmd_default.h>
wdenk180d3f72004-01-04 16:28:35 +0000117
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500118#define CONFIG_CMD_ASKENV
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_ECHO
121#define CONFIG_CMD_IMMAP
122#define CONFIG_CMD_JFFS2
123#define CONFIG_CMD_MII
124#define CONFIG_CMD_PCMCIA
125#define CONFIG_CMD_PING
126
127#endif
128
wdenk180d3f72004-01-04 16:28:35 +0000129
130/*
131 * Miscellaneous configurable options
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
134#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_LONGHELP /* #undef to save memory */
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500136#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000138#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000140#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
142#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk180d3f72004-01-04 16:28:35 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_LOAD_ADDR 0x00100000
wdenk180d3f72004-01-04 16:28:35 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk180d3f72004-01-04 16:28:35 +0000148
wdenk180d3f72004-01-04 16:28:35 +0000149/*
150 * Low Level Configuration Settings
151 * (address mappings, register initial values, etc.)
152 * You should know what you are doing if you make changes here.
153 */
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100154
wdenk180d3f72004-01-04 16:28:35 +0000155/*-----------------------------------------------------------------------
156 * Internal Memory Mapped Register
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_IMMR 0xFF000000
wdenk180d3f72004-01-04 16:28:35 +0000159
160/*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200164#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200165#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk180d3f72004-01-04 16:28:35 +0000167
168/*-----------------------------------------------------------------------
169 * Start addresses for the final memory configuration
170 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk180d3f72004-01-04 16:28:35 +0000172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk11142572004-06-06 21:35:06 +0000174#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100176/*
177 * 2048 SDRAM rows
178 * 1000 factor s -> ms
179 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
180 * 4 Number of refresh cycles per period
181 * 64 Refresh cycle in ms per number of rows
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
wdenk180d3f72004-01-04 16:28:35 +0000184#elif defined(CONFIG_FADS) /* Old/new FADS */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
wdenk180d3f72004-01-04 16:28:35 +0000186#else /* Old ADS */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
wdenk180d3f72004-01-04 16:28:35 +0000188#endif
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
191#if (CONFIG_SYS_SDRAM_SIZE)
192#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
wdenk180d3f72004-01-04 16:28:35 +0000193#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
195#endif /* CONFIG_SYS_SDRAM_SIZE */
wdenk180d3f72004-01-04 16:28:35 +0000196
197/*
198 * For booting Linux, the board info and command line data
199 * have to be in the first 8 MB of memory, since this is
200 * the maximum mapped by the Linux kernel during initialization.
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk99edcfb2004-06-09 21:54:22 +0000203
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
wdenk99edcfb2004-06-09 21:54:22 +0000206
207#ifdef CONFIG_BZIP2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
wdenk99edcfb2004-06-09 21:54:22 +0000209#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
wdenk99edcfb2004-06-09 21:54:22 +0000211#endif /* CONFIG_BZIP2 */
212
wdenk180d3f72004-01-04 16:28:35 +0000213/*-----------------------------------------------------------------------
214 * Flash organization
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
217#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
wdenk180d3f72004-01-04 16:28:35 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
220#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk180d3f72004-01-04 16:28:35 +0000221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
223#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk180d3f72004-01-04 16:28:35 +0000224
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200225#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200226#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
227#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
228#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk180d3f72004-01-04 16:28:35 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_DIRECT_FLASH_TFTP
wdenk11142572004-06-06 21:35:06 +0000232
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500233#if defined(CONFIG_CMD_JFFS2)
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200234
235/*
236 * JFFS2 partitions
237 *
238 */
239/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100240#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200241#define CONFIG_JFFS2_DEV "nor0"
242#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
243#define CONFIG_JFFS2_PART_OFFSET 0x00000000
244
245/* mtdparts command line support */
246/* Note: fake mtd_id used, no linux mtd map file */
247/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100248#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200249#define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
250#define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
251*/
252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
Jon Loeliger77a31852007-07-10 10:39:10 -0500254#endif
wdenk180d3f72004-01-04 16:28:35 +0000255
256/*-----------------------------------------------------------------------
257 * Cache Configuration
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
260#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk180d3f72004-01-04 16:28:35 +0000261
262/*-----------------------------------------------------------------------
263 * I2C configuration
264 */
Jon Loeligerc508a4c2007-07-09 18:31:28 -0500265#if defined(CONFIG_CMD_I2C)
wdenk180d3f72004-01-04 16:28:35 +0000266#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
268#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk180d3f72004-01-04 16:28:35 +0000269#endif
270
271/*-----------------------------------------------------------------------
272 * SYPCR - System Protection Control 11-9
273 * SYPCR can only be written once after reset!
274 *-----------------------------------------------------------------------
275 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
276 */
277#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk180d3f72004-01-04 16:28:35 +0000279 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
280#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk180d3f72004-01-04 16:28:35 +0000282#endif
283
284/*-----------------------------------------------------------------------
285 * SIUMCR - SIU Module Configuration 11-6
286 *-----------------------------------------------------------------------
287 * PCMCIA config., multi-function pin tri-state
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk180d3f72004-01-04 16:28:35 +0000290
291/*-----------------------------------------------------------------------
292 * TBSCR - Time Base Status and Control 11-26
293 *-----------------------------------------------------------------------
294 * Clear Reference Interrupt Status, Timebase freezing enabled
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk180d3f72004-01-04 16:28:35 +0000297
298/*-----------------------------------------------------------------------
299 * PISCR - Periodic Interrupt Status and Control 11-31
300 *-----------------------------------------------------------------------
301 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk180d3f72004-01-04 16:28:35 +0000304
305/*-----------------------------------------------------------------------
306 * SCCR - System Clock and reset Control Register 15-27
307 *-----------------------------------------------------------------------
308 * Set clock output, timebase and RTC source and divider,
309 * power management and some other internal clocks
310 */
311#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_SCCR SCCR_TBS
wdenk180d3f72004-01-04 16:28:35 +0000313
wdenk11142572004-06-06 21:35:06 +0000314/*-----------------------------------------------------------------------
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100315 * DER - Debug Enable Register
wdenk11142572004-06-06 21:35:06 +0000316 *-----------------------------------------------------------------------
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100317 * Set to zero to prevent the processor from entering debug mode
wdenk180d3f72004-01-04 16:28:35 +0000318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_DER 0
wdenk180d3f72004-01-04 16:28:35 +0000320
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100321/* Because of the way the 860 starts up and assigns CS0 the entire
322 * address space, we have to set the memory controller differently.
323 * Normally, you write the option register first, and then enable the
324 * chip select by writing the base register. For CS0, you must write
325 * the base register first, followed by the option register.
326 */
wdenk180d3f72004-01-04 16:28:35 +0000327
328/*
329 * Init Memory Controller:
330 *
331 * BR0/OR0 (Flash)
332 * BR1/OR1 (BCSR)
333 */
334/* the other CS:s are determined by looking at parameters in BCSRx */
335
336#define BCSR_ADDR ((uint) 0xFF080000)
337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenk180d3f72004-01-04 16:28:35 +0000339
340/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
wdenk180d3f72004-01-04 16:28:35 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
344#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
wdenk180d3f72004-01-04 16:28:35 +0000345
346/* BCSRx - Board Control and Status Registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
348#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
wdenk180d3f72004-01-04 16:28:35 +0000349
wdenk180d3f72004-01-04 16:28:35 +0000350/* values according to the manual */
351
wdenk180d3f72004-01-04 16:28:35 +0000352#define BCSR0 ((uint) (BCSR_ADDR + 0x00))
353#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
354#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
355#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
356#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
357
358/*
359 * (F)ADS bitvalues by Helmut Buchsbaum
360 *
361 * See User's Manual for a proper
362 * description of the following structures
363 */
364
365#define BCSR0_ERB ((uint)0x80000000)
366#define BCSR0_IP ((uint)0x40000000)
367#define BCSR0_BDIS ((uint)0x10000000)
368#define BCSR0_BPS_MASK ((uint)0x0C000000)
369#define BCSR0_ISB_MASK ((uint)0x01800000)
370#define BCSR0_DBGC_MASK ((uint)0x00600000)
371#define BCSR0_DBPC_MASK ((uint)0x00180000)
372#define BCSR0_EBDF_MASK ((uint)0x00060000)
373
374#define BCSR1_FLASH_EN ((uint)0x80000000)
375#define BCSR1_DRAM_EN ((uint)0x40000000)
376#define BCSR1_ETHEN ((uint)0x20000000)
377#define BCSR1_IRDEN ((uint)0x10000000)
378#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
379#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
380#define BCSR1_BCSR_EN ((uint)0x02000000)
381#define BCSR1_RS232EN_1 ((uint)0x01000000)
382#define BCSR1_PCCEN ((uint)0x00800000)
383#define BCSR1_PCCVCC0 ((uint)0x00400000)
384#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
385#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
386#define BCSR1_RS232EN_2 ((uint)0x00040000)
387#define BCSR1_SDRAM_EN ((uint)0x00020000)
388#define BCSR1_PCCVCC1 ((uint)0x00010000)
389
390#define BCSR1_PCCVCCON BCSR1_PCCVCC0
391
392#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenk99edcfb2004-06-09 21:54:22 +0000393#define BCSR2_FLASH_PD_SHIFT 28
wdenk180d3f72004-01-04 16:28:35 +0000394#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
395#define BCSR2_DRAM_PD_SHIFT 23
396#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
397#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
398
399#define BCSR3_DBID_MASK ((ushort)0x3800)
400#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
401#define BCSR3_BREVNR0 ((ushort)0x0080)
402#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
403#define BCSR3_BREVN1 ((ushort)0x0008)
404#define BCSR3_BREVN2_MASK ((ushort)0x0003)
405
406#define BCSR4_ETHLOOP ((uint)0x80000000)
407#define BCSR4_TFPLDL ((uint)0x40000000)
408#define BCSR4_TPSQEL ((uint)0x20000000)
409#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100410#if defined(CONFIG_MPC823)
wdenk180d3f72004-01-04 16:28:35 +0000411#define BCSR4_USB_EN ((uint)0x08000000)
wdenk180d3f72004-01-04 16:28:35 +0000412#define BCSR4_USB_SPEED ((uint)0x04000000)
wdenk180d3f72004-01-04 16:28:35 +0000413#define BCSR4_VCCO ((uint)0x02000000)
wdenk180d3f72004-01-04 16:28:35 +0000414#define BCSR4_VIDEO_ON ((uint)0x00800000)
wdenk180d3f72004-01-04 16:28:35 +0000415#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
wdenk180d3f72004-01-04 16:28:35 +0000416#define BCSR4_VIDEO_RST ((uint)0x00200000)
wdenk180d3f72004-01-04 16:28:35 +0000417#define BCSR4_MODEM_EN ((uint)0x00100000)
wdenk180d3f72004-01-04 16:28:35 +0000418#define BCSR4_DATA_VOICE ((uint)0x00080000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100419#elif defined(CONFIG_MPC850)
wdenk180d3f72004-01-04 16:28:35 +0000420#define BCSR4_DATA_VOICE ((uint)0x00080000)
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100421#elif defined(CONFIG_MPC860SAR)
422#define BCSR4_UTOPIA_EN ((uint)0x08000000)
423#else /* MPC860T and other chips with FEC */
424#define BCSR4_FETH_EN ((uint)0x08000000)
425#define BCSR4_FETHCFG0 ((uint)0x04000000)
426#define BCSR4_FETHFDE ((uint)0x02000000)
427#define BCSR4_FETHCFG1 ((uint)0x00400000)
428#define BCSR4_FETHRST ((uint)0x00200000)
429#endif
wdenk180d3f72004-01-04 16:28:35 +0000430
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100431/* BSCR5 exists on MPC86xADS and MPC885ADS only */
wdenk11142572004-06-06 21:35:06 +0000432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
wdenk11142572004-06-06 21:35:06 +0000434
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
wdenk11142572004-06-06 21:35:06 +0000436
437#define BCSR5_MII2_EN 0x40
438#define BCSR5_MII2_RST 0x20
439#define BCSR5_T1_RST 0x10
440#define BCSR5_ATM155_RST 0x08
441#define BCSR5_ATM25_RST 0x04
442#define BCSR5_MII1_EN 0x02
443#define BCSR5_MII1_RST 0x01
444
wdenk180d3f72004-01-04 16:28:35 +0000445/* We don't use the 8259.
446*/
447#define NR_8259_INTS 0
448
wdenk180d3f72004-01-04 16:28:35 +0000449/*-----------------------------------------------------------------------
450 * PCMCIA stuff
451 *-----------------------------------------------------------------------
452 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
454#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
455#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
456#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
457#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
458#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
459#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
460#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk180d3f72004-01-04 16:28:35 +0000461
462/*-----------------------------------------------------------------------
463 * IDE/ATA stuff
464 *-----------------------------------------------------------------------
465 */
466#define CONFIG_MAC_PARTITION 1
467#define CONFIG_DOS_PARTITION 1
468#define CONFIG_ISO_PARTITION 1
469
470#undef CONFIG_ATAPI
Jon Loeliger77a31852007-07-10 10:39:10 -0500471#if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
wdenk180d3f72004-01-04 16:28:35 +0000472#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
Wolfgang Denk966083e2006-07-21 15:24:56 +0200473#endif
wdenk180d3f72004-01-04 16:28:35 +0000474#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
475#undef CONFIG_IDE_LED /* LED for ide not supported */
476#undef CONFIG_IDE_RESET /* reset for ide not supported */
477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
479#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenk180d3f72004-01-04 16:28:35 +0000480
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
482#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk180d3f72004-01-04 16:28:35 +0000483
484/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk180d3f72004-01-04 16:28:35 +0000486/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk180d3f72004-01-04 16:28:35 +0000488/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
wdenk180d3f72004-01-04 16:28:35 +0000490
491#define CONFIG_DISK_SPINUP_TIME 1000000
Wolfgang Denk8ff02082006-03-12 01:55:43 +0100492/* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */