blob: 2209ddf8238db9010cc54111d2e9da177e8c6246 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040027 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060028 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Paul Gortmaker2738bc82009-09-20 20:36:06 -040032/*
33 * Top level Makefile configuration choices
34 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020035#ifdef CONFIG_PCI
Paul Gortmaker2738bc82009-09-20 20:36:06 -040036#define CONFIG_PCI1
37#endif
38
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020039#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040040#define CONFIG_SYS_CLK_DIV 1
41#endif
42
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020043#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040044#define CONFIG_SYS_CLK_DIV 2
45#endif
46
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020047#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040048#define CONFIG_PCIE1
49#endif
50
51/*
52 * High Level Configuration Options
53 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060054#define CONFIG_BOOKE 1 /* BOOKE */
55#define CONFIG_E500 1 /* BOOKE e500 family */
56#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
57#define CONFIG_MPC8548 1 /* MPC8548 specific */
58#define CONFIG_SBC8548 1 /* SBC8548 board specific */
59
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050060/*
61 * If you want to boot from the SODIMM flash, instead of the soldered
62 * on flash, set this, and change JP12, SW2:8 accordingly.
63 */
64#undef CONFIG_SYS_ALT_BOOT
65
Wolfgang Denk2ae18242010-10-06 09:05:45 +020066#ifndef CONFIG_SYS_TEXT_BASE
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050067#ifdef CONFIG_SYS_ALT_BOOT
68#define CONFIG_SYS_TEXT_BASE 0xfff00000
69#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020070#define CONFIG_SYS_TEXT_BASE 0xfffa0000
71#endif
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050072#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020073
Joe Hamman9e3ed392007-12-13 06:45:14 -060074#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040075
76#ifdef CONFIG_PCI
77#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
78#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
79#endif
80#ifdef CONFIG_PCIE1
81#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
82#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060083
84#define CONFIG_TSEC_ENET /* tsec ethernet support */
85#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060086
Joe Hamman9e3ed392007-12-13 06:45:14 -060087#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
88
Kumar Galae2b159d2008-01-16 09:05:27 -060089#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060090
Paul Gortmaker2738bc82009-09-20 20:36:06 -040091/*
92 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
93 */
94#ifndef CONFIG_SYS_CLK_DIV
95#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
96#endif
97#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060098
99/*
100 * These can be toggled for performance analysis, otherwise use default.
101 */
102#define CONFIG_L2_CACHE /* toggle L2 cache */
103#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600104
105/*
106 * Only possible on E500 Version 2 or newer cores.
107 */
108#define CONFIG_ENABLE_36BIT_PHYS 1
109
110#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
113#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600115
Timur Tabie46fedf2011-08-04 18:03:41 -0500116#define CONFIG_SYS_CCSRBAR 0xe0000000
117#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Joe Hamman9e3ed392007-12-13 06:45:14 -0600118
Kumar Gala33b90792008-08-26 23:15:28 -0500119/* DDR Setup */
120#define CONFIG_FSL_DDR2
121#undef CONFIG_FSL_DDR_INTERACTIVE
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500122#undef CONFIG_DDR_ECC /* only for ECC DDR module */
123/*
124 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
125 * to collide, meaning you couldn't reliably read either. So
126 * physically remove the LBC PC100 SDRAM module from the board
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500127 * before enabling the two SPD options below, or check that you
128 * have the hardware fix on your board via "i2c probe" and looking
129 * for a device at 0x53.
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500130 */
Kumar Gala33b90792008-08-26 23:15:28 -0500131#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
132#undef CONFIG_DDR_SPD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600133
Kumar Gala33b90792008-08-26 23:15:28 -0500134#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
135#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
138#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500139#define CONFIG_VERY_BIG_RAM
140
141#define CONFIG_NUM_DDR_CONTROLLERS 1
142#define CONFIG_DIMM_SLOTS_PER_CTLR 1
143#define CONFIG_CHIP_SELECTS_PER_CTRL 2
144
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500145/*
146 * The hardware fix for the I2C address collision puts the DDR
147 * SPD at 0x53, but if we are running on an older board w/o the
148 * fix, it will still be at 0x51. We check 0x53 1st.
149 */
Kumar Gala33b90792008-08-26 23:15:28 -0500150#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500151#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600152
153/*
154 * Make sure required options are set
155 */
156#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -0500158 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600159#endif
160
161#undef CONFIG_CLOCKS_IN_MHZ
162
163/*
164 * FLASH on the Local Bus
165 * Two banks, one 8MB the other 64MB, using the CFI driver.
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500166 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
167 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600168 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500169 * Default:
170 * ec00_0000 efff_ffff 64MB SODIMM
171 * ff80_0000 ffff_ffff 8MB soldered flash
172 *
173 * Alternate:
174 * ef80_0000 efff_ffff 8MB soldered flash
175 * fc00_0000 ffff_ffff 64MB SODIMM
176 *
177 * BR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600178 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
179 * Port Size = 8 bits = BRx[19:20] = 01
180 * Use GPCM = BRx[24:26] = 000
181 * Valid = BRx[31] = 1
182 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500183 * BR0_64M:
184 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600185 * Port Size = 32 bits = BRx[19:20] = 11
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500186 *
187 * 0 4 8 12 16 20 24 28
188 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
189 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
190 */
191#define CONFIG_SYS_BR0_8M 0xff800801
192#define CONFIG_SYS_BR0_64M 0xfc001801
193
194/*
195 * BR6_8M:
196 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
197 * Port Size = 8 bits = BRx[19:20] = 01
Joe Hamman9e3ed392007-12-13 06:45:14 -0600198 * Use GPCM = BRx[24:26] = 000
199 * Valid = BRx[31] = 1
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500200
201 * BR6_64M:
202 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
203 * Port Size = 32 bits = BRx[19:20] = 11
Joe Hamman9e3ed392007-12-13 06:45:14 -0600204 *
205 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500206 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
207 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
208 */
209#define CONFIG_SYS_BR6_8M 0xef800801
210#define CONFIG_SYS_BR6_64M 0xec001801
211
212/*
213 * OR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600214 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
215 * XAM = OR0[17:18] = 11
216 * CSNT = OR0[20] = 1
217 * ACS = half cycle delay = OR0[21:22] = 11
218 * SCY = 6 = OR0[24:27] = 0110
219 * TRLX = use relaxed timing = OR0[29] = 1
220 * EAD = use external address latch delay = OR0[31] = 1
221 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500222 * OR0_64M:
223 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600224 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500225 *
226 * 0 4 8 12 16 20 24 28
227 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
228 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
229 */
230#define CONFIG_SYS_OR0_8M 0xff806e65
231#define CONFIG_SYS_OR0_64M 0xfc006e65
232
233/*
234 * OR6_8M:
235 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600236 * XAM = OR6[17:18] = 11
237 * CSNT = OR6[20] = 1
238 * ACS = half cycle delay = OR6[21:22] = 11
239 * SCY = 6 = OR6[24:27] = 0110
240 * TRLX = use relaxed timing = OR6[29] = 1
241 * EAD = use external address latch delay = OR6[31] = 1
242 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500243 * OR6_64M:
244 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
245 *
Joe Hamman9e3ed392007-12-13 06:45:14 -0600246 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500247 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
248 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600249 */
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500250#define CONFIG_SYS_OR6_8M 0xff806e65
251#define CONFIG_SYS_OR6_64M 0xfc006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600252
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500253#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker3fd673c2011-12-30 23:53:07 -0500255#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600256
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500257#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
258#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600259
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500260#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
261#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
262#else /* JP12 in alternate position */
263#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
264#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600265
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500266#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
267#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
268
269#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
270#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
271#endif
272
273#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400274#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
275 CONFIG_SYS_ALT_FLASH}
276#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
277#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#undef CONFIG_SYS_FLASH_CHECKSUM
279#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
280#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600281
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200282#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600283
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200284#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_FLASH_CFI
286#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600287
288/* CS5 = Local bus peripherals controlled by the EPLD */
289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BR5_PRELIM 0xf8000801
291#define CONFIG_SYS_OR5_PRELIM 0xff006e65
292#define CONFIG_SYS_EPLD_BASE 0xf8000000
293#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
294#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
295#define CONFIG_SYS_BD_REV 0xf8300000
296#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600297
298/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400299 * SDRAM on the Local Bus (CS3 and CS4)
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500300 * Note that most boards have a hardware errata where both the
301 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
302 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500303 * A hardware workaround is also available, see README.sbc8548 file.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400306#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600307
308/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400309 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600311 *
312 * For BR3, need:
313 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
314 * port-size = 32-bits = BR2[19:20] = 11
315 * no parity checking = BR2[21:22] = 00
316 * SDRAM for MSEL = BR2[24:26] = 011
317 * Valid = BR[31] = 1
318 *
319 * 0 4 8 12 16 20 24 28
320 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
321 *
322 */
323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600325
326/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400327 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600328 *
329 * For OR3, need:
330 * 64MB mask for AM, OR3[0:7] = 1111 1100
331 * XAM, OR3[17:18] = 11
332 * 10 columns OR3[19-21] = 011
333 * 12 rows OR3[23-25] = 011
334 * EAD set for extra time OR[31] = 0
335 *
336 * 0 4 8 12 16 20 24 28
337 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
338 */
339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600341
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400342/*
343 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
344 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
345 *
346 * For BR4, need:
347 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
348 * port-size = 32-bits = BR2[19:20] = 11
349 * no parity checking = BR2[21:22] = 00
350 * SDRAM for MSEL = BR2[24:26] = 011
351 * Valid = BR[31] = 1
352 *
353 * 0 4 8 12 16 20 24 28
354 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
355 *
356 */
357
358#define CONFIG_SYS_BR4_PRELIM 0xf4001861
359
360/*
361 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
362 *
363 * For OR4, need:
364 * 64MB mask for AM, OR3[0:7] = 1111 1100
365 * XAM, OR3[17:18] = 11
366 * 10 columns OR3[19-21] = 011
367 * 12 rows OR3[23-25] = 011
368 * EAD set for extra time OR[31] = 0
369 *
370 * 0 4 8 12 16 20 24 28
371 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
372 */
373
374#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
375
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
377#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
378#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
379#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600380
381/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600382 * Common settings for all Local Bus SDRAM commands.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600383 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500384#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500385 | LSDMR_BSMA1516 \
386 | LSDMR_PRETOACT3 \
387 | LSDMR_ACTTORW3 \
388 | LSDMR_BUFCMD \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500389 | LSDMR_BL8 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500390 | LSDMR_WRC2 \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500391 | LSDMR_CL3 \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600392 )
393
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500394#define CONFIG_SYS_LBC_LSDMR_PCHALL \
395 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
396#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
397 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
398#define CONFIG_SYS_LBC_LSDMR_MRW \
399 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
400#define CONFIG_SYS_LBC_LSDMR_RFEN \
401 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_INIT_RAM_LOCK 1
404#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200405#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600408
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200409#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600411
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400412/*
413 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200414 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400415 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200416 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400417 * thing for MONITOR_LEN in both cases.
418 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200419#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500420#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600421
422/* Serial Port */
423#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_NS16550
425#define CONFIG_SYS_NS16550_SERIAL
426#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400427#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600430 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
431
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
433#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600434
435/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_HUSH_PARSER
Joe Hamman9e3ed392007-12-13 06:45:14 -0600437
438/* pass open firmware flat tree */
439#define CONFIG_OF_LIBFDT 1
440#define CONFIG_OF_BOARD_SETUP 1
441#define CONFIG_OF_STDOUT_VIA_ALIAS 1
442
443/*
444 * I2C
445 */
446#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
447#define CONFIG_HARD_I2C /* I2C with hardware support*/
448#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
450#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
451#define CONFIG_SYS_I2C_SLAVE 0x7F
452#define CONFIG_SYS_I2C_OFFSET 0x3000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600453
454/*
455 * General PCI
456 * Memory space is mapped 1-1, but I/O space must start from 0.
457 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400458#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600460
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400461#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
462#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
463#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400465#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
466#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
467#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
468#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600469
470#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400471#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
472#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
473#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400475#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
476#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
477#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
478#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600479#endif
480
481#ifdef CONFIG_RIO
482/*
483 * RapidIO MMU
484 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
486#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600487#endif
488
Joe Hamman9e3ed392007-12-13 06:45:14 -0600489#if defined(CONFIG_PCI)
490
Joe Hamman9e3ed392007-12-13 06:45:14 -0600491#define CONFIG_PCI_PNP /* do pci plug-and-play */
492
493#undef CONFIG_EEPRO100
494#undef CONFIG_TULIP
495
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400496#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600497
Joe Hamman9e3ed392007-12-13 06:45:14 -0600498#endif /* CONFIG_PCI */
499
500
501#if defined(CONFIG_TSEC_ENET)
502
Joe Hamman9e3ed392007-12-13 06:45:14 -0600503#define CONFIG_MII 1 /* MII PHY management */
504#define CONFIG_TSEC1 1
505#define CONFIG_TSEC1_NAME "eTSEC0"
506#define CONFIG_TSEC2 1
507#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600508#undef CONFIG_MPC85XX_FEC
509
Paul Gortmaker58da8892008-12-11 15:47:50 -0500510#define TSEC1_PHY_ADDR 0x19
511#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600512
513#define TSEC1_PHYIDX 0
514#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500515
Joe Hamman9e3ed392007-12-13 06:45:14 -0600516#define TSEC1_FLAGS TSEC_GIGABIT
517#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600518
519/* Options are: eTSEC[0-3] */
520#define CONFIG_ETHPRIME "eTSEC0"
521#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
522#endif /* CONFIG_TSEC_ENET */
523
524/*
525 * Environment
526 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200527#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200528#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200529#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400530#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
531#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200532#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400533#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
534#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
535#else
536#warning undefined environment size/location.
537#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600538
539#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600541
542/*
543 * BOOTP options
544 */
545#define CONFIG_BOOTP_BOOTFILESIZE
546#define CONFIG_BOOTP_BOOTPATH
547#define CONFIG_BOOTP_GATEWAY
548#define CONFIG_BOOTP_HOSTNAME
549
550
551/*
552 * Command line configuration.
553 */
554#include <config_cmd_default.h>
555
556#define CONFIG_CMD_PING
557#define CONFIG_CMD_I2C
558#define CONFIG_CMD_MII
559#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500560#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600561
562#if defined(CONFIG_PCI)
563 #define CONFIG_CMD_PCI
564#endif
565
566
567#undef CONFIG_WATCHDOG /* watchdog disabled */
568
569/*
570 * Miscellaneous configurable options
571 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500572#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500573#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_LONGHELP /* undef to save memory */
575#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
576#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600577#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600579#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600581#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
583#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
584#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
585#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600586
587/*
588 * For booting Linux, the board info and command line data
589 * have to be in the first 8 MB of memory, since this is
590 * the maximum mapped by the Linux kernel during initialization.
591 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600593
Joe Hamman9e3ed392007-12-13 06:45:14 -0600594#if defined(CONFIG_CMD_KGDB)
595#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
596#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
597#endif
598
599/*
600 * Environment Configuration
601 */
602
603/* The mac addresses for all ethernet interface */
604#if defined(CONFIG_TSEC_ENET)
605#define CONFIG_HAS_ETH0
606#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
607#define CONFIG_HAS_ETH1
608#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600609#endif
610
611#define CONFIG_IPADDR 192.168.0.55
612
613#define CONFIG_HOSTNAME sbc8548
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000614#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000615#define CONFIG_BOOTFILE "/uImage"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600616#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
617
618#define CONFIG_SERVERIP 192.168.0.2
619#define CONFIG_GATEWAYIP 192.168.0.1
620#define CONFIG_NETMASK 255.255.255.0
621
622#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
623
624#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
625#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
626
627#define CONFIG_BAUDRATE 115200
628
629#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200630"netdev=eth0\0" \
631"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
632"tftpflash=tftpboot $loadaddr $uboot; " \
633 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
634 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
635 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
636 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
637 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
638"consoledev=ttyS0\0" \
639"ramdiskaddr=2000000\0" \
640"ramdiskfile=uRamdisk\0" \
641"fdtaddr=c00000\0" \
642"fdtfile=sbc8548.dtb\0"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600643
644#define CONFIG_NFSBOOTCOMMAND \
645 "setenv bootargs root=/dev/nfs rw " \
646 "nfsroot=$serverip:$rootpath " \
647 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
648 "console=$consoledev,$baudrate $othbootargs;" \
649 "tftp $loadaddr $bootfile;" \
650 "tftp $fdtaddr $fdtfile;" \
651 "bootm $loadaddr - $fdtaddr"
652
653
654#define CONFIG_RAMBOOTCOMMAND \
655 "setenv bootargs root=/dev/ram rw " \
656 "console=$consoledev,$baudrate $othbootargs;" \
657 "tftp $ramdiskaddr $ramdiskfile;" \
658 "tftp $loadaddr $bootfile;" \
659 "tftp $fdtaddr $fdtfile;" \
660 "bootm $loadaddr $ramdiskaddr $fdtaddr"
661
662#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
663
664#endif /* __CONFIG_H */