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dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
dzu@denx.de6ca24c62006-04-21 18:30:47 +02002 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2004-2005
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10 *
11 * (C) Copyright 2006
12 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
13 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020014 * SPDX-License-Identifier: GPL-2.0+
dzu@denx.de6ca24c62006-04-21 18:30:47 +020015 */
16
17#include <common.h>
18#include <mpc5xxx.h>
19#include <pci.h>
Ben Warren19403632008-08-31 10:03:22 -070020#include <netdev.h>
dzu@denx.de6ca24c62006-04-21 18:30:47 +020021
22#ifdef CONFIG_VIDEO_SM501
23#include <sm501.h>
24#endif
25
26#if defined(CONFIG_MPC5200_DDR)
27#include "mt46v16m16-75.h"
28#else
29#include "mt48lc16m16a2-75.h"
30#endif
31
32#ifdef CONFIG_RTC_MPC5200
33#include <rtc.h>
Wolfgang Denk610cf362006-05-03 01:24:04 +020034#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +020035
36#ifdef CONFIG_PS2MULT
37void ps2mult_early_init(void);
38#endif
39
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#ifndef CONFIG_SYS_RAMBOOT
dzu@denx.de6ca24c62006-04-21 18:30:47 +020041static void sdram_start (int hi_addr)
42{
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
44
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
47 hi_addr_bit;
48 __asm__ volatile ("sync");
49
50 /* precharge all banks */
51 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
52 hi_addr_bit;
53 __asm__ volatile ("sync");
54
55#if SDRAM_DDR
56 /* set mode register: extended mode */
57 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
58 __asm__ volatile ("sync");
59
60 /* set mode register: reset DLL */
61 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
62 __asm__ volatile ("sync");
63#endif
64
65 /* precharge all banks */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
67 hi_addr_bit;
68 __asm__ volatile ("sync");
69
70 /* auto refresh */
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
72 hi_addr_bit;
73 __asm__ volatile ("sync");
74
75 /* set mode register */
76 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
77 __asm__ volatile ("sync");
78
79 /* normal operation */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
81 __asm__ volatile ("sync");
82}
83#endif
84
85/*
86 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
dzu@denx.de6ca24c62006-04-21 18:30:47 +020088 * is something else than 0x00000000.
89 */
90
Becky Bruce9973e3c2008-06-09 16:03:40 -050091phys_size_t initdram (int board_type)
dzu@denx.de6ca24c62006-04-21 18:30:47 +020092{
93 ulong dramsize = 0;
94 ulong dramsize2 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#ifndef CONFIG_SYS_RAMBOOT
dzu@denx.de6ca24c62006-04-21 18:30:47 +020096 ulong test1, test2;
97
98 /* setup SDRAM chip selects */
99 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
100 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
101 __asm__ volatile ("sync");
102
103 /* setup config registers */
104 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
105 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
106 __asm__ volatile ("sync");
107
108#if SDRAM_DDR
109 /* set tap delay */
110 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
111 __asm__ volatile ("sync");
112#endif
113
114 /* find RAM size using SDRAM CS0 only */
115 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200117 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200119 if (test1 > test2) {
120 sdram_start(0);
121 dramsize = test1;
122 } else {
123 dramsize = test2;
124 }
125
126 /* memory smaller than 1MB is impossible */
127 if (dramsize < (1 << 20)) {
128 dramsize = 0;
129 }
130
131 /* set SDRAM CS0 size according to the amount of RAM found */
132 if (dramsize > 0) {
133 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
134 __builtin_ffs(dramsize >> 20) - 1;
135 } else {
136 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
137 }
138
139 /* let SDRAM CS1 start right after CS0 */
140 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
141
142 /* find RAM size using SDRAM CS1 only */
143 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200145 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200147 if (test1 > test2) {
148 sdram_start(0);
149 dramsize2 = test1;
150 } else {
151 dramsize2 = test2;
152 }
153
154 /* memory smaller than 1MB is impossible */
155 if (dramsize2 < (1 << 20)) {
156 dramsize2 = 0;
157 }
158
159 /* set SDRAM CS1 size according to the amount of RAM found */
160 if (dramsize2 > 0) {
161 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
162 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
163 } else {
164 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
165 }
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#else /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200168
169 /* retrieve size of memory connected to SDRAM CS0 */
170 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
171 if (dramsize >= 0x13) {
172 dramsize = (1 << (dramsize - 0x13)) << 20;
173 } else {
174 dramsize = 0;
175 }
176
177 /* retrieve size of memory connected to SDRAM CS1 */
178 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
179 if (dramsize2 >= 0x13) {
180 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
181 } else {
182 dramsize2 = 0;
183 }
184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#endif /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200186
187 return dramsize;
188}
189
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200190int checkboard (void)
191{
192#if defined (CONFIG_TQM5200)
193 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
194#endif
195
196#if defined (CONFIG_BC3450)
197 puts ("Dev: GERSYS BC3450\n");
198#endif
199
200 return 0;
201}
202
203void flash_preinit(void)
204{
205 /*
206 * Now, when we are in RAM, enable flash write
207 * access for detection process.
208 * Note that CS_BOOT cannot be cleared when
209 * executing in flash.
210 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200211 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
212}
213
214
215#ifdef CONFIG_PCI
216static struct pci_controller hose;
217
218extern void pci_mpc5xxx_init(struct pci_controller *);
219
220void pci_init_board(void)
221{
222 pci_mpc5xxx_init(&hose);
223}
224#endif
225
Jon Loeliger77a31852007-07-10 10:39:10 -0500226#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200227
228void init_ide_reset (void)
229{
230 debug ("init_ide_reset\n");
231
232 /* Configure PSC1_4 as GPIO output for ATA reset */
233 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
234 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
235}
236
237void ide_set_reset (int idereset)
238{
239 debug ("ide_reset(%d)\n", idereset);
240
241 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100242 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200243 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100244 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200245 }
246}
Jon Loeliger77a31852007-07-10 10:39:10 -0500247#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200248
249#ifdef CONFIG_POST
250/*
251 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
252 * is left open, no keypress is detected.
253 */
254int post_hotkeys_pressed(void)
255{
256 struct mpc5xxx_gpio *gpio;
257
258 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
259
260 /*
261 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
262 * CODEC or UART mode. Consumer IrDA should still be possible.
263 */
264 gpio->port_config &= ~(0x07000000);
265 gpio->port_config |= 0x03000000;
266
267 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
268 gpio->simple_gpioe |= 0x20000000;
269
270 /* Configure GPIO_IRDA_1 as input */
271 gpio->simple_ddr &= ~(0x20000000);
272
273 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
274}
275#endif
276
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200277#ifdef CONFIG_BOARD_EARLY_INIT_R
278int board_early_init_r (void)
279{
280#ifdef CONFIG_RTC_MPC5200
Wolfgang Denk610cf362006-05-03 01:24:04 +0200281 struct rtc_time t;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200282
283 /* set to Wed Dec 31 19:00:00 1969 */
284 t.tm_sec = t.tm_min = 0;
285 t.tm_hour = 19;
286 t.tm_mday = 31;
287 t.tm_mon = 12;
288 t.tm_year = 1969;
289 t.tm_wday = 3;
Wolfgang Denk610cf362006-05-03 01:24:04 +0200290
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200291 rtc_set(&t);
292#endif /* CONFIG_RTC_MPC5200 */
293
294#ifdef CONFIG_PS2MULT
295 ps2mult_early_init();
296#endif /* CONFIG_PS2MULT */
297 return (0);
298}
299#endif /* CONFIG_BOARD_EARLY_INIT_R */
300
301
302int last_stage_init (void)
303{
304 /*
305 * auto scan for really existing devices and re-set chip select
306 * configuration.
307 */
308 u16 save, tmp;
309 int restore;
310
311 /*
312 * Check for SRAM and SRAM size
313 */
314
315 /* save original SRAM content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200317 restore = 1;
318
319 /* write test pattern to SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200321 __asm__ volatile ("sync");
322 /*
323 * Put a different pattern on the data lines: otherwise they may float
324 * long enough to read back what we wrote.
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200327 if (tmp == 0xA5A5)
328 puts ("!! possible error in SRAM detection\n");
329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200331 /* no SRAM at all, disable cs */
332 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
333 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
334 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
335 restore = 0;
336 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200338 /* make sure that we access a mirrored address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200340 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200342 /* SRAM size = 512 kByte */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200344 0x80000);
345 __asm__ volatile ("sync");
346 puts ("SRAM: 512 kB\n");
347 }
348 else
349 puts ("!! possible error in SRAM detection\n");
350 } else {
351 puts ("SRAM: 1 MB\n");
352 }
353 /* restore origianl SRAM content */
354 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200356 __asm__ volatile ("sync");
357 }
358
359 /*
360 * Check for Grafic Controller
361 */
362
363 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200365 restore = 1;
366
367 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200369 __asm__ volatile ("sync");
370 /*
371 * Put a different pattern on the data lines: otherwise they may float
372 * long enough to read back what we wrote.
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200375 if (tmp == 0xA5A5)
376 puts ("!! possible error in grafic controller detection\n");
377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200379 /* no grafic controller at all, disable cs */
380 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
381 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
382 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
383 restore = 0;
384 __asm__ volatile ("sync");
385 } else {
386 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
387 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200388 /* restore origianl FB content */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200389 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200391 __asm__ volatile ("sync");
392 }
393
394 return 0;
395}
396
397#ifdef CONFIG_VIDEO_SM501
398
Wolfgang Denk610cf362006-05-03 01:24:04 +0200399#define DISPLAY_WIDTH 640
400#define DISPLAY_HEIGHT 480
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200401
402#ifdef CONFIG_VIDEO_SM501_8BPP
403#error CONFIG_VIDEO_SM501_8BPP not supported.
404#endif /* CONFIG_VIDEO_SM501_8BPP */
405
406#ifdef CONFIG_VIDEO_SM501_16BPP
407#error CONFIG_VIDEO_SM501_16BPP not supported.
408#endif /* CONFIG_VIDEO_SM501_16BPP */
409
410#ifdef CONFIG_VIDEO_SM501_32BPP
411static const SMI_REGS init_regs [] =
412{
413#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
414 /* FP only */
415 {0x00004, 0x0},
416 {0x00048, 0x00021807},
417 {0x0004C, 0x091a0a01},
418 {0x00054, 0x1},
419 {0x00040, 0x00021807},
420 {0x00044, 0x091a0a01},
421 {0x00054, 0x0},
422 {0x80000, 0x01013106},
423 {0x80004, 0xc428bb17},
424 {0x80000, 0x03013106},
425 {0x8000C, 0x00000000},
426 {0x80010, 0x0a000a00},
427 {0x80014, 0x02800000},
428 {0x80018, 0x01e00000},
429 {0x8001C, 0x00000000},
430 {0x80020, 0x01e00280},
431 {0x80024, 0x02fa027f},
432 {0x80028, 0x004a028b},
433 {0x8002C, 0x020c01df},
434 {0x80030, 0x000201e9},
435 {0x80200, 0x00010200},
436 {0x80000, 0x0f013106},
437#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
438 /* CRT only */
439 {0x00004, 0x0},
440 {0x00048, 0x00021807},
441 {0x0004C, 0x10090a01},
442 {0x00054, 0x1},
443 {0x00040, 0x00021807},
444 {0x00044, 0x10090a01},
445 {0x00054, 0x0},
446 {0x80200, 0x00010000},
447 {0x80204, 0x0},
448 {0x80208, 0x0A000A00},
449 {0x8020C, 0x02fa027f},
450 {0x80210, 0x004a028b},
451 {0x80214, 0x020c01df},
452 {0x80218, 0x000201e9},
453 {0x80200, 0x00013306},
454#else /* panel + CRT */
455 {0x00004, 0x0},
456 {0x00048, 0x00021807},
457 {0x0004C, 0x091a0a01},
458 {0x00054, 0x1},
459 {0x00040, 0x00021807},
460 {0x00044, 0x091a0a01},
461 {0x00054, 0x0},
462 {0x80000, 0x0f013106},
463 {0x80004, 0xc428bb17},
464 {0x8000C, 0x00000000},
465 {0x80010, 0x0a000a00},
466 {0x80014, 0x02800000},
467 {0x80018, 0x01e00000},
468 {0x8001C, 0x00000000},
469 {0x80020, 0x01e00280},
470 {0x80024, 0x02fa027f},
471 {0x80028, 0x004a028b},
472 {0x8002C, 0x020c01df},
473 {0x80030, 0x000201e9},
474 {0x80200, 0x00010000},
475#endif
476 {0, 0}
477};
478#endif /* CONFIG_VIDEO_SM501_32BPP */
479
480#ifdef CONFIG_CONSOLE_EXTRA_INFO
481/*
482 * Return text to be printed besides the logo.
483 */
484void video_get_info_str (int line_number, char *info)
485{
486 if (line_number == 1) {
487#if defined (CONFIG_TQM5200)
488 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
489#else
490#error No supported board selected
491#endif /* CONFIG_TQM5200 */
492
493#if defined (CONFIG_BC3450)
494 } else if (line_number == 2) {
495 strcpy (info, " Dev: GERSYS BC3450");
496#endif /* CONFIG_BC3450 */
497 }
498 else {
499 info [0] = '\0';
500 }
501}
502#endif
503
504/*
505 * Returns SM501 register base address. First thing called in the
506 * driver. Checks if SM501 is physically present.
507 */
508unsigned int board_video_init (void)
509{
510 u16 save, tmp;
511 int restore, ret;
512
513 /*
514 * Check for Grafic Controller
515 */
516
517 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200519 restore = 1;
520
521 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200523 __asm__ volatile ("sync");
524 /*
525 * Put a different pattern on the data lines: otherwise they may float
526 * long enough to read back what we wrote.
527 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200529 if (tmp == 0xA5A5)
530 puts ("!! possible error in grafic controller detection\n");
531
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200533 /* no grafic controller found */
534 restore = 0;
535 ret = 0;
536 } else {
537 ret = SM501_MMIO_BASE;
538 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200539
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200540 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200542 __asm__ volatile ("sync");
543 }
544 return ret;
545}
546
547/*
548 * Returns SM501 framebuffer address
549 */
550unsigned int board_video_get_fb (void)
551{
552 return SM501_FB_BASE;
553}
554
555/*
556 * Called after initializing the SM501 and before clearing the screen.
557 */
558void board_validate_screen (unsigned int base)
559{
560}
561
562/*
563 * Return a pointer to the initialization sequence.
564 */
565const SMI_REGS *board_get_regs (void)
566{
567 return init_regs;
568}
569
570int board_get_width (void)
571{
572 return DISPLAY_WIDTH;
573}
574
575int board_get_height (void)
576{
577 return DISPLAY_HEIGHT;
578}
579
580#endif /* CONFIG_VIDEO_SM501 */
Ben Warren19403632008-08-31 10:03:22 -0700581
582int board_eth_init(bd_t *bis)
583{
Ben Warrene1d74802008-08-31 10:39:12 -0700584 cpu_eth_init(bis); /* Built in FEC comes first */
Ben Warren19403632008-08-31 10:03:22 -0700585 return pci_eth_init(bis);
586}