| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 |
| 4 | * Graeme Russ, <graeme.russ@gmail.com> |
| Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 5 | */ |
| Bin Meng | c17ca6b | 2015-08-13 00:29:10 -0700 | [diff] [blame] | 6 | |
| Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 7 | #include <common.h> |
| Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 8 | #include <linux/errno.h> |
| Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 9 | #include <asm/mtrr.h> |
| Graeme Russ | d47ab0e | 2011-12-23 16:51:29 +1100 | [diff] [blame] | 10 | |
| 11 | DECLARE_GLOBAL_DATA_PTR; |
| 12 | |
| Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 13 | int init_cache_f_r(void) |
| 14 | { |
| Simon Glass | cc2d27d | 2019-09-25 08:56:49 -0600 | [diff] [blame^] | 15 | bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || |
| 16 | IS_ENABLED(CONFIG_FSP_VERSION2); |
| Simon Glass | db55bd7 | 2015-01-01 16:18:11 -0700 | [diff] [blame] | 17 | int ret; |
| 18 | |
| Simon Glass | cc2d27d | 2019-09-25 08:56:49 -0600 | [diff] [blame^] | 19 | do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) && |
| 20 | !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER); |
| 21 | |
| 22 | if (do_mtrr) { |
| 23 | ret = mtrr_commit(false); |
| 24 | /* |
| 25 | * If MTRR MSR is not implemented by the processor, just ignore |
| 26 | * it |
| 27 | */ |
| 28 | if (ret && ret != -ENOSYS) |
| 29 | return ret; |
| 30 | } |
| 31 | |
| Graeme Russ | a1d57b7 | 2011-12-23 21:14:22 +1100 | [diff] [blame] | 32 | /* Initialise the CPU cache(s) */ |
| 33 | return init_cache(); |
| 34 | } |