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Peter Crosthwaite9757b652014-08-28 21:16:39 +10001/*
2 * Digilent ZYBO board DTS
3 *
Michal Simek999667c2015-07-22 11:12:10 +02004 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
Peter Crosthwaite9757b652014-08-28 21:16:39 +10006 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
Michal Simek999667c2015-07-22 11:12:10 +020013 model = "Zynq ZYBO Development Board";
14 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100015
16 aliases {
Michal Simek999667c2015-07-22 11:12:10 +020017 ethernet0 = &gem0;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100018 serial0 = &uart1;
Nathan Rossi7bbf8252015-12-09 00:44:42 +100019 spi0 = &qspi;
Michal Simek86472192015-12-08 11:56:23 +010020 mmc0 = &sdhci0;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100021 };
22
Michal Simekcc7978b2016-11-11 13:11:37 +010023 memory@0 {
Peter Crosthwaite9757b652014-08-28 21:16:39 +100024 device_type = "memory";
Michal Simek999667c2015-07-22 11:12:10 +020025 reg = <0x0 0x20000000>;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100026 };
Michal Simek999667c2015-07-22 11:12:10 +020027
28 chosen {
Michal Simek936bbc52016-04-07 11:15:00 +020029 bootargs = "";
Michal Simek999667c2015-07-22 11:12:10 +020030 stdout-path = "serial0:115200n8";
31 };
32
Nathan Rossi7bbf8252015-12-09 00:44:42 +100033 usb_phy0: phy0 {
Michal Simekbaec7df2016-02-13 10:38:08 +010034 compatible = "usb-nop-xceiv";
Michal Simeka195ed32016-04-07 14:42:53 +020035 #phy-cells = <0>;
Michal Simekbaec7df2016-02-13 10:38:08 +010036 reset-gpios = <&gpio0 46 1>;
Nathan Rossi7bbf8252015-12-09 00:44:42 +100037 };
Michal Simek999667c2015-07-22 11:12:10 +020038};
39
40&clkc {
41 ps-clk-frequency = <50000000>;
42};
43
44&gem0 {
45 status = "okay";
46 phy-mode = "rgmii-id";
47 phy-handle = <&ethernet_phy>;
48
49 ethernet_phy: ethernet-phy@0 {
50 reg = <0>;
51 };
52};
53
Michal Simeka95d54b2016-04-07 13:04:15 +020054&qspi {
55 u-boot,dm-pre-reloc;
56 status = "okay";
57};
58
Michal Simek999667c2015-07-22 11:12:10 +020059&sdhci0 {
Michal Simek86472192015-12-08 11:56:23 +010060 u-boot,dm-pre-reloc;
Michal Simek999667c2015-07-22 11:12:10 +020061 status = "okay";
62};
63
64&uart1 {
Simon Glass035c6b22015-10-17 19:41:24 -060065 u-boot,dm-pre-reloc;
Michal Simek999667c2015-07-22 11:12:10 +020066 status = "okay";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100067};
Nathan Rossi7bbf8252015-12-09 00:44:42 +100068
Nathan Rossi7bbf8252015-12-09 00:44:42 +100069&usb0 {
70 status = "okay";
71 dr_mode = "host";
72 usb-phy = <&usb_phy0>;
73};