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Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +02001/*
2 * LPC32xx I2C interface driver
3 *
Sylvain Lemieux1933af12015-08-04 17:04:41 -04004 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +02005 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <asm/io.h>
12#include <i2c.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020014#include <asm/arch/clk.h>
15
16/*
17 * Provide default speed and slave if target did not
18 */
19
20#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
21#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
22#endif
23
24#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
25#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
26#endif
27
28/* i2c register set */
29struct lpc32xx_i2c_registers {
30 union {
31 u32 rx;
32 u32 tx;
33 };
34 u32 stat;
35 u32 ctrl;
36 u32 clk_hi;
37 u32 clk_lo;
38 u32 adr;
39 u32 rxfl;
40 u32 txfl;
41 u32 rxb;
42 u32 txb;
43 u32 stx;
44 u32 stxfl;
45};
46
47/* TX register fields */
48#define LPC32XX_I2C_TX_START 0x00000100
49#define LPC32XX_I2C_TX_STOP 0x00000200
50
51/* Control register values */
52#define LPC32XX_I2C_SOFT_RESET 0x00000100
53
54/* Status register values */
55#define LPC32XX_I2C_STAT_TFF 0x00000400
56#define LPC32XX_I2C_STAT_RFE 0x00000200
57#define LPC32XX_I2C_STAT_DRMI 0x00000008
58#define LPC32XX_I2C_STAT_NAI 0x00000004
59#define LPC32XX_I2C_STAT_TDI 0x00000001
60
61static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {
62 (struct lpc32xx_i2c_registers *)I2C1_BASE,
Sylvain Lemieux1933af12015-08-04 17:04:41 -040063 (struct lpc32xx_i2c_registers *)I2C2_BASE,
64 (struct lpc32xx_i2c_registers *)(USB_BASE + 0x300)
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020065};
66
67/* Set I2C bus speed */
68static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,
69 unsigned int speed)
70{
71 int half_period;
72
73 if (speed == 0)
74 return -EINVAL;
75
Vladimir Zapolskiyea16c6a2015-08-12 20:22:13 +030076 /* OTG I2C clock source and CLK registers are different */
77 if (adap->hwadapnr == 2) {
78 half_period = (get_periph_clk_rate() / speed) / 2;
79 if (half_period > 0xFF)
80 return -EINVAL;
81 } else {
82 half_period = (get_hclk_clk_rate() / speed) / 2;
83 if (half_period > 0x3FF)
84 return -EINVAL;
85 }
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +020086
87 writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
88 writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
89 return 0;
90}
91
92/* I2C init called by cmd_i2c when doing 'i2c reset'. */
93static void _i2c_init(struct i2c_adapter *adap,
94 int requested_speed, int slaveadd)
95{
96 struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
97
98 /* soft reset (auto-clears) */
99 writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
Vladimir Zapolskiyea16c6a2015-08-12 20:22:13 +0300100 /* set HI and LO periods for half of the default speed */
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200101 lpc32xx_i2c_set_bus_speed(adap, requested_speed);
102}
103
104/* I2C probe called by cmd_i2c when doing 'i2c probe'. */
105static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev)
106{
107 struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
108 int stat;
109
110 /* Soft-reset the controller */
111 writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
112 while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
113 ;
114 /* Addre slave for write with start before and stop after */
115 writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,
116 &i2c->tx);
117 /* wait for end of transation */
118 while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
119 ;
120 /* was there no acknowledge? */
121 return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;
122}
123
124/*
125 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
126 * Begin write, send address byte(s), begin read, receive data bytes, end.
127 */
128static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
129 int alen, u8 *data, int length)
130{
131 struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
132 int stat, wlen;
133
134 /* Soft-reset the controller */
135 writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
136 while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
137 ;
138 /* do we need to write an address at all? */
139 if (alen) {
140 /* Address slave in write mode */
141 writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
142 /* write address bytes */
143 while (alen--) {
144 /* compute address byte + stop for the last one */
145 int a = (addr >> (8 * alen)) & 0xff;
146 if (!alen)
147 a |= LPC32XX_I2C_TX_STOP;
148 /* Send address byte */
149 writel(a, &i2c->tx);
150 }
151 /* wait for end of transation */
152 while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
153 ;
154 /* clear end-of-transaction flag */
155 writel(1, &i2c->stat);
156 }
157 /* do we have to read data at all? */
158 if (length) {
159 /* Address slave in read mode */
160 writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
161 wlen = length;
162 /* get data */
163 while (length | wlen) {
164 /* read status for TFF and RFE */
165 stat = readl(&i2c->stat);
166 /* must we, can we write a trigger byte? */
167 if ((wlen > 0)
168 & (!(stat & LPC32XX_I2C_STAT_TFF))) {
169 wlen--;
170 /* write trigger byte + stop if last */
171 writel(wlen ? 0 :
172 LPC32XX_I2C_TX_STOP, &i2c->tx);
173 }
174 /* must we, can we read a data byte? */
175 if ((length > 0)
176 & (!(stat & LPC32XX_I2C_STAT_RFE))) {
177 length--;
178 /* read byte */
179 *(data++) = readl(&i2c->rx);
180 }
181 }
Sylvain Lemieux3d2b6a22015-07-27 13:37:38 -0400182 /* wait for end of transation */
183 while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
184 ;
185 /* clear end-of-transaction flag */
186 writel(1, &i2c->stat);
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200187 }
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200188 /* success */
189 return 0;
190}
191
192/*
193 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
194 * Begin write, send address byte(s), send data bytes, end.
195 */
196static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
197 int alen, u8 *data, int length)
198{
199 struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
200 int stat;
201
202 /* Soft-reset the controller */
203 writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
204 while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)
205 ;
206 /* do we need to write anything at all? */
207 if (alen | length)
208 /* Address slave in write mode */
209 writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
Sylvain Lemieux58243002015-07-27 13:37:39 -0400210 else
211 return 0;
Albert ARIBAUD \(3ADEV\)5e862b92015-03-31 11:40:45 +0200212 /* write address bytes */
213 while (alen) {
214 /* wait for transmit fifo not full */
215 stat = readl(&i2c->stat);
216 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
217 alen--;
218 int a = (addr >> (8 * alen)) & 0xff;
219 if (!(alen | length))
220 a |= LPC32XX_I2C_TX_STOP;
221 /* Send address byte */
222 writel(a, &i2c->tx);
223 }
224 }
225 while (length) {
226 /* wait for transmit fifo not full */
227 stat = readl(&i2c->stat);
228 if (!(stat & LPC32XX_I2C_STAT_TFF)) {
229 /* compute data byte, add stop if length==0 */
230 length--;
231 int d = *(data++);
232 if (!length)
233 d |= LPC32XX_I2C_TX_STOP;
234 /* Send data byte */
235 writel(d, &i2c->tx);
236 }
237 }
238 /* wait for end of transation */
239 while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
240 ;
241 /* clear end-of-transaction flag */
242 writel(1, &i2c->stat);
243 return 0;
244}
245
246U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,
247 lpc32xx_i2c_read, lpc32xx_i2c_write,
248 lpc32xx_i2c_set_bus_speed,
249 CONFIG_SYS_I2C_LPC32XX_SPEED,
250 CONFIG_SYS_I2C_LPC32XX_SLAVE,
251 0)
252
253U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,
254 lpc32xx_i2c_read, lpc32xx_i2c_write,
255 lpc32xx_i2c_set_bus_speed,
256 CONFIG_SYS_I2C_LPC32XX_SPEED,
257 CONFIG_SYS_I2C_LPC32XX_SLAVE,
258 1)
Sylvain Lemieux1933af12015-08-04 17:04:41 -0400259
260U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2, _i2c_init, NULL,
261 lpc32xx_i2c_read, lpc32xx_i2c_write,
262 lpc32xx_i2c_set_bus_speed,
263 100000,
264 0,
265 2)