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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / cd5b2b9941d5b6f6596787ebdb03c215d91fc44d / . / board / uc100 / uc100.c
blob: 6fc68e5cc3c4f3d8715ccbeadb354ae2e493be3f [file] [log] [blame]
wdenkf7d15722004-12-18 22:35:43 +0000[diff] [blame]1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#if 0
25#define DEBUG
26#endif
27
28#include <common.h>
29#include <mpc8xx.h>
30#include <i2c.h>
stroesecd5b2b92005-07-05 11:35:27 +0000[diff] [blame^]31#include <miiphy.h>
wdenkf7d15722004-12-18 22:35:43 +0000[diff] [blame]32
33
34/*********************************************************************/
35/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
36/*********************************************************************/
37const uint sdram_init_upm_table[] = {
38 /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
39 /* NOP - Precharge - AutoRefr - NOP - NOP */
40 /* NOP - AutoRefr - NOP */
41 /* NOP - NOP - LoadModeR - NOP - Active */
42 /* Position of Single Read */
43 0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
44 0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
45
46 /* Burst Read. (offset 8 in UPMA RAM) */
47 /* Cycle lent for Initialisation WV */
48 0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
49 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
50 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
51
52 /* Single Write. (offset 18 in UPMA RAM) */
53 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
54 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
55
56 /* Burst Write. (offset 20 in UPMA RAM) */
57 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
58 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
59 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
60
61 /* Refresh (offset 30 in UPMA RAM) */
62 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
63 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
64 0xFFFFFFFF, 0xFFFFFFFF,
65
66 /* Exception. (offset 3c in UPMA RAM) */
67 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
68};
69
70/*********************************************************************/
71/* UPMA initilization table. */
72/*********************************************************************/
73const uint sdram_upm_table[] = {
74 /* single read. (offset 0 in UPMA RAM) */
75 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
76 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
77
78 /* Burst Read. (offset 8 in UPMA RAM) */
79 0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
80 0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
81 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
82
83 /* Single Write. (offset 18 in UPMA RAM) */
84 0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
85 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
86
87 /* Burst Write. (offset 20 in UPMA RAM) */
88 0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
89 0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
90 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
91
92 /* Refresh (offset 30 in UPMA RAM) */
93 0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
94 0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
95 0xFFFFFFFF, 0xFFFFFFFF,
96
97 /* Exception. (offset 3c in UPMA RAM) */
98 0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
99};
100
101/*********************************************************************/
102/* UPMB initilization table. */
103/*********************************************************************/
104const uint mpm_upm_table[] = {
105 /* single read. (offset 0 in upm RAM) */
106 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
107 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
108
109 /* burst read. (Offset 8 in upm RAM) */
110 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
111 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
112 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
113 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
114
115 /* single write. (Offset 0x18 in upm RAM) */
116 0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
117 0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
118
119 /* burst write. (Offset 0x20 in upm RAM) */
120 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
121 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
122 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
123 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
124
125 /* Refresh cycle, offset 0x30 */
126 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
127 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
128 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
129
130 /* Exception, 0ffset 0x3C */
131 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
132};
133
134
135int board_switch(void)
136{
137 volatile pcmconf8xx_t *pcmp;
138
139 pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
140
141 return ((pcmp->pcmc_pipr >> 24) & 0xf);
142}
143
144
145/*
146 * Check Board Identity:
147 */
148int checkboard (void)
149{
150 unsigned char str[64];
151 int i = getenv_r ("serial#", str, sizeof(str));
152
153 puts ("Board: ");
154
155 if (i == -1) {
156 puts ("### No HW ID - assuming UC100");
157 } else {
158 puts(str);
159 }
160
161 printf (" (SWITCH=%1X)\n", board_switch());
162
163 return 0;
164}
165
166
167/*
168 * Initialize SDRAM
169 */
170long int initdram (int board_type)
171{
172 volatile immap_t *immap = (immap_t *) CFG_IMMR;
173 volatile memctl8xx_t *memctl = &immap->im_memctl;
174
175 /*---------------------------------------------------------------------*/
176 /* Initialize the UPMA/UPMB registers with the appropriate table. */
177 /*---------------------------------------------------------------------*/
178 upmconfig (UPMA, (uint *) sdram_init_upm_table,
179 sizeof (sdram_init_upm_table) / sizeof (uint));
180 upmconfig (UPMB, (uint *) mpm_upm_table,
181 sizeof (mpm_upm_table) / sizeof (uint));
182
183 /*---------------------------------------------------------------------*/
184 /* Memory Periodic Timer Prescaler: divide by 16 */
185 /*---------------------------------------------------------------------*/
186 memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
187
188 memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
189 memctl->memc_mbmr = CFG_MBMR_VAL;
190
191 /*---------------------------------------------------------------------*/
192 /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
193 /* for SDRAM */
194 /* */
195 /* NOTE: The refresh rate in MAMR reg is set according to the lowest */
196 /* clock rate (16.67MHz) to allow proper operation for all ADS */
197 /* clock frequencies. */
198 /*---------------------------------------------------------------------*/
199 memctl->memc_or1 = CFG_OR1_PRELIM;
200 memctl->memc_br1 = CFG_BR1_PRELIM;
201
202 /*-------------------------------------------------------------------*/
203 /* Wait at least 200 usec for DRAM to stabilize, this magic number */
204 /* obtained from the init code. */
205 /*-------------------------------------------------------------------*/
206 udelay(200);
207
208 memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
209
210 memctl->memc_br1 = CFG_BR1_PRELIM;
211 memctl->memc_or1 = CFG_OR1_PRELIM;
212
213 /*---------------------------------------------------------------------*/
214 /* run MRS command in location 5-8 of UPMB. */
215 /*---------------------------------------------------------------------*/
216 memctl->memc_mar = 0x88;
217 /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
218
219 memctl->memc_mcr = 0x80002100;
220 /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
221
222 udelay(200);
223
224 /*---------------------------------------------------------------------*/
225 /* Initialisation for normal access WV */
226 /*---------------------------------------------------------------------*/
227
228 /*---------------------------------------------------------------------*/
229 /* Initialize the UPMA register with the appropriate table. */
230 /*---------------------------------------------------------------------*/
231 upmconfig (UPMA, (uint *) sdram_upm_table,
232 sizeof (sdram_upm_table) / sizeof (uint));
233
234 /*---------------------------------------------------------------------*/
235 /* rerstore MBMR value (4-beat refresh burst.) */
236 /*---------------------------------------------------------------------*/
237 memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
238
239 udelay(200);
240
241 return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
242}
243
244
245int misc_init_r (void)
246{
247 uchar val;
248
249 /*
250 * Make sure that RTC has clock output enabled (triggers watchdog!)
251 */
252 val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
253 val |= 0x80;
254 i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
255
stroesecd5b2b92005-07-05 11:35:27 +0000[diff] [blame^]256 /*
257 * Configure PHY to setup LED's correctly and use 100MBit, FD
258 */
259 mii_init();
260
261 miiphy_write(0, PHY_BMCR, 0x2100); /* disable auto-negotiation, 100mbit, full-duplex */
262 miiphy_write(0, PHY_FCSCR, 0x4122); /* set LED's to Link, Transmit, Receive */
263
wdenkf7d15722004-12-18 22:35:43 +0000[diff] [blame]264 return 0;
265}
266
267
268#ifdef CONFIG_POST
269/*
270 * Returns 1 if keys pressed to start the power-on long-running tests
271 * Called from board_init_f().
272 */
273int post_hotkeys_pressed (void)
274{
275 return 0; /* No hotkeys supported */
276}
277#endif