blob: d4612d3527e08dc0fb7d4c1bf1c54ea6520f991a [file] [log] [blame]
Sekhar Nori8ed58852010-01-27 11:10:40 -05001/*
2 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Register definitions for the DaVinci SPI Controller
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Sekhar Nori8ed58852010-01-27 11:10:40 -05007 */
8
9#ifndef _DAVINCI_SPI_H_
10#define _DAVINCI_SPI_H_
11
12struct davinci_spi_regs {
13 dv_reg gcr0; /* 0x00 */
14 dv_reg gcr1; /* 0x04 */
15 dv_reg int0; /* 0x08 */
16 dv_reg lvl; /* 0x0c */
17 dv_reg flg; /* 0x10 */
18 dv_reg pc0; /* 0x14 */
19 dv_reg pc1; /* 0x18 */
20 dv_reg pc2; /* 0x1c */
21 dv_reg pc3; /* 0x20 */
22 dv_reg pc4; /* 0x24 */
23 dv_reg pc5; /* 0x28 */
24 dv_reg rsvd[3];
25 dv_reg dat0; /* 0x38 */
26 dv_reg dat1; /* 0x3c */
27 dv_reg buf; /* 0x40 */
28 dv_reg emu; /* 0x44 */
29 dv_reg delay; /* 0x48 */
30 dv_reg def; /* 0x4c */
31 dv_reg fmt0; /* 0x50 */
32 dv_reg fmt1; /* 0x54 */
33 dv_reg fmt2; /* 0x58 */
34 dv_reg fmt3; /* 0x5c */
35 dv_reg intvec0; /* 0x60 */
36 dv_reg intvec1; /* 0x64 */
37};
38
39#define BIT(x) (1 << (x))
40
41/* SPIGCR0 */
42#define SPIGCR0_SPIENA_MASK 0x1
43#define SPIGCR0_SPIRST_MASK 0x0
44
45/* SPIGCR0 */
46#define SPIGCR1_CLKMOD_MASK BIT(1)
47#define SPIGCR1_MASTER_MASK BIT(0)
48#define SPIGCR1_SPIENA_MASK BIT(24)
49
50/* SPIPC0 */
51#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
52#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
53#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
54#define SPIPC0_EN0FUN_MASK BIT(0)
55
56/* SPIFMT0 */
57#define SPIFMT_SHIFTDIR_SHIFT 20
58#define SPIFMT_POLARITY_SHIFT 17
59#define SPIFMT_PHASE_SHIFT 16
60#define SPIFMT_PRESCALE_SHIFT 8
61
62/* SPIDAT1 */
63#define SPIDAT1_CSHOLD_SHIFT 28
64#define SPIDAT1_CSNR_SHIFT 16
65
66/* SPIDELAY */
67#define SPI_C2TDELAY_SHIFT 24
68#define SPI_T2CDELAY_SHIFT 16
69
70/* SPIBUF */
71#define SPIBUF_RXEMPTY_MASK BIT(31)
72#define SPIBUF_TXFULL_MASK BIT(29)
73
74/* SPIDEF */
75#define SPIDEF_CSDEF0_MASK BIT(0)
76
Karicheri, Muralidharan2bcdf842014-04-04 13:16:54 -040077#define SPI0_BUS 0
78#define SPI0_BASE CONFIG_SYS_SPI_BASE
79/*
80 * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
81 * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
82 * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
83 */
84#ifndef CONFIG_SYS_SPI0
85#define SPI0_NUM_CS 1
86#else
87#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS
88#endif
89
90/*
91 * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
92 * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
93 */
94#ifdef CONFIG_SYS_SPI1
95#define SPI1_BUS 1
96#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS
97#define SPI1_BASE CONFIG_SYS_SPI1_BASE
98#endif
99
100/*
101 * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
102 * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
103 */
104#ifdef CONFIG_SYS_SPI2
105#define SPI2_BUS 2
106#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS
107#define SPI2_BASE CONFIG_SYS_SPI2_BASE
108#endif
109
Sekhar Nori8ed58852010-01-27 11:10:40 -0500110struct davinci_spi_slave {
111 struct spi_slave slave;
112 struct davinci_spi_regs *regs;
113 unsigned int freq;
114};
115
116static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
117{
118 return container_of(slave, struct davinci_spi_slave, slave);
119}
120
121#endif /* _DAVINCI_SPI_H_ */