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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / cfad2878b43fd90dd7a2ed68e584580a0831082e / . / dts / upstream / Bindings / usb / qcom,dwc3.yaml
blob: efde47a5b145565d1bd6cbe1d96196ce873fef77 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10 - Wesley Cheng <quic_wcheng@quicinc.com>
11
12properties:
13 compatible:
14 items:
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
21 - qcom,ipq8074-dwc3
22 - qcom,ipq9574-dwc3
23 - qcom,msm8953-dwc3
24 - qcom,msm8994-dwc3
25 - qcom,msm8996-dwc3
26 - qcom,msm8998-dwc3
27 - qcom,qcm2290-dwc3
28 - qcom,qcs404-dwc3
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]29 - qcom,qdu1000-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]30 - qcom,sa8775p-dwc3
31 - qcom,sc7180-dwc3
32 - qcom,sc7280-dwc3
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]33 - qcom,sc8180x-dwc3
34 - qcom,sc8180x-dwc3-mp
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]35 - qcom,sc8280xp-dwc3
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]36 - qcom,sc8280xp-dwc3-mp
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]37 - qcom,sdm660-dwc3
38 - qcom,sdm670-dwc3
39 - qcom,sdm845-dwc3
40 - qcom,sdx55-dwc3
41 - qcom,sdx65-dwc3
42 - qcom,sdx75-dwc3
43 - qcom,sm4250-dwc3
44 - qcom,sm6115-dwc3
45 - qcom,sm6125-dwc3
46 - qcom,sm6350-dwc3
47 - qcom,sm6375-dwc3
48 - qcom,sm8150-dwc3
49 - qcom,sm8250-dwc3
50 - qcom,sm8350-dwc3
51 - qcom,sm8450-dwc3
52 - qcom,sm8550-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]53 - qcom,sm8650-dwc3
54 - qcom,x1e80100-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]55 - const: qcom,dwc3
56
57 reg:
58 description: Offset and length of register set for QSCRATCH wrapper
59 maxItems: 1
60
61 "#address-cells":
62 enum: [ 1, 2 ]
63
64 "#size-cells":
65 enum: [ 1, 2 ]
66
67 ranges: true
68
69 power-domains:
70 description: specifies a phandle to PM domain provider node
71 maxItems: 1
72
73 required-opps:
74 maxItems: 1
75
76 clocks:
77 description: |
78 Several clocks are used, depending on the variant. Typical ones are::
79 - cfg_noc:: System Config NOC clock.
80 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
81 60MHz for HS operation.
82 - iface:: System bus AXI clock.
83 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
84 power mode (U3).
85 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
86 mode. Its frequency should be 19.2MHz.
87 minItems: 1
88 maxItems: 9
89
90 clock-names:
91 minItems: 1
92 maxItems: 9
93
94 resets:
95 maxItems: 1
96
97 interconnects:
98 maxItems: 2
99
100 interconnect-names:
101 items:
102 - const: usb-ddr
103 - const: apps-usb
104
105 interrupts:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]106 description: |
107 Different types of interrupts are used based on HS PHY used on target:
108 - pwr_event: Used for wakeup based on other power events.
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]109 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]110 hs_phy_irq which is not triggered by default and its
111 functionality is mutually exclusive to that of
112 {dp/dm}_hs_phy_irq and qusb2_phy_irq.
113 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
114 expose only a single IRQ whose behavior can be modified
115 by the QUSB2PHY_INTR_CTRL register. The required DPSE/
116 DMSE configuration is done in QUSB2PHY_INTR_CTRL register
117 of PHY address space.
118 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
119 DM pads of the SoC. These are used for wakeup
120 only on SoCs with non-QUSB2 targets with
121 exception of SDM670/SDM845/SM6350.
122 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
123 minItems: 2
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]124 maxItems: 18
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]125
126 interrupt-names:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]127 minItems: 2
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]128 maxItems: 18
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]129
130 qcom,select-utmi-as-pipe-clk:
131 description:
132 If present, disable USB3 pipe_clk requirement.
133 Used when dwc3 operates without SSPHY and only
134 HS/FS/LS modes are supported.
135 type: boolean
136
137 wakeup-source: true
138
139# Required child node:
140
141patternProperties:
142 "^usb@[0-9a-f]+$":
143 $ref: snps,dwc3.yaml#
144 unevaluatedProperties: false
145
146 properties:
147 wakeup-source: false
148
149required:
150 - compatible
151 - reg
152 - "#address-cells"
153 - "#size-cells"
154 - ranges
155 - clocks
156 - clock-names
157 - interrupts
158 - interrupt-names
159
160allOf:
161 - if:
162 properties:
163 compatible:
164 contains:
165 enum:
166 - qcom,ipq4019-dwc3
167 then:
168 properties:
169 clocks:
170 maxItems: 3
171 clock-names:
172 items:
173 - const: core
174 - const: sleep
175 - const: mock_utmi
176
177 - if:
178 properties:
179 compatible:
180 contains:
181 enum:
182 - qcom,ipq8064-dwc3
183 then:
184 properties:
185 clocks:
186 items:
187 - description: Master/Core clock, has to be >= 125 MHz
188 for SS operation and >= 60MHz for HS operation.
189 clock-names:
190 items:
191 - const: core
192
193 - if:
194 properties:
195 compatible:
196 contains:
197 enum:
198 - qcom,ipq9574-dwc3
199 - qcom,msm8953-dwc3
200 - qcom,msm8996-dwc3
201 - qcom,msm8998-dwc3
202 - qcom,sa8775p-dwc3
203 - qcom,sc7180-dwc3
204 - qcom,sc7280-dwc3
205 - qcom,sdm670-dwc3
206 - qcom,sdm845-dwc3
207 - qcom,sdx55-dwc3
208 - qcom,sdx65-dwc3
209 - qcom,sdx75-dwc3
210 - qcom,sm6350-dwc3
211 then:
212 properties:
213 clocks:
214 maxItems: 5
215 clock-names:
216 items:
217 - const: cfg_noc
218 - const: core
219 - const: iface
220 - const: sleep
221 - const: mock_utmi
222
223 - if:
224 properties:
225 compatible:
226 contains:
227 enum:
228 - qcom,ipq6018-dwc3
229 then:
230 properties:
231 clocks:
232 minItems: 3
233 maxItems: 4
234 clock-names:
235 oneOf:
236 - items:
237 - const: core
238 - const: sleep
239 - const: mock_utmi
240 - items:
241 - const: cfg_noc
242 - const: core
243 - const: sleep
244 - const: mock_utmi
245
246 - if:
247 properties:
248 compatible:
249 contains:
250 enum:
251 - qcom,ipq8074-dwc3
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]252 - qcom,qdu1000-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]253 then:
254 properties:
255 clocks:
256 maxItems: 4
257 clock-names:
258 items:
259 - const: cfg_noc
260 - const: core
261 - const: sleep
262 - const: mock_utmi
263
264 - if:
265 properties:
266 compatible:
267 contains:
268 enum:
269 - qcom,ipq5018-dwc3
270 - qcom,ipq5332-dwc3
271 - qcom,msm8994-dwc3
272 - qcom,qcs404-dwc3
273 then:
274 properties:
275 clocks:
276 maxItems: 4
277 clock-names:
278 items:
279 - const: core
280 - const: iface
281 - const: sleep
282 - const: mock_utmi
283
284 - if:
285 properties:
286 compatible:
287 contains:
288 enum:
289 - qcom,sc8280xp-dwc3
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]290 - qcom,sc8280xp-dwc3-mp
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]291 - qcom,x1e80100-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]292 then:
293 properties:
294 clocks:
295 maxItems: 9
296 clock-names:
297 items:
298 - const: cfg_noc
299 - const: core
300 - const: iface
301 - const: sleep
302 - const: mock_utmi
303 - const: noc_aggr
304 - const: noc_aggr_north
305 - const: noc_aggr_south
306 - const: noc_sys
307
308 - if:
309 properties:
310 compatible:
311 contains:
312 enum:
313 - qcom,sdm660-dwc3
314 then:
315 properties:
316 clocks:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]317 minItems: 4
318 maxItems: 5
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]319 clock-names:
320 oneOf:
321 - items:
322 - const: cfg_noc
323 - const: core
324 - const: iface
325 - const: sleep
326 - const: mock_utmi
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]327 - items:
328 - const: cfg_noc
329 - const: core
330 - const: sleep
331 - const: mock_utmi
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]332
333 - if:
334 properties:
335 compatible:
336 contains:
337 enum:
338 - qcom,qcm2290-dwc3
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]339 - qcom,sc8180x-dwc3
340 - qcom,sc8180x-dwc3-mp
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]341 - qcom,sm6115-dwc3
342 - qcom,sm6125-dwc3
343 - qcom,sm8150-dwc3
344 - qcom,sm8250-dwc3
345 - qcom,sm8450-dwc3
346 - qcom,sm8550-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]347 - qcom,sm8650-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]348 then:
349 properties:
350 clocks:
351 minItems: 6
352 clock-names:
353 items:
354 - const: cfg_noc
355 - const: core
356 - const: iface
357 - const: sleep
358 - const: mock_utmi
359 - const: xo
360
361 - if:
362 properties:
363 compatible:
364 contains:
365 enum:
366 - qcom,sm8350-dwc3
367 then:
368 properties:
369 clocks:
370 minItems: 5
371 maxItems: 6
372 clock-names:
373 minItems: 5
374 items:
375 - const: cfg_noc
376 - const: core
377 - const: iface
378 - const: sleep
379 - const: mock_utmi
380 - const: xo
381
382 - if:
383 properties:
384 compatible:
385 contains:
386 enum:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]387 - qcom,ipq5018-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]388 - qcom,ipq6018-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]389 - qcom,ipq8074-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]390 - qcom,msm8953-dwc3
391 - qcom,msm8998-dwc3
392 then:
393 properties:
394 interrupts:
395 minItems: 2
396 maxItems: 3
397 interrupt-names:
398 items:
399 - const: pwr_event
400 - const: qusb2_phy
401 - const: ss_phy_irq
402
403 - if:
404 properties:
405 compatible:
406 contains:
407 enum:
408 - qcom,msm8996-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]409 - qcom,qcs404-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]410 - qcom,sdm660-dwc3
411 - qcom,sm6115-dwc3
412 - qcom,sm6125-dwc3
413 then:
414 properties:
415 interrupts:
416 minItems: 3
417 maxItems: 4
418 interrupt-names:
419 items:
420 - const: pwr_event
421 - const: qusb2_phy
422 - const: hs_phy_irq
423 - const: ss_phy_irq
424
425 - if:
426 properties:
427 compatible:
428 contains:
429 enum:
430 - qcom,ipq5332-dwc3
431 - qcom,x1e80100-dwc3
432 then:
433 properties:
434 interrupts:
435 maxItems: 4
436 interrupt-names:
437 items:
438 - const: pwr_event
439 - const: dp_hs_phy_irq
440 - const: dm_hs_phy_irq
441 - const: ss_phy_irq
442
443 - if:
444 properties:
445 compatible:
446 contains:
447 enum:
448 - qcom,ipq4019-dwc3
449 - qcom,ipq8064-dwc3
450 - qcom,msm8994-dwc3
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]451 - qcom,qdu1000-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]452 - qcom,sa8775p-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]453 - qcom,sc7180-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]454 - qcom,sc7280-dwc3
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]455 - qcom,sc8180x-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]456 - qcom,sc8280xp-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]457 - qcom,sdm670-dwc3
458 - qcom,sdm845-dwc3
459 - qcom,sdx55-dwc3
460 - qcom,sdx65-dwc3
461 - qcom,sdx75-dwc3
462 - qcom,sm4250-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]463 - qcom,sm6350-dwc3
464 - qcom,sm8150-dwc3
465 - qcom,sm8250-dwc3
466 - qcom,sm8350-dwc3
467 - qcom,sm8450-dwc3
468 - qcom,sm8550-dwc3
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]469 - qcom,sm8650-dwc3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]470 then:
471 properties:
472 interrupts:
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]473 minItems: 4
474 maxItems: 5
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]475 interrupt-names:
476 items:
477 - const: pwr_event
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]478 - const: hs_phy_irq
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]479 - const: dp_hs_phy_irq
480 - const: dm_hs_phy_irq
481 - const: ss_phy_irq
482
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]483 - if:
484 properties:
485 compatible:
486 contains:
487 enum:
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]488 - qcom,sc8180x-dwc3-mp
489 then:
490 properties:
491 interrupts:
492 minItems: 10
493 maxItems: 10
494 interrupt-names:
495 items:
496 - const: pwr_event_1
497 - const: pwr_event_2
498 - const: hs_phy_1
499 - const: hs_phy_2
500 - const: dp_hs_phy_1
501 - const: dm_hs_phy_1
502 - const: dp_hs_phy_2
503 - const: dm_hs_phy_2
504 - const: ss_phy_1
505 - const: ss_phy_2
506
507 - if:
508 properties:
509 compatible:
510 contains:
511 enum:
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]512 - qcom,sc8280xp-dwc3-mp
513 then:
514 properties:
515 interrupts:
516 minItems: 18
517 maxItems: 18
518 interrupt-names:
519 items:
520 - const: pwr_event_1
521 - const: pwr_event_2
522 - const: pwr_event_3
523 - const: pwr_event_4
524 - const: hs_phy_1
525 - const: hs_phy_2
526 - const: hs_phy_3
527 - const: hs_phy_4
528 - const: dp_hs_phy_1
529 - const: dm_hs_phy_1
530 - const: dp_hs_phy_2
531 - const: dm_hs_phy_2
532 - const: dp_hs_phy_3
533 - const: dm_hs_phy_3
534 - const: dp_hs_phy_4
535 - const: dm_hs_phy_4
536 - const: ss_phy_1
537 - const: ss_phy_2
538
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]539additionalProperties: false
540
541examples:
542 - |
543 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
544 #include <dt-bindings/interrupt-controller/arm-gic.h>
545 #include <dt-bindings/interrupt-controller/irq.h>
546 soc {
547 #address-cells = <2>;
548 #size-cells = <2>;
549
550 usb@a6f8800 {
551 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
552 reg = <0 0x0a6f8800 0 0x400>;
553
554 #address-cells = <2>;
555 #size-cells = <2>;
556 ranges;
557 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
558 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
559 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
560 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
561 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
562 clock-names = "cfg_noc",
563 "core",
564 "iface",
565 "sleep",
566 "mock_utmi";
567
568 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
569 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
570 assigned-clock-rates = <19200000>, <150000000>;
571
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]572 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>,
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]575 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>,
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]576 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "pwr_event", "hs_phy_irq",
578 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]579
580 power-domains = <&gcc USB30_PRIM_GDSC>;
581
582 resets = <&gcc GCC_USB30_PRIM_BCR>;
583
584 usb@a600000 {
585 compatible = "snps,dwc3";
586 reg = <0 0x0a600000 0 0xcd00>;
587 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
588 iommus = <&apps_smmu 0x740 0>;
589 snps,dis_u2_susphy_quirk;
590 snps,dis_enblslpm_quirk;
591 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
592 phy-names = "usb2-phy", "usb3-phy";
593 };
594 };
595 };