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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
30
31#define SD_VERSION_SD 0x20000
32#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
33#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
34#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
35#define MMC_VERSION_MMC 0x10000
36#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
37#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
38#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
39#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
40#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
41#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
42
43#define MMC_MODE_HS 0x001
44#define MMC_MODE_HS_52MHz 0x010
45#define MMC_MODE_4BIT 0x100
46#define MMC_MODE_8BIT 0x200
47
48#define SD_DATA_4BIT 0x00040000
49
Albin Tonnerre79b91de2009-08-22 14:21:53 +020050#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050051
52#define MMC_DATA_READ 1
53#define MMC_DATA_WRITE 2
54
55#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
56#define UNUSABLE_ERR -17 /* Unusable Card */
57#define COMM_ERR -18 /* Communications Error */
58#define TIMEOUT -19
59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020060#define MMC_CMD_GO_IDLE_STATE 0
61#define MMC_CMD_SEND_OP_COND 1
62#define MMC_CMD_ALL_SEND_CID 2
63#define MMC_CMD_SET_RELATIVE_ADDR 3
64#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050065#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020066#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050067#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020068#define MMC_CMD_SEND_CSD 9
69#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050070#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020071#define MMC_CMD_SEND_STATUS 13
72#define MMC_CMD_SET_BLOCKLEN 16
73#define MMC_CMD_READ_SINGLE_BLOCK 17
74#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050075#define MMC_CMD_WRITE_SINGLE_BLOCK 24
76#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020077#define MMC_CMD_APP_CMD 55
78
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020079#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050080#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020081#define SD_CMD_SEND_IF_COND 8
82
83#define SD_CMD_APP_SET_BUS_WIDTH 6
84#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050085#define SD_CMD_APP_SEND_SCR 51
86
87/* SCR definitions in different words */
88#define SD_HIGHSPEED_BUSY 0x00020000
89#define SD_HIGHSPEED_SUPPORTED 0x00020000
90
91#define MMC_HS_TIMING 0x00000100
92#define MMC_HS_52MHZ 0x2
93
Rabin Vincent0b453ff2009-04-05 13:30:55 +053094#define OCR_BUSY 0x80000000
Andy Fleming272cc702008-10-30 16:41:01 -050095#define OCR_HCS 0x40000000
96
97#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
98#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
99#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
100#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
101#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
102#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
103#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
104#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
105#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
106#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
107#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
108#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
109#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
110#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
111#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
112#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
113#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
114
115#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
116#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
117 addressed by index which are
118 1 in value field */
119#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
120 addressed by index, which are
121 1 in value field */
122#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
123
124#define SD_SWITCH_CHECK 0
125#define SD_SWITCH_SWITCH 1
126
127/*
128 * EXT_CSD fields
129 */
130
131#define EXT_CSD_BUS_WIDTH 183 /* R/W */
132#define EXT_CSD_HS_TIMING 185 /* R/W */
133#define EXT_CSD_CARD_TYPE 196 /* RO */
134#define EXT_CSD_REV 192 /* RO */
135#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
136
137/*
138 * EXT_CSD field definitions
139 */
140
141#define EXT_CSD_CMD_SET_NORMAL (1<<0)
142#define EXT_CSD_CMD_SET_SECURE (1<<1)
143#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
144
145#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */
146#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */
147
148#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
149#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
150#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200151
Andy Fleming1de97f92008-10-30 16:31:39 -0500152#define R1_ILLEGAL_COMMAND (1 << 22)
153#define R1_APP_CMD (1 << 5)
154
Andy Fleming272cc702008-10-30 16:41:01 -0500155#define MMC_RSP_PRESENT (1 << 0)
156#define MMC_RSP_136 (1 << 1) /* 136 bit response */
157#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
158#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
159#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
160
161#define MMC_RSP_NONE (0)
162#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
163#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
164 MMC_RSP_BUSY)
165#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
166#define MMC_RSP_R3 (MMC_RSP_PRESENT)
167#define MMC_RSP_R4 (MMC_RSP_PRESENT)
168#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
169#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
170#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
171
wdenk71f95112003-06-15 22:40:42 +0000172
Andy Fleming1de97f92008-10-30 16:31:39 -0500173struct mmc_cid {
174 unsigned long psn;
175 unsigned short oid;
176 unsigned char mid;
177 unsigned char prv;
178 unsigned char mdt;
179 char pnm[7];
180};
181
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200182/*
183 * WARNING!
184 *
185 * This structure is used by atmel_mci.c only.
186 * It works for the AVR32 architecture but NOT
187 * for ARM/AT91 architectures.
188 * Its use is highly depreciated.
189 * After the atmel_mci.c driver for AVR32 has
190 * been replaced this structure will be removed.
191 */
Andy Fleming1de97f92008-10-30 16:31:39 -0500192struct mmc_csd
193{
194 u8 csd_structure:2,
195 spec_vers:4,
196 rsvd1:2;
197 u8 taac;
198 u8 nsac;
199 u8 tran_speed;
200 u16 ccc:12,
201 read_bl_len:4;
202 u64 read_bl_partial:1,
203 write_blk_misalign:1,
204 read_blk_misalign:1,
205 dsr_imp:1,
206 rsvd2:2,
207 c_size:12,
208 vdd_r_curr_min:3,
209 vdd_r_curr_max:3,
210 vdd_w_curr_min:3,
211 vdd_w_curr_max:3,
212 c_size_mult:3,
213 sector_size:5,
214 erase_grp_size:5,
215 wp_grp_size:5,
216 wp_grp_enable:1,
217 default_ecc:2,
218 r2w_factor:3,
219 write_bl_len:4,
220 write_bl_partial:1,
221 rsvd3:5;
222 u8 file_format_grp:1,
223 copy:1,
224 perm_write_protect:1,
225 tmp_write_protect:1,
226 file_format:2,
227 ecc:2;
228 u8 crc:7;
229 u8 one:1;
230};
231
Andy Fleming272cc702008-10-30 16:41:01 -0500232struct mmc_cmd {
233 ushort cmdidx;
234 uint resp_type;
235 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530236 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500237 uint flags;
238};
239
240struct mmc_data {
241 union {
242 char *dest;
243 const char *src; /* src buffers don't get written to */
244 };
245 uint flags;
246 uint blocks;
247 uint blocksize;
248};
249
250struct mmc {
251 struct list_head link;
252 char name[32];
253 void *priv;
254 uint voltages;
255 uint version;
256 uint f_min;
257 uint f_max;
258 int high_capacity;
259 uint bus_width;
260 uint clock;
261 uint card_caps;
262 uint host_caps;
263 uint ocr;
264 uint scr[2];
265 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530266 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500267 ushort rca;
268 uint tran_speed;
269 uint read_bl_len;
270 uint write_bl_len;
271 u64 capacity;
272 block_dev_desc_t block_dev;
273 int (*send_cmd)(struct mmc *mmc,
274 struct mmc_cmd *cmd, struct mmc_data *data);
275 void (*set_ios)(struct mmc *mmc);
276 int (*init)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500277#ifdef CONFIG_MMC_MBLOCK
278 uint b_max;
279#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500280};
281
282int mmc_register(struct mmc *mmc);
283int mmc_initialize(bd_t *bis);
284int mmc_init(struct mmc *mmc);
285int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000286void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500287struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700288int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500289void print_mmc_devices(char separator);
Stefano Babic11fdade2010-02-05 15:04:43 +0100290int board_mmc_getcd(u8 *cd, struct mmc *mmc);
Andy Fleming272cc702008-10-30 16:41:01 -0500291
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200292#ifdef CONFIG_GENERIC_MMC
293int atmel_mci_init(void *regs);
294#else
Andy Fleming272cc702008-10-30 16:41:01 -0500295int mmc_legacy_init(int verbose);
296#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200297
wdenk71f95112003-06-15 22:40:42 +0000298#endif /* _MMC_H_ */