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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf12e5682003-07-07 20:07:54 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf12e5682003-07-07 20:07:54 +000026#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020027#define CONFIG_SYS_SMC_RXBUFLEN 128
28#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000029#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
30
wdenkae3af052003-08-07 22:18:11 +000031#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000032
wdenkae3af052003-08-07 22:18:11 +000033#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000034
35#define CONFIG_BOARD_TYPES 1 /* support board types */
36
37#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010038 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkf12e5682003-07-07 20:07:54 +000039 "echo"
40
41#undef CONFIG_BOOTARGS
42
43#define CONFIG_EXTRA_ENV_SETTINGS \
44 "netdev=eth0\0" \
45 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010046 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000047 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010048 "addip=setenv bootargs ${bootargs} " \
49 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
50 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000051 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000053 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010054 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
55 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000056 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020057 "hostname=TQM855M\0" \
58 "bootfile=TQM855M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020059 "fdt_addr=40080000\0" \
60 "kernel_addr=400A0000\0" \
61 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020062 "u-boot=TQM855M/u-image.bin\0" \
63 "load=tftp 200000 ${u-boot}\0" \
64 "update=prot off 40000000 +${filesize};" \
65 "era 40000000 +${filesize};" \
66 "cp.b 200000 40000000 ${filesize};" \
67 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000068 ""
69#define CONFIG_BOOTCOMMAND "run flash_self"
70
71#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000073
74#undef CONFIG_WATCHDOG /* watchdog disabled */
75
76#define CONFIG_STATUS_LED 1 /* Status LED enabled */
77
78#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
79
wdenkd4ca31c2004-01-02 14:00:00 +000080/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010081#define CONFIG_SYS_I2C
82#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
83#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
84#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenkd4ca31c2004-01-02 14:00:00 +000085/*
86 * Software (bit-bang) I2C driver configuration
87 */
88#define PB_SCL 0x00000020 /* PB 26 */
89#define PB_SDA 0x00000010 /* PB 27 */
90
91#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
92#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
93#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
94#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
95#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
96 else immr->im_cpm.cp_pbdat &= ~PB_SDA
97#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
98 else immr->im_cpm.cp_pbdat &= ~PB_SCL
99#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
wdenkd4ca31c2004-01-02 14:00:00 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
102#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
wdenkd4ca31c2004-01-02 14:00:00 +0000103#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
105#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
106#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
wdenkd4ca31c2004-01-02 14:00:00 +0000107#endif
108
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500109/*
110 * BOOTP options
111 */
112#define CONFIG_BOOTP_SUBNETMASK
113#define CONFIG_BOOTP_GATEWAY
114#define CONFIG_BOOTP_HOSTNAME
115#define CONFIG_BOOTP_BOOTPATH
116#define CONFIG_BOOTP_BOOTFILESIZE
117
wdenkf12e5682003-07-07 20:07:54 +0000118
119#define CONFIG_MAC_PARTITION
120#define CONFIG_DOS_PARTITION
121
122#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
123
wdenkf12e5682003-07-07 20:07:54 +0000124
Jon Loeliger26946902007-07-04 22:30:50 -0500125/*
126 * Command line configuration.
127 */
Jon Loeliger26946902007-07-04 22:30:50 -0500128#define CONFIG_CMD_ASKENV
129#define CONFIG_CMD_DATE
130#define CONFIG_CMD_DHCP
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +0100131#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500132#define CONFIG_CMD_EEPROM
133#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200134#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500135#define CONFIG_CMD_SNTP
136
wdenkf12e5682003-07-07 20:07:54 +0000137
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200138#define CONFIG_NETCONSOLE
139
140
wdenkf12e5682003-07-07 20:07:54 +0000141/*
142 * Miscellaneous configurable options
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf12e5682003-07-07 20:07:54 +0000145
Wolfgang Denk2751a952006-10-28 02:29:14 +0200146#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000148
Jon Loeliger26946902007-07-04 22:30:50 -0500149#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000151#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000153#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
155#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
156#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
159#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000162
wdenkf12e5682003-07-07 20:07:54 +0000163/*
164 * Low Level Configuration Settings
165 * (address mappings, register initial values, etc.)
166 * You should know what you are doing if you make changes here.
167 */
168/*-----------------------------------------------------------------------
169 * Internal Memory Mapped Register
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000172
173/*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in DPRAM)
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200177#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200178#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000180
181/*-----------------------------------------------------------------------
182 * Start addresses for the final memory configuration
183 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_SDRAM_BASE 0x00000000
187#define CONFIG_SYS_FLASH_BASE 0x40000000
188#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
189#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
190#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000191
192/*
193 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization.
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000198
199/*-----------------------------------------------------------------------
200 * FLASH organization
201 */
wdenkf12e5682003-07-07 20:07:54 +0000202
Martin Krausee318d9e2007-09-27 11:10:08 +0200203/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200205#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
207#define CONFIG_SYS_FLASH_EMPTY_INFO
208#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
209#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
210#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000211
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200212#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200213#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
214#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
215#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000216
217/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
219#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200222
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200223#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
224
wdenkf12e5682003-07-07 20:07:54 +0000225/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200226 * Dynamic MTD partition support
227 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100228#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200229#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
230#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200231#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
232
233#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
234 "128k(dtb)," \
235 "1920k(kernel)," \
236 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200237 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200238
239/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000240 * Hardware Information Block
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
243#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
244#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000245
246/*-----------------------------------------------------------------------
247 * Cache Configuration
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500250#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000252#endif
253
254/*-----------------------------------------------------------------------
255 * SYPCR - System Protection Control 11-9
256 * SYPCR can only be written once after reset!
257 *-----------------------------------------------------------------------
258 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
259 */
260#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000262 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
263#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000265#endif
266
267/*-----------------------------------------------------------------------
268 * SIUMCR - SIU Module Configuration 11-6
269 *-----------------------------------------------------------------------
270 * PCMCIA config., multi-function pin tri-state
271 */
272#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000274#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000276#endif /* CONFIG_CAN_DRIVER */
277
278/*-----------------------------------------------------------------------
279 * TBSCR - Time Base Status and Control 11-26
280 *-----------------------------------------------------------------------
281 * Clear Reference Interrupt Status, Timebase freezing enabled
282 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000284
285/*-----------------------------------------------------------------------
286 * RTCSC - Real-Time Clock Status and Control Register 11-27
287 *-----------------------------------------------------------------------
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000290
291/*-----------------------------------------------------------------------
292 * PISCR - Periodic Interrupt Status and Control 11-31
293 *-----------------------------------------------------------------------
294 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000297
298/*-----------------------------------------------------------------------
299 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
300 *-----------------------------------------------------------------------
301 * Reset PLL lock status sticky bit, timer expired status bit and timer
302 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000303 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000305
306/*-----------------------------------------------------------------------
307 * SCCR - System Clock and reset Control Register 15-27
308 *-----------------------------------------------------------------------
309 * Set clock output, timebase and RTC source and divider,
310 * power management and some other internal clocks
311 */
312#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000314 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
315 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000316
317/*-----------------------------------------------------------------------
318 * PCMCIA stuff
319 *-----------------------------------------------------------------------
320 *
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
323#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
325#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
326#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
327#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
328#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
329#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000330
331/*-----------------------------------------------------------------------
332 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
333 *-----------------------------------------------------------------------
334 */
335
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000336#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000337#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
338
339#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
340#undef CONFIG_IDE_LED /* LED for ide not supported */
341#undef CONFIG_IDE_RESET /* reset for ide not supported */
342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
344#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000349
350/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000352
353/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000355
356/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000358
359/*-----------------------------------------------------------------------
360 *
361 *-----------------------------------------------------------------------
362 *
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000365
366/*
367 * Init Memory Controller:
368 *
369 * BR0/1 and OR0/1 (FLASH)
370 */
371
372#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
373#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
374
375/* used to re-map FLASH both when starting from SRAM or FLASH:
376 * restrict access enough to keep SRAM working (if any)
377 * but not too much to meddle with FLASH accesses
378 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
380#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000381
382/*
383 * FLASH timing:
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000386 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
389#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
390#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
393#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
394#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000395
396/*
397 * BR2/3 and OR2/3 (SDRAM)
398 *
399 */
400#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
401#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
402#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
403
404/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
408#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000409
410#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
412#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000413#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
415#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
416#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
417#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000418 BR_PS_8 | BR_MS_UPMB | BR_V )
419#endif /* CONFIG_CAN_DRIVER */
420
421/*
422 * Memory Periodic Timer Prescaler
423 *
424 * The Divider for PTA (refresh timer) configuration is based on an
425 * example SDRAM configuration (64 MBit, one bank). The adjustment to
426 * the number of chip selects (NCS) and the actually needed refresh
427 * rate is done by setting MPTPR.
428 *
429 * PTA is calculated from
430 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
431 *
432 * gclk CPU clock (not bus clock!)
433 * Trefresh Refresh cycle * 4 (four word bursts used)
434 *
435 * 4096 Rows from SDRAM example configuration
436 * 1000 factor s -> ms
437 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
438 * 4 Number of refresh cycles per period
439 * 64 Refresh cycle in ms per number of rows
440 * --------------------------------------------
441 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
442 *
443 * 50 MHz => 50.000.000 / Divider = 98
444 * 66 Mhz => 66.000.000 / Divider = 129
445 * 80 Mhz => 80.000.000 / Divider = 156
446 */
wdenke9132ea2004-04-24 23:23:30 +0000447
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
449#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000450
451/*
452 * For 16 MBit, refresh rates could be 31.3 us
453 * (= 64 ms / 2K = 125 / quad bursts).
454 * For a simpler initialization, 15.6 us is used instead.
455 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
457 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000458 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
460#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000461
462/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
464#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000465
466/*
467 * MAMR settings for SDRAM
468 */
469
470/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000472 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
473 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
474/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000476 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
477 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
478
wdenkf12e5682003-07-07 20:07:54 +0000479#define CONFIG_SCC1_ENET
480#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200481#define CONFIG_ETHPRIME "SCC"
wdenkf12e5682003-07-07 20:07:54 +0000482
Heiko Schocher7026ead2010-02-09 15:50:27 +0100483/* pass open firmware flat tree */
484#define CONFIG_OF_LIBFDT 1
485#define CONFIG_OF_BOARD_SETUP 1
486#define CONFIG_HWCONFIG 1
487
wdenkf12e5682003-07-07 20:07:54 +0000488#endif /* __CONFIG_H */