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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d037e79f3a6e1bd1214ce97cf063885bb25be812 / . / arch / arm / dts / imx6qdl-gw54xx.dtsi
blob: 98c81e9c9b5bc27a110c4a703d57df67fd70adcf [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/sound/fsl-imx-audmux.h>
10
11/ {
12 /* these are used by bootloader for disabling nodes */
13 aliases {
14 led0 = &led0;
15 led1 = &led1;
16 led2 = &led2;
Tim Harvey19a387f2021-03-01 14:33:35 -0800[diff] [blame]17 mmc0 = &usdhc3;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]18 nand = &gpmi;
19 ssi0 = &ssi1;
Tim Harveydd79c972021-07-24 10:40:36 -0700[diff] [blame]20 usb0 = &usbotg;
21 usb1 = &usbh1;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 backlight {
29 compatible = "pwm-backlight";
30 pwms = <&pwm4 0 5000000>;
31 brightness-levels = <0 4 8 16 32 64 128 255>;
32 default-brightness-level = <7>;
33 };
34
35 gpio-keys {
36 compatible = "gpio-keys";
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 user-pb {
41 label = "user_pb";
42 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
43 linux,code = <BTN_0>;
44 };
45
46 user-pb1x {
47 label = "user_pb1x";
48 linux,code = <BTN_1>;
49 interrupt-parent = <&gsc>;
50 interrupts = <0>;
51 };
52
53 key-erased {
54 label = "key-erased";
55 linux,code = <BTN_2>;
56 interrupt-parent = <&gsc>;
57 interrupts = <1>;
58 };
59
60 eeprom-wp {
61 label = "eeprom_wp";
62 linux,code = <BTN_3>;
63 interrupt-parent = <&gsc>;
64 interrupts = <2>;
65 };
66
67 tamper {
68 label = "tamper";
69 linux,code = <BTN_4>;
70 interrupt-parent = <&gsc>;
71 interrupts = <5>;
72 };
73
74 switch-hold {
75 label = "switch_hold";
76 linux,code = <BTN_5>;
77 interrupt-parent = <&gsc>;
78 interrupts = <7>;
79 };
80 };
81
82 leds {
83 compatible = "gpio-leds";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_gpio_leds>;
86
87 led0: user1 {
88 label = "user1";
89 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
90 default-state = "on";
91 linux,default-trigger = "heartbeat";
92 };
93
94 led1: user2 {
95 label = "user2";
96 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
97 default-state = "off";
98 };
99
100 led2: user3 {
101 label = "user3";
102 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
103 default-state = "off";
104 };
105 };
106
107 memory@10000000 {
108 device_type = "memory";
109 reg = <0x10000000 0x40000000>;
110 };
111
112 pps {
113 compatible = "pps-gpio";
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_pps>;
116 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
117 status = "okay";
118 };
119
120 regulators {
121 compatible = "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 reg_1p0v: regulator@0 {
126 compatible = "regulator-fixed";
127 reg = <0>;
128 regulator-name = "1P0V";
129 regulator-min-microvolt = <1000000>;
130 regulator-max-microvolt = <1000000>;
131 regulator-always-on;
132 };
133
134 reg_3p3v: regulator@1 {
135 compatible = "regulator-fixed";
136 reg = <1>;
137 regulator-name = "3P3V";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 regulator-always-on;
141 };
142
143 reg_usb_h1_vbus: regulator@2 {
144 compatible = "regulator-fixed";
145 reg = <2>;
146 regulator-name = "usb_h1_vbus";
147 regulator-min-microvolt = <5000000>;
148 regulator-max-microvolt = <5000000>;
Tim Harvey073b1052021-09-29 15:04:22 -0700[diff] [blame]149 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
150 enable-active-high;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]151 };
152
153 reg_usb_otg_vbus: regulator@3 {
154 compatible = "regulator-fixed";
155 reg = <3>;
156 regulator-name = "usb_otg_vbus";
157 regulator-min-microvolt = <5000000>;
158 regulator-max-microvolt = <5000000>;
159 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
160 enable-active-high;
161 };
162 };
163
164 sound-analog {
165 compatible = "fsl,imx6q-ventana-sgtl5000",
166 "fsl,imx-audio-sgtl5000";
167 model = "sgtl5000-audio";
168 ssi-controller = <&ssi1>;
169 audio-codec = <&sgtl5000>;
170 audio-routing =
171 "MIC_IN", "Mic Jack",
172 "Mic Jack", "Mic Bias",
173 "Headphone Jack", "HP_OUT";
174 mux-int-port = <1>;
175 mux-ext-port = <4>;
176 };
177};
178
179&audmux {
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
182 status = "okay";
183
184 ssi2 {
185 fsl,audmux-port = <1>;
186 fsl,port-config = <
187 (IMX_AUDMUX_V2_PTCR_TFSDIR |
188 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
189 IMX_AUDMUX_V2_PTCR_TCLKDIR |
190 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
191 IMX_AUDMUX_V2_PTCR_SYN)
192 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
193 >;
194 };
195
196 aud5 {
197 fsl,audmux-port = <4>;
198 fsl,port-config = <
199 IMX_AUDMUX_V2_PTCR_SYN
200 IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
201 };
202};
203
204&can1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_flexcan1>;
207 status = "okay";
208};
209
210&clks {
211 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
212 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
213 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
214 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
215};
216
217&ecspi2 {
218 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_ecspi2>;
221 status = "okay";
222};
223
224&fec {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_enet>;
227 phy-mode = "rgmii-id";
228 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harveycd18f1e2021-05-03 11:21:27 -0700[diff] [blame]229 phy-reset-duration = <10>;
230 phy-reset-post-delay = <100>;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]231 status = "okay";
232};
233
234&gpmi {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_gpmi_nand>;
237 status = "okay";
238};
239
240&hdmi {
241 ddc-i2c-bus = <&i2c3>;
242 status = "okay";
243};
244
245&i2c1 {
246 clock-frequency = <100000>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c1>;
249 status = "okay";
250
251 gsc: gsc@20 {
252 compatible = "gw,gsc";
253 reg = <0x20>;
254 interrupt-parent = <&gpio1>;
255 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
256 interrupt-controller;
257 #interrupt-cells = <1>;
258 #address-cells = <1>;
259 #size-cells = <0>;
260
261 adc {
262 compatible = "gw,gsc-adc";
263 #address-cells = <1>;
264 #size-cells = <0>;
265
266 channel@0 {
267 gw,mode = <0>;
268 reg = <0x00>;
269 label = "temp";
270 };
271
272 channel@2 {
273 gw,mode = <1>;
274 reg = <0x02>;
275 label = "vdd_vin";
276 };
277
278 channel@5 {
279 gw,mode = <1>;
280 reg = <0x05>;
281 label = "vdd_3p3";
282 };
283
284 channel@8 {
285 gw,mode = <1>;
286 reg = <0x08>;
287 label = "vdd_bat";
288 };
289
290 channel@b {
291 gw,mode = <1>;
292 reg = <0x0b>;
293 label = "vdd_5p0";
294 };
295
296 channel@e {
297 gw,mode = <1>;
298 reg = <0xe>;
299 label = "vdd_arm";
300 };
301
302 channel@11 {
303 gw,mode = <1>;
304 reg = <0x11>;
305 label = "vdd_soc";
306 };
307
308 channel@14 {
309 gw,mode = <1>;
310 reg = <0x14>;
311 label = "vdd_3p0";
312 };
313
314 channel@17 {
315 gw,mode = <1>;
316 reg = <0x17>;
317 label = "vdd_1p5";
318 };
319
320 channel@1d {
321 gw,mode = <1>;
322 reg = <0x1d>;
323 label = "vdd_1p8";
324 };
325
326 channel@20 {
327 gw,mode = <1>;
328 reg = <0x20>;
329 label = "vdd_1p0";
330 };
331
332 channel@23 {
333 gw,mode = <1>;
334 reg = <0x23>;
335 label = "vdd_2p5";
336 };
337
338 channel@26 {
339 gw,mode = <1>;
340 reg = <0x26>;
341 label = "vdd_gps";
342 };
343 };
344
345 fan-controller@2c {
346 compatible = "gw,gsc-fan";
347 #address-cells = <1>;
348 #size-cells = <0>;
349 reg = <0x2c>;
350 };
351 };
352
353 gsc_gpio: gpio@23 {
354 compatible = "nxp,pca9555";
355 reg = <0x23>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-parent = <&gsc>;
359 interrupts = <4>;
360 };
361
362 eeprom1: eeprom@50 {
363 compatible = "atmel,24c02";
364 reg = <0x50>;
365 pagesize = <16>;
366 };
367
368 eeprom2: eeprom@51 {
369 compatible = "atmel,24c02";
370 reg = <0x51>;
371 pagesize = <16>;
372 };
373
374 eeprom3: eeprom@52 {
375 compatible = "atmel,24c02";
376 reg = <0x52>;
377 pagesize = <16>;
378 };
379
380 eeprom4: eeprom@53 {
381 compatible = "atmel,24c02";
382 reg = <0x53>;
383 pagesize = <16>;
384 };
385
386 rtc: ds1672@68 {
387 compatible = "dallas,ds1672";
388 reg = <0x68>;
389 };
390};
391
392&i2c2 {
393 clock-frequency = <100000>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&pinctrl_i2c2>;
396 status = "okay";
397
398 pmic: pfuze100@8 {
399 compatible = "fsl,pfuze100";
400 reg = <0x08>;
401
402 regulators {
403 sw1a_reg: sw1ab {
404 regulator-min-microvolt = <300000>;
405 regulator-max-microvolt = <1875000>;
406 regulator-boot-on;
407 regulator-always-on;
408 regulator-ramp-delay = <6250>;
409 };
410
411 sw1c_reg: sw1c {
412 regulator-min-microvolt = <300000>;
413 regulator-max-microvolt = <1875000>;
414 regulator-boot-on;
415 regulator-always-on;
416 regulator-ramp-delay = <6250>;
417 };
418
419 sw2_reg: sw2 {
420 regulator-min-microvolt = <800000>;
421 regulator-max-microvolt = <3950000>;
422 regulator-boot-on;
423 regulator-always-on;
424 };
425
426 sw3a_reg: sw3a {
427 regulator-min-microvolt = <400000>;
428 regulator-max-microvolt = <1975000>;
429 regulator-boot-on;
430 regulator-always-on;
431 };
432
433 sw3b_reg: sw3b {
434 regulator-min-microvolt = <400000>;
435 regulator-max-microvolt = <1975000>;
436 regulator-boot-on;
437 regulator-always-on;
438 };
439
440 sw4_reg: sw4 {
441 regulator-min-microvolt = <800000>;
442 regulator-max-microvolt = <3300000>;
443 };
444
445 swbst_reg: swbst {
446 regulator-min-microvolt = <5000000>;
447 regulator-max-microvolt = <5150000>;
448 regulator-boot-on;
449 regulator-always-on;
450 };
451
452 snvs_reg: vsnvs {
453 regulator-min-microvolt = <1000000>;
454 regulator-max-microvolt = <3000000>;
455 regulator-boot-on;
456 regulator-always-on;
457 };
458
459 vref_reg: vrefddr {
460 regulator-boot-on;
461 regulator-always-on;
462 };
463
464 vgen1_reg: vgen1 {
465 regulator-min-microvolt = <800000>;
466 regulator-max-microvolt = <1550000>;
467 };
468
469 vgen2_reg: vgen2 {
470 regulator-min-microvolt = <800000>;
471 regulator-max-microvolt = <1550000>;
472 };
473
474 vgen3_reg: vgen3 {
475 regulator-min-microvolt = <1800000>;
476 regulator-max-microvolt = <3300000>;
477 };
478
479 vgen4_reg: vgen4 {
480 regulator-min-microvolt = <1800000>;
481 regulator-max-microvolt = <3300000>;
482 regulator-always-on;
483 };
484
485 vgen5_reg: vgen5 {
486 regulator-min-microvolt = <1800000>;
487 regulator-max-microvolt = <3300000>;
488 regulator-always-on;
489 };
490
491 vgen6_reg: vgen6 {
492 regulator-min-microvolt = <1800000>;
493 regulator-max-microvolt = <3300000>;
494 regulator-always-on;
495 };
496 };
497 };
498};
499
500&i2c3 {
501 clock-frequency = <100000>;
502 pinctrl-names = "default";
503 pinctrl-0 = <&pinctrl_i2c3>;
504 status = "okay";
505
506 sgtl5000: audio-codec@a {
507 compatible = "fsl,sgtl5000";
508 reg = <0x0a>;
509 clocks = <&clks IMX6QDL_CLK_CKO>;
510 VDDA-supply = <&sw4_reg>;
511 VDDIO-supply = <&reg_3p3v>;
512 };
513
514 touchscreen: egalax_ts@4 {
515 compatible = "eeti,egalax_ts";
516 reg = <0x04>;
517 interrupt-parent = <&gpio7>;
518 interrupts = <12 2>;
519 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
520 };
521
522 accel@1e {
523 compatible = "nxp,fxos8700";
524 reg = <0x1e>;
525 };
526};
527
528&ldb {
529 status = "okay";
530
531 lvds-channel@0 {
532 fsl,data-mapping = "spwg";
533 fsl,data-width = <18>;
534 status = "okay";
535
536 display-timings {
537 native-mode = <&timing0>;
538 timing0: hsd100pxn1 {
539 clock-frequency = <65000000>;
540 hactive = <1024>;
541 vactive = <768>;
542 hback-porch = <220>;
543 hfront-porch = <40>;
544 vback-porch = <21>;
545 vfront-porch = <7>;
546 hsync-len = <60>;
547 vsync-len = <10>;
548 };
549 };
550 };
551};
552
553&pcie {
554 pinctrl-names = "default";
555 pinctrl-0 = <&pinctrl_pcie>;
556 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
557 status = "okay";
558};
559
560&pwm1 {
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
563 status = "disabled";
564};
565
566&pwm2 {
567 pinctrl-names = "default";
568 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
569 status = "disabled";
570};
571
572&pwm3 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
575 status = "disabled";
576};
577
578&pwm4 {
579 #pwm-cells = <2>;
580 pinctrl-names = "default", "state_dio";
581 pinctrl-0 = <&pinctrl_pwm4_backlight>;
582 pinctrl-1 = <&pinctrl_pwm4_dio>;
583 status = "okay";
584};
585
586&ssi1 {
587 status = "okay";
588};
589
590&ssi2 {
591 status = "okay";
592};
593
594&uart1 {
595 pinctrl-names = "default";
596 pinctrl-0 = <&pinctrl_uart1>;
597 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
598 status = "okay";
599};
600
601&uart2 {
602 pinctrl-names = "default";
603 pinctrl-0 = <&pinctrl_uart2>;
604 status = "okay";
605};
606
607&uart5 {
608 pinctrl-names = "default";
609 pinctrl-0 = <&pinctrl_uart5>;
610 status = "okay";
611};
612
613&usbotg {
614 vbus-supply = <&reg_usb_otg_vbus>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_usbotg>;
617 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]618 dr_mode = "otg";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]619 status = "okay";
620};
621
622&usbh1 {
623 vbus-supply = <&reg_usb_h1_vbus>;
Tim Harvey073b1052021-09-29 15:04:22 -0700[diff] [blame]624 pinctrl-names = "default";
625 pinctrl-0 = <&pinctrl_usbh1>;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]626 status = "okay";
627};
628
629&usdhc3 {
630 pinctrl-names = "default", "state_100mhz", "state_200mhz";
631 pinctrl-0 = <&pinctrl_usdhc3>;
632 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
633 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
634 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
635 vmmc-supply = <&reg_3p3v>;
636 no-1-8-v; /* firmware will remove if board revision supports */
637 status = "okay";
638};
639
640&wdog1 {
641 status = "disabled";
642};
643
644&wdog2 {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_wdog>;
647 fsl,ext-reset-output;
648 status = "okay";
649};
650
651&iomuxc {
652 pinctrl_audmux: audmuxgrp {
653 fsl,pins = <
654 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
655 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
656 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
657 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
658 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
659 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
660 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
661 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
662 >;
663 };
664
665 pinctrl_enet: enetgrp {
666 fsl,pins = <
667 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
668 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
669 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
670 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
671 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
672 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
673 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
674 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
675 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
676 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
677 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
678 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
679 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
680 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
681 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
682 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Tim Harveycd18f1e2021-05-03 11:21:27 -0700[diff] [blame]683 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]684 >;
685 };
686
687 pinctrl_ecspi2: escpi2grp {
688 fsl,pins = <
689 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
690 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
691 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
692 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
693 >;
694 };
695
696 pinctrl_flexcan1: flexcan1grp {
697 fsl,pins = <
698 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
699 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
700 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
701 >;
702 };
703
704 pinctrl_gpio_leds: gpioledsgrp {
705 fsl,pins = <
706 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
707 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
708 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
709 >;
710 };
711
712 pinctrl_gpmi_nand: gpminandgrp {
713 fsl,pins = <
714 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
715 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
716 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
717 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
718 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
719 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
720 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
721 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
722 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
723 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
724 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
725 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
726 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
727 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
728 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
729 >;
730 };
731
732 pinctrl_i2c1: i2c1grp {
733 fsl,pins = <
734 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
735 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
736 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
737 >;
738 };
739
740 pinctrl_i2c2: i2c2grp {
741 fsl,pins = <
742 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
743 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
744 >;
745 };
746
747 pinctrl_i2c3: i2c3grp {
748 fsl,pins = <
749 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
750 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
751 >;
752 };
753
754 pinctrl_pcie: pciegrp {
755 fsl,pins = <
756 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
757 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
758 >;
759 };
760
761 pinctrl_pps: ppsgrp {
762 fsl,pins = <
763 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
764 >;
765 };
766
767 pinctrl_pwm1: pwm1grp {
768 fsl,pins = <
769 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
770 >;
771 };
772
773 pinctrl_pwm2: pwm2grp {
774 fsl,pins = <
775 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
776 >;
777 };
778
779 pinctrl_pwm3: pwm3grp {
780 fsl,pins = <
781 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
782 >;
783 };
784
785 pinctrl_pwm4_backlight: pwm4grpbacklight {
786 fsl,pins = <
787 /* LVDS_PWM J6.5 */
788 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
789 >;
790 };
791
792 pinctrl_pwm4_dio: pwm4grpdio {
793 fsl,pins = <
794 /* DIO3 J16.4 */
795 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
796 >;
797 };
798
799 pinctrl_uart1: uart1grp {
800 fsl,pins = <
801 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
802 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
803 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
804 >;
805 };
806
807 pinctrl_uart2: uart2grp {
808 fsl,pins = <
809 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
810 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
811 >;
812 };
813
814 pinctrl_uart5: uart5grp {
815 fsl,pins = <
816 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
817 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
818 >;
819 };
820
Tim Harvey073b1052021-09-29 15:04:22 -0700[diff] [blame]821 pinctrl_usbh1: usbh1grp {
822 fsl,pins = <
823 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
824 >;
825 };
826
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]827 pinctrl_usbotg: usbotggrp {
828 fsl,pins = <
829 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
830 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
Tim Harveya194e6e2021-07-24 10:40:38 -0700[diff] [blame]831 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x17059
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]832 >;
833 };
834
835 pinctrl_usdhc3: usdhc3grp {
836 fsl,pins = <
837 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
838 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
839 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
840 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
841 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
842 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
843 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
844 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
845 >;
846 };
847
848 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
849 fsl,pins = <
850 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
851 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
852 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
853 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
854 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
855 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
856 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
857 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
858 >;
859 };
860
861 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
862 fsl,pins = <
863 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
864 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
865 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
866 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
867 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
868 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
869 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
870 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
871 >;
872 };
873
874 pinctrl_wdog: wdoggrp {
875 fsl,pins = <
876 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
877 >;
878 };
879};