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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesec2642d12004-12-16 18:38:22 +00002 * (C) Copyright 2001-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000027#include <malloc.h>
28#include <pci.h>
Stefan Roese3048bcb2007-10-03 15:01:02 +020029#include <asm/4xx_pci.h>
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010030#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000031
stroesed69b1002003-03-25 14:41:35 +000032#include "pci405.h"
33
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
stroesed69b1002003-03-25 14:41:35 +000035
stroesec2642d12004-12-16 18:38:22 +000036/* Prototypes */
37int gunzip(void *, int, unsigned char *, unsigned long *);
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010038int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
stroesec2642d12004-12-16 18:38:22 +000039unsigned long fpga_done_state(void);
40unsigned long fpga_init_state(void);
41
wdenkc6097192002-11-03 00:24:07 +000042#if 0
43#define FPGA_DEBUG
44#endif
45
stroesec2642d12004-12-16 18:38:22 +000046/* predefine these here */
47#define FPGA_DONE_STATE (fpga_done_state())
48#define FPGA_INIT_STATE (fpga_init_state())
49
wdenkc6097192002-11-03 00:24:07 +000050/* fpga configuration data - generated by bin2cc */
51const unsigned char fpgadata[] =
52{
53#include "fpgadata.c"
54};
55
56/*
57 * include common fpga code (for esd boards)
58 */
59#include "../common/fpga.c"
60
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010061#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
62#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
wdenkc6097192002-11-03 00:24:07 +000063
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010064#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
65#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
stroesec2642d12004-12-16 18:38:22 +000066
67
68int board_revision(void)
69{
Stefan Roesed1c3b272009-09-09 16:25:29 +020070 unsigned long CPC0_CR0Reg;
stroesec2642d12004-12-16 18:38:22 +000071 unsigned long value;
72
73 /*
74 * Get version of PCI405 board from GPIO's
75 */
76
77 /*
78 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
79 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020080 CPC0_CR0Reg = mfdcr(CPC0_CR0);
81 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010082 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
83 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
stroesec2642d12004-12-16 18:38:22 +000084 udelay(1000); /* wait some time before reading input */
Matthias Fuchs0c2385c2008-11-24 15:11:09 +010085 value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
stroesec2642d12004-12-16 18:38:22 +000086
87 /*
88 * Restore GPIO settings
89 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020090 mtdcr(CPC0_CR0, CPC0_CR0Reg);
stroesec2642d12004-12-16 18:38:22 +000091
92 switch (value) {
Stefan Roese5315dfa2005-08-12 16:56:56 +020093 case 0x00100200:
94 /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
stroesec2642d12004-12-16 18:38:22 +000095 return 1;
Stefan Roese5315dfa2005-08-12 16:56:56 +020096 case 0x00000200:
97 /* CS2==0 && IRQ5==1 -> version 1.2 */
stroesec2642d12004-12-16 18:38:22 +000098 return 2;
Stefan Roese5315dfa2005-08-12 16:56:56 +020099 case 0x00000000:
100 /* CS2==0 && IRQ5==0 -> version 1.3 */
101 return 3;
stroesec2642d12004-12-16 18:38:22 +0000102#if 0 /* not yet manufactured ! */
103 case 0x00100000:
Stefan Roese5315dfa2005-08-12 16:56:56 +0200104 /* CS2==1 && IRQ5==0 -> version 1.4 */
stroesec2642d12004-12-16 18:38:22 +0000105 return 4;
106#endif
107 default:
108 /* should not be reached! */
109 return 0;
110 }
111}
112
113
114unsigned long fpga_done_state(void)
115{
stroesec2642d12004-12-16 18:38:22 +0000116 if (gd->board_type < 2) {
117 return FPGA_DONE_STATE_V11;
118 } else {
119 return FPGA_DONE_STATE_V12;
120 }
121}
122
123
124unsigned long fpga_init_state(void)
125{
stroesec2642d12004-12-16 18:38:22 +0000126 if (gd->board_type < 2) {
127 return FPGA_INIT_STATE_V11;
128 } else {
129 return FPGA_INIT_STATE_V12;
130 }
131}
wdenkc6097192002-11-03 00:24:07 +0000132
133
wdenkc837dcb2004-01-20 23:12:12 +0000134int board_early_init_f (void)
wdenkc6097192002-11-03 00:24:07 +0000135{
Stefan Roesed1c3b272009-09-09 16:25:29 +0200136 unsigned long CPC0_CR0Reg;
wdenkc6097192002-11-03 00:24:07 +0000137
138 /*
stroesec2642d12004-12-16 18:38:22 +0000139 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
140 */
Matthias Fuchs0c2385c2008-11-24 15:11:09 +0100141 out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
142 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
143 out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
144 out_be32((void*)GPIO0_OR, 0); /* pull prg low */
stroesec2642d12004-12-16 18:38:22 +0000145
146 /*
wdenkc6097192002-11-03 00:24:07 +0000147 * IRQ 0-15 405GP internally generated; active high; level sensitive
148 * IRQ 16 405GP internally generated; active low; level sensitive
149 * IRQ 17-24 RESERVED
150 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
151 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
152 * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
153 * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
154 * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
155 * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
156 * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
157 */
158 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
159 mtdcr(uicer, 0x00000000); /* disable all ints */
160 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
161 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
162 mtdcr(uictr, 0x10000000); /* set int trigger levels */
163 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
164 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
165
166 /*
167 * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
168 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200169 CPC0_CR0Reg = mfdcr(CPC0_CR0);
170 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
wdenkc6097192002-11-03 00:24:07 +0000171
stroese1545ad32003-05-23 11:33:57 +0000172 /*
stroesec2642d12004-12-16 18:38:22 +0000173 * Setup GPIO pins (CS6+CS7 as GPIO)
174 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200175 mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
stroesec2642d12004-12-16 18:38:22 +0000176
177 /*
stroese1545ad32003-05-23 11:33:57 +0000178 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
179 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200180 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
stroese1545ad32003-05-23 11:33:57 +0000181
wdenkc6097192002-11-03 00:24:07 +0000182 return 0;
183}
184
wdenkc6097192002-11-03 00:24:07 +0000185int misc_init_r (void)
186{
187 unsigned char *dst;
188 ulong len = sizeof(fpgadata);
189 int status;
190 int index;
191 int i;
stroesed69b1002003-03-25 14:41:35 +0000192 unsigned int *ptr;
193 unsigned int *magic;
wdenkc6097192002-11-03 00:24:07 +0000194
195 /*
196 * On PCI-405 the environment is saved in eeprom!
197 * FPGA can be gzip compressed (malloc) and booted this late.
198 */
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
201 if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
wdenkc6097192002-11-03 00:24:07 +0000202 printf ("GUNZIP ERROR - must RESET board to recover\n");
203 do_reset (NULL, 0, 0, NULL);
204 }
205
206 status = fpga_boot(dst, len);
207 if (status != 0) {
208 printf("\nFPGA: Booting failed ");
209 switch (status) {
210 case ERROR_FPGA_PRG_INIT_LOW:
211 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
212 break;
213 case ERROR_FPGA_PRG_INIT_HIGH:
214 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
215 break;
216 case ERROR_FPGA_PRG_DONE:
217 printf("(Timeout: DONE not high after programming FPGA)\n ");
218 break;
219 }
220
221 /* display infos on fpgaimage */
222 index = 15;
223 for (i=0; i<4; i++) {
224 len = dst[index];
225 printf("FPGA: %s\n", &(dst[index+1]));
226 index += len+3;
227 }
228 putc ('\n');
229 /* delayed reboot */
230 for (i=20; i>0; i--) {
231 printf("Rebooting in %2d seconds \r",i);
232 for (index=0;index<1000;index++)
233 udelay(1000);
234 }
235 putc ('\n');
236 do_reset(NULL, 0, 0, NULL);
237 }
238
239 puts("FPGA: ");
240
241 /* display infos on fpgaimage */
242 index = 15;
243 for (i=0; i<4; i++) {
244 len = dst[index];
245 printf("%s ", &(dst[index+1]));
246 index += len+3;
247 }
248 putc ('\n');
249
250 /*
stroesed69b1002003-03-25 14:41:35 +0000251 * Reset FPGA via FPGA_DATA pin
wdenkc6097192002-11-03 00:24:07 +0000252 */
stroesed69b1002003-03-25 14:41:35 +0000253 SET_FPGA(FPGA_PRG | FPGA_CLK);
254 udelay(1000); /* wait 1ms */
255 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
256 udelay(1000); /* wait 1ms */
wdenkc6097192002-11-03 00:24:07 +0000257
stroesed69b1002003-03-25 14:41:35 +0000258 /*
259 * Check if magic for pci reconfig is written
260 */
261 magic = (unsigned int *)0x00000004;
262 if (*magic == PCI_RECONFIG_MAGIC) {
263 /*
264 * Rewrite pci config regs (only after soft-reset with magic set)
265 */
266 ptr = (unsigned int *)PCI_REGS_ADDR;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200267 if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
stroesed69b1002003-03-25 14:41:35 +0000268 puts("Restoring PCI Configurations Regs!\n");
269 ptr = (unsigned int *)PCI_REGS_ADDR + 1;
270 for (i=0; i<0x40; i+=4) {
271 pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
272 }
273 }
274 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
stroese1545ad32003-05-23 11:33:57 +0000275
stroesed69b1002003-03-25 14:41:35 +0000276 *magic = 0; /* clear pci reconfig magic again */
277 }
wdenkc6097192002-11-03 00:24:07 +0000278
stroesec2642d12004-12-16 18:38:22 +0000279 /*
280 * Decrease PLB latency timeout and reduce priority of the PCI bridge master
281 */
282#define PCI0_BRDGOPT1 0x4a
283 pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
stroesec2642d12004-12-16 18:38:22 +0000284
Stefan Roesed1c3b272009-09-09 16:25:29 +0200285#define PLB0_ACR 0x87
stroesec2642d12004-12-16 18:38:22 +0000286 /*
287 * Enable fairness and high bus utilization
288 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200289 mtdcr(PLB0_ACR, 0x98000000);
stroesec2642d12004-12-16 18:38:22 +0000290
wdenkc6097192002-11-03 00:24:07 +0000291 free(dst);
292 return (0);
293}
294
295
296/*
297 * Check Board Identity:
298 */
wdenkc6097192002-11-03 00:24:07 +0000299int checkboard (void)
300{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200301 char str[64];
wdenkc6097192002-11-03 00:24:07 +0000302 int i = getenv_r ("serial#", str, sizeof(str));
303
304 puts ("Board: ");
305
306 if (i == -1) {
stroesed69b1002003-03-25 14:41:35 +0000307 puts ("### No HW ID - assuming PCI405");
wdenkc6097192002-11-03 00:24:07 +0000308 } else {
309 puts (str);
310 }
stroesec2642d12004-12-16 18:38:22 +0000311
312 gd->board_type = board_revision();
313 printf(" (Rev 1.%ld", gd->board_type);
314
315 if (gd->board_type >= 2) {
Stefan Roesed1c3b272009-09-09 16:25:29 +0200316 unsigned long CPC0_CR0Reg;
stroesec2642d12004-12-16 18:38:22 +0000317 unsigned long value;
318
319 /*
320 * Setup GPIO pins (Trace/GPIO1 to GPIO)
321 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200322 CPC0_CR0Reg = mfdcr(CPC0_CR0);
323 mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
Matthias Fuchs0c2385c2008-11-24 15:11:09 +0100324 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
325 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
stroesec2642d12004-12-16 18:38:22 +0000326 udelay(1000); /* wait some time before reading input */
Matthias Fuchs0c2385c2008-11-24 15:11:09 +0100327 value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
stroesec2642d12004-12-16 18:38:22 +0000328 if (value) {
329 puts(", 33 MHz PCI");
330 } else {
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200331 puts(", 66 MHz PCI");
stroesec2642d12004-12-16 18:38:22 +0000332 }
333 }
334
335 puts(")\n");
wdenkc6097192002-11-03 00:24:07 +0000336
337 return 0;
338}
339
340/* ------------------------------------------------------------------------- */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100341#define UART1_MCR 0xef600404
Stefan Roese5315dfa2005-08-12 16:56:56 +0200342int wpeeprom(int wp)
343{
344 int wp_state = wp;
Stefan Roese5315dfa2005-08-12 16:56:56 +0200345
346 if (wp == 1) {
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100347 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
Stefan Roese5315dfa2005-08-12 16:56:56 +0200348 } else if (wp == 0) {
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100349 out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
Stefan Roese5315dfa2005-08-12 16:56:56 +0200350 } else {
Matthias Fuchsbb57ad42009-02-20 10:19:19 +0100351 if (in_8((void *)UART1_MCR) & 0x02) {
Stefan Roese5315dfa2005-08-12 16:56:56 +0200352 wp_state = 0;
353 } else {
354 wp_state = 1;
355 }
356 }
357 return wp_state;
358}
359
360int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
361{
362 int wp = -1;
363 if (argc >= 2) {
364 if (argv[1][0] == '1') {
365 wp = 1;
366 } else if (argv[1][0] == '0') {
367 wp = 0;
368 }
369 }
370
371 wp = wpeeprom(wp);
372 printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
373 return 0;
374}
375
376U_BOOT_CMD(
377 wpeeprom, 2, 1, do_wpeeprom,
Peter Tyser2fb26042009-01-27 18:03:12 -0600378 "Check/Enable/Disable I2C EEPROM write protection",
Stefan Roese5315dfa2005-08-12 16:56:56 +0200379 "wpeeprom\n"
380 " - check I2C EEPROM write protection state\n"
381 "wpeeprom 1\n"
382 " - enable I2C EEPROM write protection\n"
383 "wpeeprom 0\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200384 " - disable I2C EEPROM write protection"
385);