blob: 8de65425c97c130311fb87b6bd59692e2a421f80 [file] [log] [blame]
wdenkfe8c2802002-11-03 00:38:21 +00001/*
Wolfgang Denkb9365a22006-07-21 11:56:05 +02002 * (C) Copyright 2000-2006
wdenkfe8c2802002-11-03 00:38:21 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
Stefan Roese3248f632007-10-22 16:22:40 +020023
wdenkfe8c2802002-11-03 00:38:21 +000024/*
Josh Boyer31773492009-08-07 13:53:20 -040025 * This source code is dual-licensed. You may use it under the terms of the
26 * GNU General Public License version 2, or under the license below.
27 *
wdenkfe8c2802002-11-03 00:38:21 +000028 * This source code has been made available to you by IBM on an AS-IS
29 * basis. Anyone receiving this source is licensed under IBM
30 * copyrights to use it in any way he or she deems fit, including
31 * copying it, modifying it, compiling it, and redistributing it either
32 * with or without modifications. No license under IBM patents or
33 * patent applications is to be implied by the copyright license.
34 *
35 * Any user of this software should understand that IBM cannot provide
36 * technical support for this software and will not be responsible for
37 * any consequences resulting from the use of this software.
38 *
39 * Any person who transfers this source code or any derivative work
40 * must include the IBM copyright notice, this paragraph, and the
41 * preceding two paragraphs in the transferred software.
42 *
43 * COPYRIGHT I B M CORPORATION 1995
44 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
45 */
Stefan Roese3248f632007-10-22 16:22:40 +020046
wdenkfe8c2802002-11-03 00:38:21 +000047#include <common.h>
48#include <commproc.h>
49#include <asm/processor.h>
Stefan Roese3248f632007-10-22 16:22:40 +020050#include <asm/io.h>
wdenkfe8c2802002-11-03 00:38:21 +000051#include <watchdog.h>
Stefan Roese4fb25a32008-06-25 10:59:22 +020052#include <ppc4xx.h>
wdenkfe8c2802002-11-03 00:38:21 +000053
wdenkff36fd82005-01-09 22:28:56 +000054#ifdef CONFIG_SERIAL_MULTI
55#include <serial.h>
56#endif
57
wdenk42dfe7a2004-03-14 22:25:36 +000058#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
wdenkfe8c2802002-11-03 00:38:21 +000059#include <malloc.h>
60#endif
61
Wolfgang Denkd87080b2006-03-31 18:32:53 +020062DECLARE_GLOBAL_DATA_PTR;
63
Stefan Roesee01bd212007-03-21 13:38:59 +010064#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
65 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +020066 defined(CONFIG_405EX) || defined(CONFIG_440)
wdenkfe8c2802002-11-03 00:38:21 +000067
68#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +020069#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +010070 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
71 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
73#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400)
Stefan Roesec157d8e2005-08-01 16:41:48 +020074#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200)
76#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300)
Stefan Roesec157d8e2005-08-01 16:41:48 +020077#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010078
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020079#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
Stefan Roese8ac41e32008-03-11 15:05:26 +010081#endif
82
83#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
85#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010086#endif
87
Stefan Roese887e2ec2006-09-07 11:51:23 +020088#if defined(CONFIG_440GP)
wdenkfe8c2802002-11-03 00:38:21 +000089#define CR0_MASK 0x3fff0000
90#define CR0_EXTCLK_ENA 0x00600000
91#define CR0_UDIV_POS 16
Stefan Roese887e2ec2006-09-07 11:51:23 +020092#define UDIV_SUBTRACT 1
Stefan Roesed1c3b272009-09-09 16:25:29 +020093#define UART0_SDR CPC0_CR0
Stefan Roese887e2ec2006-09-07 11:51:23 +020094#define MFREG(a, d) d = mfdcr(a)
95#define MTREG(a, d) mtdcr(a, d)
96#else /* #if defined(CONFIG_440GP) */
97/* all other 440 PPC's access clock divider via sdr register */
98#define CR0_MASK 0xdfffffff
99#define CR0_EXTCLK_ENA 0x00800000
100#define CR0_UDIV_POS 0
101#define UDIV_SUBTRACT 0
Stefan Roesed1c3b272009-09-09 16:25:29 +0200102#define UART0_SDR SDR0_UART0
103#define UART1_SDR SDR0_UART1
Stefan Roeseb2815f72008-06-06 16:10:41 +0200104#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
105 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100107 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200108#define UART2_SDR SDR0_UART2
Stefan Roese887e2ec2006-09-07 11:51:23 +0200109#endif
Stefan Roeseb2815f72008-06-06 16:10:41 +0200110#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
111 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100112 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200113#define UART3_SDR SDR0_UART3
Stefan Roese887e2ec2006-09-07 11:51:23 +0200114#endif
115#define MFREG(a, d) mfsdr(a, d)
116#define MTREG(a, d) mtsdr(a, d)
117#endif /* #if defined(CONFIG_440GP) */
Stefan Roesee01bd212007-03-21 13:38:59 +0100118#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
stroese8749cfb2003-05-23 11:25:57 +0000119#define UART0_BASE 0xef600300
120#define UART1_BASE 0xef600400
121#define UCR0_MASK 0x0000007f
122#define UCR1_MASK 0x00007f00
123#define UCR0_UDIV_POS 0
124#define UCR1_UDIV_POS 8
125#define UDIV_MAX 127
Stefan Roesedbbd1252007-10-05 17:10:59 +0200126#elif defined(CONFIG_405EX)
127#define UART0_BASE 0xef600200
128#define UART1_BASE 0xef600300
129#define CR0_MASK 0x000000ff
130#define CR0_EXTCLK_ENA 0x00800000
131#define CR0_UDIV_POS 0
132#define UDIV_SUBTRACT 0
Stefan Roesed1c3b272009-09-09 16:25:29 +0200133#define UART0_SDR SDR0_UART0
134#define UART1_SDR SDR0_UART1
stroese8749cfb2003-05-23 11:25:57 +0000135#else /* CONFIG_405GP || CONFIG_405CR */
wdenkfe8c2802002-11-03 00:38:21 +0000136#define UART0_BASE 0xef600300
137#define UART1_BASE 0xef600400
138#define CR0_MASK 0x00001fff
stroesed7787c62003-02-17 16:06:06 +0000139#define CR0_EXTCLK_ENA 0x000000c0
wdenkfe8c2802002-11-03 00:38:21 +0000140#define CR0_UDIV_POS 1
stroese8749cfb2003-05-23 11:25:57 +0000141#define UDIV_MAX 32
142#endif
143
144/* using serial port 0 or 1 as U-Boot console ? */
145#if defined(CONFIG_UART1_CONSOLE)
146#define ACTING_UART0_BASE UART1_BASE
147#define ACTING_UART1_BASE UART0_BASE
148#else
149#define ACTING_UART0_BASE UART0_BASE
150#define ACTING_UART1_BASE UART1_BASE
Stefan Roese887e2ec2006-09-07 11:51:23 +0200151#endif
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200154#error "External serial clock not supported on AMCC PPC405EP!"
wdenkfe8c2802002-11-03 00:38:21 +0000155#endif
156
157#define UART_RBR 0x00
158#define UART_THR 0x00
159#define UART_IER 0x01
160#define UART_IIR 0x02
161#define UART_FCR 0x02
162#define UART_LCR 0x03
163#define UART_MCR 0x04
164#define UART_LSR 0x05
165#define UART_MSR 0x06
166#define UART_SCR 0x07
167#define UART_DLL 0x00
168#define UART_DLM 0x01
169
170/*-----------------------------------------------------------------------------+
171 | Line Status Register.
172 +-----------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000173#define asyncLSRDataReady1 0x01
174#define asyncLSROverrunError1 0x02
175#define asyncLSRParityError1 0x04
176#define asyncLSRFramingError1 0x08
177#define asyncLSRBreakInterrupt1 0x10
178#define asyncLSRTxHoldEmpty1 0x20
179#define asyncLSRTxShiftEmpty1 0x40
180#define asyncLSRRxFifoError1 0x80
181
wdenk42dfe7a2004-03-14 22:25:36 +0000182#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
wdenkfe8c2802002-11-03 00:38:21 +0000183/*-----------------------------------------------------------------------------+
184 | Fifo
185 +-----------------------------------------------------------------------------*/
186typedef struct {
187 char *rx_buffer;
188 ulong rx_put;
189 ulong rx_get;
190} serial_buffer_t;
191
192volatile static serial_buffer_t buf_info;
193#endif
194
Stefan Roese3248f632007-10-22 16:22:40 +0200195static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
196{
197 PPC4xx_SYS_INFO sys_info;
198 u8 val;
199
200 get_sys_info(&sys_info);
201
202 /* Correct UART frequency in bd-info struct now that
203 * the UART divisor is available
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
206 gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
Stefan Roese3248f632007-10-22 16:22:40 +0200207#else
Stefan Roesef10493c2007-10-23 11:31:05 +0200208 gd->uart_clk = sys_info.freqUART / udiv;
Stefan Roese3248f632007-10-22 16:22:40 +0200209#endif
210
211 out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
212 out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
213 out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
214 out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
215 out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
216 out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
217 val = in_8((u8 *)base + UART_LSR); /* clear line status */
218 val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
219 out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
220 out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
221}
222
223#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
wdenkfe8c2802002-11-03 00:38:21 +0000225static void serial_divs (int baudrate, unsigned long *pudiv,
Stefan Roesee01bd212007-03-21 13:38:59 +0100226 unsigned short *pbdiv)
wdenkfe8c2802002-11-03 00:38:21 +0000227{
Stefan Roesee01bd212007-03-21 13:38:59 +0100228 sys_info_t sysinfo;
wdenkfe8c2802002-11-03 00:38:21 +0000229 unsigned long div; /* total divisor udiv * bdiv */
230 unsigned long umin; /* minimum udiv */
Stefan Roesee01bd212007-03-21 13:38:59 +0100231 unsigned short diff; /* smallest diff */
232 unsigned long udiv; /* best udiv */
233 unsigned short idiff; /* current diff */
234 unsigned short ibdiv; /* current bdiv */
wdenkfe8c2802002-11-03 00:38:21 +0000235 unsigned long i;
Stefan Roesee01bd212007-03-21 13:38:59 +0100236 unsigned long est; /* current estimate */
wdenkfe8c2802002-11-03 00:38:21 +0000237
Stefan Roesee01bd212007-03-21 13:38:59 +0100238 get_sys_info(&sysinfo);
wdenkfe8c2802002-11-03 00:38:21 +0000239
Stefan Roesee01bd212007-03-21 13:38:59 +0100240 udiv = 32; /* Assume lowest possible serial clk */
241 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
242 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
243 diff = 32; /* highest possible */
wdenkfe8c2802002-11-03 00:38:21 +0000244
245 /* i is the test udiv value -- start with the largest
246 * possible (32) to minimize serial clock and constrain
247 * search to umin.
248 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100249 for (i = 32; i > umin; i--) {
250 ibdiv = div / i;
wdenkfe8c2802002-11-03 00:38:21 +0000251 est = i * ibdiv;
252 idiff = (est > div) ? (est-div) : (div-est);
Stefan Roesee01bd212007-03-21 13:38:59 +0100253 if (idiff == 0) {
wdenkfe8c2802002-11-03 00:38:21 +0000254 udiv = i;
255 break; /* can't do better */
Stefan Roesee01bd212007-03-21 13:38:59 +0100256 } else if (idiff < diff) {
wdenkfe8c2802002-11-03 00:38:21 +0000257 udiv = i; /* best so far */
258 diff = idiff; /* update lowest diff*/
259 }
260 }
261
262 *pudiv = udiv;
Stefan Roesee01bd212007-03-21 13:38:59 +0100263 *pbdiv = div / udiv;
264}
wdenkfe8c2802002-11-03 00:38:21 +0000265
Stefan Roesee01bd212007-03-21 13:38:59 +0100266#elif defined(CONFIG_405EZ)
267
268static void serial_divs (int baudrate, unsigned long *pudiv,
269 unsigned short *pbdiv)
270{
271 sys_info_t sysinfo;
272 unsigned long div; /* total divisor udiv * bdiv */
273 unsigned long umin; /* minimum udiv */
274 unsigned short diff; /* smallest diff */
275 unsigned long udiv; /* best udiv */
276 unsigned short idiff; /* current diff */
277 unsigned short ibdiv; /* current bdiv */
278 unsigned long i;
279 unsigned long est; /* current estimate */
280 unsigned long plloutb;
Stefan Roese273db7e2007-08-13 09:05:33 +0200281 unsigned long cpr_pllc;
Stefan Roesee01bd212007-03-21 13:38:59 +0100282 u32 reg;
283
Stefan Roese273db7e2007-08-13 09:05:33 +0200284 /* check the pll feedback source */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200285 mfcpr(CPR0_PLLC, cpr_pllc);
Stefan Roese273db7e2007-08-13 09:05:33 +0200286
Stefan Roesee01bd212007-03-21 13:38:59 +0100287 get_sys_info(&sysinfo);
288
Stefan Roese429d9572007-08-14 15:03:17 +0200289 plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
Stefan Roese3248f632007-10-22 16:22:40 +0200290 sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
291 sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
Stefan Roesee01bd212007-03-21 13:38:59 +0100292 udiv = 256; /* Assume lowest possible serial clk */
293 div = plloutb / (16 * baudrate); /* total divisor */
294 umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
295 diff = 256; /* highest possible */
296
297 /* i is the test udiv value -- start with the largest
298 * possible (256) to minimize serial clock and constrain
299 * search to umin.
300 */
301 for (i = 256; i > umin; i--) {
302 ibdiv = div / i;
303 est = i * ibdiv;
304 idiff = (est > div) ? (est-div) : (div-est);
305 if (idiff == 0) {
306 udiv = i;
307 break; /* can't do better */
308 } else if (idiff < diff) {
309 udiv = i; /* best so far */
310 diff = idiff; /* update lowest diff*/
311 }
312 }
313
314 *pudiv = udiv;
Stefan Roesed1c3b272009-09-09 16:25:29 +0200315 mfcpr(CPC0_PERD0, reg);
Stefan Roesee01bd212007-03-21 13:38:59 +0100316 reg &= ~0x0000ffff;
317 reg |= ((udiv - 0) << 8) | (udiv - 0);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200318 mtcpr(CPC0_PERD0, reg);
Stefan Roesee01bd212007-03-21 13:38:59 +0100319 *pbdiv = div / udiv;
wdenkfe8c2802002-11-03 00:38:21 +0000320}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */
wdenkfe8c2802002-11-03 00:38:21 +0000322
wdenkfe8c2802002-11-03 00:38:21 +0000323/*
324 * Minimal serial functions needed to use one of the SMC ports
325 * as serial console interface.
326 */
327
328#if defined(CONFIG_440)
Stefan Roese3248f632007-10-22 16:22:40 +0200329int serial_init_dev(unsigned long base)
wdenkfe8c2802002-11-03 00:38:21 +0000330{
wdenkfe8c2802002-11-03 00:38:21 +0000331 unsigned long reg;
332 unsigned long udiv;
333 unsigned short bdiv;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
wdenkfe8c2802002-11-03 00:38:21 +0000335 unsigned long tmp;
336#endif
337
Stefan Roese887e2ec2006-09-07 11:51:23 +0200338 MFREG(UART0_SDR, reg);
wdenkba56f622004-02-06 23:19:44 +0000339 reg &= ~CR0_MASK;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
wdenkfe8c2802002-11-03 00:38:21 +0000342 reg |= CR0_EXTCLK_ENA;
343 udiv = 1;
344 tmp = gd->baudrate * 16;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345 bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
wdenkfe8c2802002-11-03 00:38:21 +0000346#else
347 /* For 440, the cpu clock is on divider chain A, UART on divider
348 * chain B ... so cpu clock is irrelevant. Get the "optimized"
349 * values that are subject to the 1/2 opb clock constraint
350 */
351 serial_divs (gd->baudrate, &udiv, &bdiv);
352#endif
353
Stefan Roese887e2ec2006-09-07 11:51:23 +0200354 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
355
356 /*
357 * Configure input clock to baudrate generator for all
358 * available serial ports here
359 */
360 MTREG(UART0_SDR, reg);
361#if defined(UART1_SDR)
362 MTREG(UART1_SDR, reg);
wdenkff36fd82005-01-09 22:28:56 +0000363#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200364#if defined(UART2_SDR)
365 MTREG(UART2_SDR, reg);
366#endif
367#if defined(UART3_SDR)
368 MTREG(UART3_SDR, reg);
wdenkba56f622004-02-06 23:19:44 +0000369#endif
wdenkff36fd82005-01-09 22:28:56 +0000370
Stefan Roese3248f632007-10-22 16:22:40 +0200371 serial_init_common(base, udiv, bdiv);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200372
wdenkfe8c2802002-11-03 00:38:21 +0000373 return (0);
374}
375
376#else /* !defined(CONFIG_440) */
377
Stefan Roese3248f632007-10-22 16:22:40 +0200378int serial_init_dev (unsigned long base)
wdenkfe8c2802002-11-03 00:38:21 +0000379{
wdenkfe8c2802002-11-03 00:38:21 +0000380 unsigned long reg;
381 unsigned long tmp;
382 unsigned long clk;
383 unsigned long udiv;
384 unsigned short bdiv;
wdenkfe8c2802002-11-03 00:38:21 +0000385
Stefan Roesedbbd1252007-10-05 17:10:59 +0200386#ifdef CONFIG_405EX
387 clk = tmp = 0;
388 mfsdr(UART0_SDR, reg);
389 reg &= ~CR0_MASK;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roesedbbd1252007-10-05 17:10:59 +0200391 reg |= CR0_EXTCLK_ENA;
392 udiv = 1;
393 tmp = gd->baudrate * 16;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394 bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200395#else
396 serial_divs(gd->baudrate, &udiv, &bdiv);
397#endif
398 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
399
400 /*
401 * Configure input clock to baudrate generator for all
402 * available serial ports here
403 */
404 mtsdr(UART0_SDR, reg);
405
406#if defined(UART1_SDR)
407 mtsdr(UART1_SDR, reg);
408#endif
409
410#elif defined(CONFIG_405EZ)
Stefan Roesee01bd212007-03-21 13:38:59 +0100411 serial_divs(gd->baudrate, &udiv, &bdiv);
412 clk = tmp = reg = 0;
413#else
stroese8749cfb2003-05-23 11:25:57 +0000414#ifdef CONFIG_405EP
Stefan Roesed1c3b272009-09-09 16:25:29 +0200415 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
stroese8749cfb2003-05-23 11:25:57 +0000416 clk = gd->cpu_clk;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417 tmp = CONFIG_SYS_BASE_BAUD * 16;
stroese8749cfb2003-05-23 11:25:57 +0000418 udiv = (clk + tmp / 2) / tmp;
419 if (udiv > UDIV_MAX) /* max. n bits for udiv */
420 udiv = UDIV_MAX;
421 reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
422 reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200423 mtdcr (CPC0_UCR, reg);
stroese8749cfb2003-05-23 11:25:57 +0000424#else /* CONFIG_405EP */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200425 reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
427 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
wdenkfe8c2802002-11-03 00:38:21 +0000428 udiv = 1;
429 reg |= CR0_EXTCLK_ENA;
430#else
431 clk = gd->cpu_clk;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#ifdef CONFIG_SYS_405_UART_ERRATA_59
wdenkfe8c2802002-11-03 00:38:21 +0000433 udiv = 31; /* Errata 59: stuck at 31 */
434#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435 tmp = CONFIG_SYS_BASE_BAUD * 16;
wdenkfe8c2802002-11-03 00:38:21 +0000436 udiv = (clk + tmp / 2) / tmp;
stroese8749cfb2003-05-23 11:25:57 +0000437 if (udiv > UDIV_MAX) /* max. n bits for udiv */
438 udiv = UDIV_MAX;
wdenkfe8c2802002-11-03 00:38:21 +0000439#endif
440#endif
wdenkfe8c2802002-11-03 00:38:21 +0000441 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200442 mtdcr (CPC0_CR0, reg);
stroese8749cfb2003-05-23 11:25:57 +0000443#endif /* CONFIG_405EP */
wdenkfe8c2802002-11-03 00:38:21 +0000444 tmp = gd->baudrate * udiv * 16;
445 bdiv = (clk + tmp / 2) / tmp;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200446#endif /* CONFIG_405EX */
wdenkfe8c2802002-11-03 00:38:21 +0000447
Stefan Roese3248f632007-10-22 16:22:40 +0200448 serial_init_common(base, udiv, bdiv);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200449
wdenkfe8c2802002-11-03 00:38:21 +0000450 return (0);
451}
452
453#endif /* if defined(CONFIG_440) */
454
Stefan Roese3248f632007-10-22 16:22:40 +0200455void serial_setbrg_dev(unsigned long base)
wdenkfe8c2802002-11-03 00:38:21 +0000456{
Stefan Roese3248f632007-10-22 16:22:40 +0200457 serial_init_dev(base);
wdenkfe8c2802002-11-03 00:38:21 +0000458}
459
Stefan Roese3248f632007-10-22 16:22:40 +0200460void serial_putc_dev(unsigned long base, const char c)
wdenkfe8c2802002-11-03 00:38:21 +0000461{
462 int i;
463
464 if (c == '\n')
Stefan Roese3248f632007-10-22 16:22:40 +0200465 serial_putc_dev(base, '\r');
wdenkfe8c2802002-11-03 00:38:21 +0000466
467 /* check THRE bit, wait for transmiter available */
468 for (i = 1; i < 3500; i++) {
Stefan Roese3248f632007-10-22 16:22:40 +0200469 if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
wdenkfe8c2802002-11-03 00:38:21 +0000470 break;
471 udelay (100);
472 }
Stefan Roese3248f632007-10-22 16:22:40 +0200473
474 out_8((u8 *)base + UART_THR, c); /* put character out */
wdenkfe8c2802002-11-03 00:38:21 +0000475}
476
Stefan Roese3248f632007-10-22 16:22:40 +0200477void serial_puts_dev (unsigned long base, const char *s)
wdenkfe8c2802002-11-03 00:38:21 +0000478{
Stefan Roese3248f632007-10-22 16:22:40 +0200479 while (*s)
480 serial_putc_dev (base, *s++);
wdenkfe8c2802002-11-03 00:38:21 +0000481}
482
Stefan Roese3248f632007-10-22 16:22:40 +0200483int serial_getc_dev (unsigned long base)
wdenkfe8c2802002-11-03 00:38:21 +0000484{
485 unsigned char status = 0;
486
487 while (1) {
488#if defined(CONFIG_HW_WATCHDOG)
489 WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
490#endif /* CONFIG_HW_WATCHDOG */
Stefan Roese3248f632007-10-22 16:22:40 +0200491
492 status = in_8((u8 *)base + UART_LSR);
493 if ((status & asyncLSRDataReady1) != 0x0)
wdenkfe8c2802002-11-03 00:38:21 +0000494 break;
Stefan Roese3248f632007-10-22 16:22:40 +0200495
wdenkfe8c2802002-11-03 00:38:21 +0000496 if ((status & ( asyncLSRFramingError1 |
497 asyncLSROverrunError1 |
498 asyncLSRParityError1 |
499 asyncLSRBreakInterrupt1 )) != 0) {
Stefan Roese3248f632007-10-22 16:22:40 +0200500 out_8((u8 *)base + UART_LSR,
wdenkfe8c2802002-11-03 00:38:21 +0000501 asyncLSRFramingError1 |
502 asyncLSROverrunError1 |
503 asyncLSRParityError1 |
504 asyncLSRBreakInterrupt1);
505 }
506 }
Stefan Roese3248f632007-10-22 16:22:40 +0200507
508 return (0x000000ff & (int) in_8((u8 *)base));
wdenkfe8c2802002-11-03 00:38:21 +0000509}
510
Stefan Roese3248f632007-10-22 16:22:40 +0200511int serial_tstc_dev (unsigned long base)
wdenkfe8c2802002-11-03 00:38:21 +0000512{
513 unsigned char status;
514
Stefan Roese3248f632007-10-22 16:22:40 +0200515 status = in_8((u8 *)base + UART_LSR);
516 if ((status & asyncLSRDataReady1) != 0x0)
wdenkfe8c2802002-11-03 00:38:21 +0000517 return (1);
Stefan Roese3248f632007-10-22 16:22:40 +0200518
wdenkfe8c2802002-11-03 00:38:21 +0000519 if ((status & ( asyncLSRFramingError1 |
520 asyncLSROverrunError1 |
521 asyncLSRParityError1 |
522 asyncLSRBreakInterrupt1 )) != 0) {
Stefan Roese3248f632007-10-22 16:22:40 +0200523 out_8((u8 *)base + UART_LSR,
wdenkfe8c2802002-11-03 00:38:21 +0000524 asyncLSRFramingError1 |
525 asyncLSROverrunError1 |
526 asyncLSRParityError1 |
527 asyncLSRBreakInterrupt1);
528 }
Stefan Roese3248f632007-10-22 16:22:40 +0200529
wdenkfe8c2802002-11-03 00:38:21 +0000530 return 0;
531}
532
wdenk42dfe7a2004-03-14 22:25:36 +0000533#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
wdenkfe8c2802002-11-03 00:38:21 +0000534
535void serial_isr (void *arg)
536{
537 int space;
538 int c;
539 const int rx_get = buf_info.rx_get;
540 int rx_put = buf_info.rx_put;
541
Stefan Roese3248f632007-10-22 16:22:40 +0200542 if (rx_get <= rx_put)
wdenkfe8c2802002-11-03 00:38:21 +0000543 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
Stefan Roese3248f632007-10-22 16:22:40 +0200544 else
wdenkfe8c2802002-11-03 00:38:21 +0000545 space = rx_get - rx_put;
Stefan Roese3248f632007-10-22 16:22:40 +0200546
wdenkff36fd82005-01-09 22:28:56 +0000547 while (serial_tstc_dev (ACTING_UART0_BASE)) {
548 c = serial_getc_dev (ACTING_UART0_BASE);
wdenkfe8c2802002-11-03 00:38:21 +0000549 if (space) {
550 buf_info.rx_buffer[rx_put++] = c;
551 space--;
552 }
553 if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
554 rx_put = 0;
555 if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
556 /* Stop flow by setting RTS inactive */
Stefan Roese3248f632007-10-22 16:22:40 +0200557 out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
558 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
559 (0xFF ^ 0x02));
wdenkfe8c2802002-11-03 00:38:21 +0000560 }
561 }
562 buf_info.rx_put = rx_put;
563}
564
565void serial_buffered_init (void)
566{
567 serial_puts ("Switching to interrupt driven serial input mode.\n");
568 buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
569 buf_info.rx_put = 0;
570 buf_info.rx_get = 0;
571
Stefan Roese3248f632007-10-22 16:22:40 +0200572 if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
wdenkfe8c2802002-11-03 00:38:21 +0000573 serial_puts ("Check CTS signal present on serial port: OK.\n");
Stefan Roese3248f632007-10-22 16:22:40 +0200574 else
wdenkfe8c2802002-11-03 00:38:21 +0000575 serial_puts ("WARNING: CTS signal not present on serial port.\n");
wdenkfe8c2802002-11-03 00:38:21 +0000576
577 irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
578 serial_isr /*interrupt_handler_t *handler */ ,
579 (void *) &buf_info /*void *arg */ );
580
581 /* Enable "RX Data Available" Interrupt on UART */
Stefan Roese3248f632007-10-22 16:22:40 +0200582 out_8(ACTING_UART0_BASE + UART_IER, 0x01);
wdenkfe8c2802002-11-03 00:38:21 +0000583 /* Set DTR active */
Stefan Roese3248f632007-10-22 16:22:40 +0200584 out_8(ACTING_UART0_BASE + UART_MCR,
585 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
wdenkfe8c2802002-11-03 00:38:21 +0000586 /* Start flow by setting RTS active */
Stefan Roese3248f632007-10-22 16:22:40 +0200587 out_8(ACTING_UART0_BASE + UART_MCR,
588 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
wdenkfe8c2802002-11-03 00:38:21 +0000589 /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
Stefan Roese3248f632007-10-22 16:22:40 +0200590 out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
wdenkfe8c2802002-11-03 00:38:21 +0000591}
592
593void serial_buffered_putc (const char c)
594{
595 /* Wait for CTS */
596#if defined(CONFIG_HW_WATCHDOG)
Stefan Roese3248f632007-10-22 16:22:40 +0200597 while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
wdenkfe8c2802002-11-03 00:38:21 +0000598 WATCHDOG_RESET ();
599#else
Stefan Roese3248f632007-10-22 16:22:40 +0200600 while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
wdenkfe8c2802002-11-03 00:38:21 +0000601#endif
602 serial_putc (c);
603}
604
605void serial_buffered_puts (const char *s)
606{
607 serial_puts (s);
608}
609
610int serial_buffered_getc (void)
611{
612 int space;
613 int c;
614 int rx_get = buf_info.rx_get;
615 int rx_put;
616
617#if defined(CONFIG_HW_WATCHDOG)
618 while (rx_get == buf_info.rx_put)
619 WATCHDOG_RESET ();
620#else
621 while (rx_get == buf_info.rx_put);
622#endif
623 c = buf_info.rx_buffer[rx_get++];
624 if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
625 rx_get = 0;
626 buf_info.rx_get = rx_get;
627
628 rx_put = buf_info.rx_put;
Stefan Roese3248f632007-10-22 16:22:40 +0200629 if (rx_get <= rx_put)
wdenkfe8c2802002-11-03 00:38:21 +0000630 space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
Stefan Roese3248f632007-10-22 16:22:40 +0200631 else
wdenkfe8c2802002-11-03 00:38:21 +0000632 space = rx_get - rx_put;
Stefan Roese3248f632007-10-22 16:22:40 +0200633
wdenkfe8c2802002-11-03 00:38:21 +0000634 if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
635 /* Start flow by setting RTS active */
Stefan Roese3248f632007-10-22 16:22:40 +0200636 out_8(ACTING_UART0_BASE + UART_MCR,
637 in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
wdenkfe8c2802002-11-03 00:38:21 +0000638 }
639
640 return c;
641}
642
643int serial_buffered_tstc (void)
644{
645 return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
646}
647
648#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
649
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -0500650#if defined(CONFIG_CMD_KGDB)
wdenkfe8c2802002-11-03 00:38:21 +0000651/*
652 AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
653 number 0 or number 1
654 - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
655 configuration has been already done
656 - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
657 configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
658*/
659#if (CONFIG_KGDB_SER_INDEX & 2)
660void kgdb_serial_init (void)
661{
Stefan Roese3248f632007-10-22 16:22:40 +0200662 u8 val;
663 u16 br_reg;
wdenkfe8c2802002-11-03 00:38:21 +0000664
665 get_clocks ();
666 br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
667 5) / 10;
668 /*
669 * Init onboard 16550 UART
670 */
Stefan Roese3248f632007-10-22 16:22:40 +0200671 out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
672 out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
673 out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
674 out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
675 out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
676 out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
677 val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
678 val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
679 out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
680 out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
wdenkfe8c2802002-11-03 00:38:21 +0000681}
682
wdenkfe8c2802002-11-03 00:38:21 +0000683void putDebugChar (const char c)
684{
685 if (c == '\n')
686 serial_putc ('\r');
687
Stefan Roese3248f632007-10-22 16:22:40 +0200688 out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
wdenkfe8c2802002-11-03 00:38:21 +0000689
690 /* check THRE bit, wait for transfer done */
Stefan Roese3248f632007-10-22 16:22:40 +0200691 while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
wdenkfe8c2802002-11-03 00:38:21 +0000692}
693
wdenkfe8c2802002-11-03 00:38:21 +0000694void putDebugStr (const char *s)
695{
Stefan Roese3248f632007-10-22 16:22:40 +0200696 while (*s)
wdenkfe8c2802002-11-03 00:38:21 +0000697 serial_putc (*s++);
wdenkfe8c2802002-11-03 00:38:21 +0000698}
699
wdenkfe8c2802002-11-03 00:38:21 +0000700int getDebugChar (void)
701{
702 unsigned char status = 0;
703
704 while (1) {
Stefan Roese3248f632007-10-22 16:22:40 +0200705 status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
706 if ((status & asyncLSRDataReady1) != 0x0)
wdenkfe8c2802002-11-03 00:38:21 +0000707 break;
Stefan Roese3248f632007-10-22 16:22:40 +0200708
709 if ((status & (asyncLSRFramingError1 |
710 asyncLSROverrunError1 |
711 asyncLSRParityError1 |
712 asyncLSRBreakInterrupt1 )) != 0) {
713 out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
wdenkfe8c2802002-11-03 00:38:21 +0000714 asyncLSRFramingError1 |
715 asyncLSROverrunError1 |
716 asyncLSRParityError1 |
717 asyncLSRBreakInterrupt1);
718 }
719 }
Stefan Roese3248f632007-10-22 16:22:40 +0200720
721 return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
wdenkfe8c2802002-11-03 00:38:21 +0000722}
723
wdenkfe8c2802002-11-03 00:38:21 +0000724void kgdb_interruptible (int yes)
725{
726 return;
727}
728
729#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
730
731void kgdb_serial_init (void)
732{
733 serial_printf ("[on serial] ");
734}
735
736void putDebugChar (int c)
737{
738 serial_putc (c);
739}
740
741void putDebugStr (const char *str)
742{
743 serial_puts (str);
744}
745
746int getDebugChar (void)
747{
748 return serial_getc ();
749}
750
751void kgdb_interruptible (int yes)
752{
753 return;
754}
755#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
Jon Loeliger068b60a2007-07-10 10:27:39 -0500756#endif
wdenkfe8c2802002-11-03 00:38:21 +0000757
wdenkff36fd82005-01-09 22:28:56 +0000758
759#if defined(CONFIG_SERIAL_MULTI)
760int serial0_init(void)
761{
762 return (serial_init_dev(UART0_BASE));
763}
764
765int serial1_init(void)
766{
767 return (serial_init_dev(UART1_BASE));
768}
Stefan Roese3248f632007-10-22 16:22:40 +0200769
wdenkff36fd82005-01-09 22:28:56 +0000770void serial0_setbrg (void)
771{
772 serial_setbrg_dev(UART0_BASE);
773}
Stefan Roese3248f632007-10-22 16:22:40 +0200774
wdenkff36fd82005-01-09 22:28:56 +0000775void serial1_setbrg (void)
776{
777 serial_setbrg_dev(UART1_BASE);
778}
779
780void serial0_putc(const char c)
781{
782 serial_putc_dev(UART0_BASE,c);
783}
784
785void serial1_putc(const char c)
786{
787 serial_putc_dev(UART1_BASE, c);
788}
Stefan Roese3248f632007-10-22 16:22:40 +0200789
wdenkff36fd82005-01-09 22:28:56 +0000790void serial0_puts(const char *s)
791{
792 serial_puts_dev(UART0_BASE, s);
793}
794
795void serial1_puts(const char *s)
796{
797 serial_puts_dev(UART1_BASE, s);
798}
799
800int serial0_getc(void)
801{
802 return(serial_getc_dev(UART0_BASE));
803}
804
805int serial1_getc(void)
806{
807 return(serial_getc_dev(UART1_BASE));
808}
Stefan Roese3248f632007-10-22 16:22:40 +0200809
wdenkff36fd82005-01-09 22:28:56 +0000810int serial0_tstc(void)
811{
812 return (serial_tstc_dev(UART0_BASE));
813}
814
815int serial1_tstc(void)
816{
817 return (serial_tstc_dev(UART1_BASE));
818}
819
820struct serial_device serial0_device =
821{
822 "serial0",
823 "UART0",
824 serial0_init,
825 serial0_setbrg,
826 serial0_getc,
827 serial0_tstc,
828 serial0_putc,
829 serial0_puts,
830};
831
832struct serial_device serial1_device =
833{
834 "serial1",
835 "UART1",
836 serial1_init,
837 serial1_setbrg,
838 serial1_getc,
839 serial1_tstc,
840 serial1_putc,
841 serial1_puts,
842};
Stefan Roese3248f632007-10-22 16:22:40 +0200843#else
844/*
845 * Wrapper functions
846 */
847int serial_init(void)
848{
849 return serial_init_dev(ACTING_UART0_BASE);
850}
851
852void serial_setbrg(void)
853{
854 serial_setbrg_dev(ACTING_UART0_BASE);
855}
856
857void serial_putc(const char c)
858{
859 serial_putc_dev(ACTING_UART0_BASE, c);
860}
861
862void serial_puts(const char *s)
863{
864 serial_puts_dev(ACTING_UART0_BASE, s);
865}
866
867int serial_getc(void)
868{
869 return serial_getc_dev(ACTING_UART0_BASE);
870}
871
872int serial_tstc(void)
873{
874 return serial_tstc_dev(ACTING_UART0_BASE);
875}
wdenkff36fd82005-01-09 22:28:56 +0000876#endif /* CONFIG_SERIAL_MULTI */
877
wdenkfe8c2802002-11-03 00:38:21 +0000878#endif /* CONFIG_405GP || CONFIG_405CR */