blob: c0487656d3f03a161109bc19aadef2199cbce510 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Shevchenko495f3772017-07-06 14:41:53 +03002/*
3 * Copyright (c) 2017 Intel Corporation
Andy Shevchenko495f3772017-07-06 14:41:53 +03004 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/include/ "skeleton.dtsi"
12/include/ "rtc.dtsi"
13/include/ "tsc_timer.dtsi"
14
15/ {
16 model = "Intel Edison";
17 compatible = "intel,edison";
18
19 aliases {
Andy Shevchenkod9b59fc2019-02-28 10:10:07 +020020 serial0 = &serial0;
21 serial1 = &serial1;
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020022 serial2 = &serial2;
Andy Shevchenko495f3772017-07-06 14:41:53 +030023 };
24
25 chosen {
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020026 stdout-path = &serial2;
Andy Shevchenko495f3772017-07-06 14:41:53 +030027 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "cpu-x86";
36 reg = <0>;
37 intel,apic-id = <0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "cpu-x86";
43 reg = <1>;
44 intel,apic-id = <2>;
45 };
46 };
47
48 pci {
49 compatible = "pci-x86";
50 #address-cells = <3>;
51 #size-cells = <2>;
52 u-boot,dm-pre-reloc;
53 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
54 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
55 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
56 };
57
Andy Shevchenkod9b59fc2019-02-28 10:10:07 +020058 serial0: serial@ff010080 {
59 compatible = "intel,mid-uart";
60 reg = <0xff010080 0x100>;
61 reg-shift = <0>;
62 clock-frequency = <29491200>;
63 current-speed = <115200>;
64 };
65
66 serial1: serial@ff010100 {
67 compatible = "intel,mid-uart";
68 reg = <0xff010100 0x100>;
69 reg-shift = <0>;
70 clock-frequency = <29491200>;
71 current-speed = <115200>;
72 };
73
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020074 serial2: serial@ff010180 {
Andy Shevchenko495f3772017-07-06 14:41:53 +030075 compatible = "intel,mid-uart";
76 reg = <0xff010180 0x100>;
77 reg-shift = <0>;
78 clock-frequency = <29491200>;
79 current-speed = <115200>;
80 };
81
82 emmc: mmc@ff3fc000 {
83 compatible = "intel,sdhci-tangier";
84 reg = <0xff3fc000 0x1000>;
85 };
86
87/*
88 * FIXME: For now U-Boot DM model doesn't allow to power up this controller.
89 * Enabling it will make U-Boot hang.
90 *
91 sdcard: mmc@ff3fa000 {
92 compatible = "intel,sdhci-tangier";
93 reg = <0xff3fa000 0x1000>;
94 };
95 */
96
97 pmu: power@ff00b000 {
98 compatible = "intel,pmu-mid";
99 reg = <0xff00b000 0x1000>;
100 };
101
102 scu: ipc@ff009000 {
103 compatible = "intel,scu-ipc";
104 reg = <0xff009000 0x1000>;
105 };
Bin Mengb37b7b22018-07-19 03:07:33 -0700106
Andy Shevchenkoc974a3d2019-06-21 13:28:08 +0300107 watchdog: wdt@0 {
108 compatible = "intel,tangier-wdt";
109 };
110
Bin Mengb37b7b22018-07-19 03:07:33 -0700111 reset {
112 compatible = "intel,reset-tangier";
113 u-boot,dm-pre-reloc;
114 };
Georgii Staroselskiif26b2602018-09-11 13:31:08 +0300115
116 pinctrl {
117 compatible = "intel,pinctrl-tangier";
118 reg = <0xff0c0000 0x8000>;
119
120 /*
121 * Initial configuration came from the firmware.
122 * Which quite likely has been used in the phones, where I2C #8,
123 * that is not part of Atom peripheral, is in use.
124 * Thus we need to override the leftover.
125 */
126 i2c6_scl@0 {
127 pad-offset = <111>;
128 mode-func = <1>;
129 protected;
130 };
131 i2c6_sda@0 {
132 pad-offset = <112>;
133 mode-func = <1>;
134 protected;
135 };
136 };
Andy Shevchenko495f3772017-07-06 14:41:53 +0300137};