blob: e91f5ae47aae8fb793eae4e732a1c7773b693299 [file] [log] [blame]
Wolfgang Denkeece1592005-08-10 11:03:05 +02001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkeece1592005-08-10 11:03:05 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 * (easy to change)
17 */
18
19#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
20#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
21#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
22#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
23#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
24#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +020027
Becky Bruce31d82672008-05-08 19:02:12 -050028#define CONFIG_HIGH_BATS 1 /* High BATs supported */
29
Wolfgang Denkeece1592005-08-10 11:03:05 +020030/*
31 * Serial console configuration
32 */
33#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
34#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkeece1592005-08-10 11:03:05 +020036
37#ifdef CONFIG_STK52XX
38#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
39#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
40#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
Wolfgang Denkeece1592005-08-10 11:03:05 +020042#define CONFIG_BOARD_EARLY_INIT_R
43#endif /* CONFIG_STK52XX */
44
45/*
46 * PCI Mapping:
47 * 0x40000000 - 0x4fffffff - PCI Memory
48 * 0x50000000 - 0x50ffffff - PCI IO Space
49 */
50#ifdef CONFIG_STK52XX
51#define CONFIG_PCI 1
52#define CONFIG_PCI_PNP 1
53/* #define CONFIG_PCI_SCAN_SHOW 1 */
54
55#define CONFIG_PCI_MEM_BUS 0x40000000
56#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
57#define CONFIG_PCI_MEM_SIZE 0x10000000
58
59#define CONFIG_PCI_IO_BUS 0x50000000
60#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
61#define CONFIG_PCI_IO_SIZE 0x01000000
62
Wolfgang Denkeece1592005-08-10 11:03:05 +020063#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Wolfgang Denkeece1592005-08-10 11:03:05 +020065#define CONFIG_NS8382X 1
66#endif /* CONFIG_STK52XX */
67
Wolfgang Denkeece1592005-08-10 11:03:05 +020068/*
69 * Video console
70 */
71#if 1
72#define CONFIG_VIDEO
73#define CONFIG_VIDEO_SM501
74#define CONFIG_VIDEO_SM501_32BPP
75#define CONFIG_CFB_CONSOLE
76#define CONFIG_VIDEO_LOGO
77#define CONFIG_VGA_AS_SINGLE_DEVICE
78#define CONFIG_CONSOLE_EXTRA_INFO
79#define CONFIG_VIDEO_SW_CURSOR
80#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Wolfgang Denkeece1592005-08-10 11:03:05 +020082#endif
83
Wolfgang Denkeece1592005-08-10 11:03:05 +020084/* Partitions */
85#define CONFIG_MAC_PARTITION
86#define CONFIG_DOS_PARTITION
87#define CONFIG_ISO_PARTITION
88
89/* USB */
90#ifdef CONFIG_STK52XX
91#define CONFIG_USB_OHCI
Wolfgang Denkeece1592005-08-10 11:03:05 +020092#define CONFIG_USB_STORAGE
Wolfgang Denkeece1592005-08-10 11:03:05 +020093#endif
94
95/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
97 CONFIG_SYS_POST_CPU | \
98 CONFIG_SYS_POST_I2C)
Wolfgang Denkeece1592005-08-10 11:03:05 +020099
100#ifdef CONFIG_POST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200101/* preserve space for the post_word at end of on-chip SRAM */
102#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200103#endif
104
Wolfgang Denkeece1592005-08-10 11:03:05 +0200105
106/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500107 * BOOTP options
108 */
109#define CONFIG_BOOTP_BOOTFILESIZE
110#define CONFIG_BOOTP_BOOTPATH
111#define CONFIG_BOOTP_GATEWAY
112#define CONFIG_BOOTP_HOSTNAME
113
114
115/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500116 * Command line configuration.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200117 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500118#include <config_cmd_default.h>
Wolfgang Denkeece1592005-08-10 11:03:05 +0200119
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500120#define CONFIG_CMD_ASKENV
121#define CONFIG_CMD_DATE
122#define CONFIG_CMD_DHCP
123#define CONFIG_CMD_ECHO
124#define CONFIG_CMD_EEPROM
125#define CONFIG_CMD_I2C
126#define CONFIG_CMD_MII
127#define CONFIG_CMD_NFS
128#define CONFIG_CMD_PING
129#define CONFIG_CMD_REGINFO
130#define CONFIG_CMD_SNTP
131
Jon Loeliger46da1e92007-07-04 22:33:30 -0500132#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
133 #define CONFIG_CMD_IDE
134 #define CONFIG_CMD_FAT
135 #define CONFIG_CMD_EXT2
136#endif
137
138#ifdef CONFIG_STK52XX
139 #define CONFIG_CMD_USB
140 #define CONFIG_CMD_FAT
141#endif
142
143#ifdef CONFIG_VIDEO
144 #define CONFIG_CMD_BMP
145#endif
146
147#ifdef CONFIG_PCI
148 #define CONFIG_CMD_PCI
TsiChung Liewf33fca22008-03-30 01:19:06 -0500149 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Jon Loeliger46da1e92007-07-04 22:33:30 -0500150#endif
151
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500152#ifdef CONFIG_POST
153#define CONFIG_CMD_DIAG
154#endif
Jon Loeliger46da1e92007-07-04 22:33:30 -0500155
Wolfgang Denkeece1592005-08-10 11:03:05 +0200156
157#define CONFIG_TIMESTAMP /* display image timestamps */
158
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200159#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160# define CONFIG_SYS_LOWBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200161#endif
162
163/*
164 * Autobooting
165 */
166#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
167
168#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100169 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200170 "echo"
171
172#undef CONFIG_BOOTARGS
173
Wolfgang Denkeece1592005-08-10 11:03:05 +0200174#define CONFIG_EXTRA_ENV_SETTINGS \
175 "netdev=eth0\0" \
176 "rootpath=/opt/eldk/ppc_6xx\0" \
177 "ramargs=setenv bootargs root=/dev/ram rw\0" \
178 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100179 "nfsroot=${serverip}:${rootpath}\0" \
180 "addip=setenv bootargs ${bootargs} " \
181 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
182 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200183 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100184 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200185 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100186 "bootm ${kernel_addr}\0" \
187 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200188 "bootfile=/tftpboot/tqm5200/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100189 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denkcd65a3d2006-06-16 16:11:34 +0200190 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200191 "update=protect off FC000000 FC05FFFF;" \
192 "erase FC000000 FC05FFFF;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100193 "cp.b 200000 FC000000 ${filesize};" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200194 "protect on FC000000 FC05FFFF\0" \
195 ""
196
197#define CONFIG_BOOTCOMMAND "run net_nfs"
198
199/*
200 * IPB Bus clocking configuration.
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200205/*
206 * PCI Bus clocking configuration
207 *
208 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200210 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200213#endif
214
215/*
216 * I2C configuration
217 */
218#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
219#ifdef CONFIG_TQM5200_REV100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200221#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200223#endif
224
225/*
226 * I2C clock frequency
227 *
228 * Please notice, that the resulting clock frequency could differ from the
229 * configured value. This is because the I2C clock is derived from system
230 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
Wolfgang Denkeece1592005-08-10 11:03:05 +0200232 * approximation allways lies below the configured value, never above.
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
235#define CONFIG_SYS_I2C_SLAVE 0x7F
Wolfgang Denkeece1592005-08-10 11:03:05 +0200236
237/*
238 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
239 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
240 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
241 * same configuration could be used.
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
244#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
245#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
246#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Wolfgang Denkeece1592005-08-10 11:03:05 +0200247
248/*
249 * HW-Monitor configuration on Mini-FAP
250 */
251#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
Wolfgang Denkeece1592005-08-10 11:03:05 +0200253#endif
254
255/* List of I2C addresses to be verified by POST */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200256#if defined (CONFIG_MINIFAP)
Peter Tyser60aaaa02010-10-22 00:20:30 -0500257#undef CONFIG_SYS_POST_I2C_ADDRS
258#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
259 CONFIG_SYS_I2C_HWMON_ADDR, \
260 CONFIG_SYS_I2C_SLAVE}
Wolfgang Denkeece1592005-08-10 11:03:05 +0200261#endif
262
263/*
264 * Flash configuration
265 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200266#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200267
268/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200270#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
272#define CONFIG_SYS_FLASH_EMPTY_INFO
273#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
274#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
275#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#if !defined(CONFIG_SYS_LOWBOOT)
278#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
279#else /* CONFIG_SYS_LOWBOOT */
280#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
281#endif /* CONFIG_SYS_LOWBOOT */
282#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Wolfgang Denkeece1592005-08-10 11:03:05 +0200283 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
285#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200286
287
288/*
289 * Environment settings
290 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200291#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200292#define CONFIG_ENV_SIZE 0x10000
293#define CONFIG_ENV_SECT_SIZE 0x20000
294#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
295#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200296
297/*
298 * Memory map
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_MBAR 0xF0000000
301#define CONFIG_SYS_SDRAM_BASE 0x00000000
302#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200303
304/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denkeece1592005-08-10 11:03:05 +0200306#ifdef CONFIG_POST
307/* preserve space for the post_word at end of on-chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200308#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200309#else
Wolfgang Denk553f0982010-10-26 13:32:32 +0200310#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200311#endif
312
313
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200314#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkeece1592005-08-10 11:03:05 +0200316
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200317#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
319# define CONFIG_SYS_RAMBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200320#endif
321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
323#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
324#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200325
326/*
327 * Ethernet configuration
328 */
329#define CONFIG_MPC5xxx_FEC 1
330/*
331 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
332 */
333/* #define CONFIG_FEC_10MBIT 1 */
334#define CONFIG_PHY_ADDR 0x00
335
336/*
337 * GPIO configuration
338 *
339 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
340 * Bit 0 (mask: 0x80000000): 1
341 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
342 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
343 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
344 * Use for REV200 STK52XX boards. Do not use with REV100 modules
345 * (because, there I2C1 is used as I2C bus)
346 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
347 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
348 * 000 -> All PSC2 pins are GIOPs
349 * 001 -> CAN1/2 on PSC2 pins
350 * Use for REV100 STK52xx boards
351 * use PSC6:
352 * on STK52xx:
353 * use as UART. Pins PSC6_0 to PSC6_3 are used.
354 * Bits 9:11 (mask: 0x00700000):
355 * 101 -> PSC6 : Extended POST test is not available
356 * on MINI-FAP and TQM5200_IB:
357 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
358 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
359 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
360 * tests.
361 */
362#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200364#elif defined (CONFIG_STK52XX)
365# if defined (CONFIG_STK52XX_REV100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
Wolfgang Denkeece1592005-08-10 11:03:05 +0200367# else /* STK52xx REV200 and above */
368# if defined (CONFIG_TQM5200_REV100)
369# error TQM5200 REV100 not supported on STK52XX REV200 or above
370# else/* TQM5200 REV200 and above */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200372# endif
373# endif
374#else /* TMQ5200 Inbetriebnahme-Board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200376#endif
377
378/*
379 * RTC configuration
380 */
381#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
382
383/*
384 * Miscellaneous configurable options
385 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_LONGHELP /* undef to save memory */
387#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500388#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200390#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200392#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
394#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
395#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200396
397/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_ALT_MEMTEST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
401#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500408#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500410#endif
411
Wolfgang Denkeece1592005-08-10 11:03:05 +0200412/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500413 * Enable loopw command.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200414 */
415#define CONFIG_LOOPW
416
417/*
418 * Various low-level settings
419 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
421#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200422
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
424#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
425#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
426#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200427#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200429#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
431#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200432
Wolfgang Denkeece1592005-08-10 11:03:05 +0200433#define CONFIG_LAST_STAGE_INIT
Wolfgang Denkeece1592005-08-10 11:03:05 +0200434
435/*
436 * SRAM - Do not map below 2 GB in address space, because this area is used
437 * for SDRAM autosizing.
438 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_CS2_START 0xE5000000
440#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
441#define CONFIG_SYS_CS2_CFG 0x0004D930
Wolfgang Denkeece1592005-08-10 11:03:05 +0200442
443/*
444 * Grafic controller - Do not map below 2 GB in address space, because this
445 * area is used for SDRAM autosizing.
446 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200447#define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
449#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
450#define CONFIG_SYS_CS1_CFG 0x8F48FF70
451#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_CS_BURST 0x00000000
454#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200455
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200457
458/*-----------------------------------------------------------------------
459 * USB stuff
460 *-----------------------------------------------------------------------
461 */
462#define CONFIG_USB_CLOCK 0x0001BBBB
463#define CONFIG_USB_CONFIG 0x00001000
464
465/*-----------------------------------------------------------------------
466 * IDE/ATA stuff Supports IDE harddisk
467 *-----------------------------------------------------------------------
468 */
469
470#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
471
472#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
473#undef CONFIG_IDE_LED /* LED for ide not supported */
474
475#define CONFIG_IDE_RESET /* reset for ide supported */
476#define CONFIG_IDE_PREINIT
477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
479#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200480
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200482
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Wolfgang Denkeece1592005-08-10 11:03:05 +0200484
485/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200487
488/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200490
491/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200493
494/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_ATA_STRIDE 4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200496
497#endif /* __CONFIG_H */