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Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05301/*
2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
4 *
Michal Simek05e7ca62015-07-22 11:18:43 +02005 * Copyright (C) 2011 - 2015 Xilinx
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +05306 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "xlnx,zynq-7000";
Masahiro Yamada580a54c2014-05-15 20:37:53 +090013
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 clocks = <&clkc 3>;
23 clock-latency = <1000>;
Michal Simekbece06c2015-07-22 10:38:45 +020024 cpu0-supply = <&regulator_vccpint>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +090025 operating-points = <
26 /* kHz uV */
27 666667 1000000
28 333334 1000000
Masahiro Yamada580a54c2014-05-15 20:37:53 +090029 >;
30 };
31
32 cpu@1 {
33 compatible = "arm,cortex-a9";
34 device_type = "cpu";
35 reg = <1>;
36 clocks = <&clkc 3>;
37 };
38 };
39
40 pmu {
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <0 5 4>, <0 6 4>;
43 interrupt-parent = <&intc>;
44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
45 };
46
Michal Simekbece06c2015-07-22 10:38:45 +020047 regulator_vccpint: fixedregulator@0 {
48 compatible = "regulator-fixed";
49 regulator-name = "VCCPINT";
50 regulator-min-microvolt = <1000000>;
51 regulator-max-microvolt = <1000000>;
52 regulator-boot-on;
53 regulator-always-on;
54 };
55
Michal Simek461c3882015-07-22 11:08:40 +020056 amba: amba {
Masahiro Yamada580a54c2014-05-15 20:37:53 +090057 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 interrupt-parent = <&intc>;
61 ranges;
62
Michal Simekfb1a5062015-07-22 10:32:05 +020063 adc: adc@f8007100 {
64 compatible = "xlnx,zynq-xadc-1.00.a";
65 reg = <0xf8007100 0x20>;
66 interrupts = <0 7 4>;
67 interrupt-parent = <&intc>;
68 clocks = <&clkc 12>;
69 };
70
71 can0: can@e0008000 {
72 compatible = "xlnx,zynq-can-1.0";
73 status = "disabled";
74 clocks = <&clkc 19>, <&clkc 36>;
75 clock-names = "can_clk", "pclk";
76 reg = <0xe0008000 0x1000>;
77 interrupts = <0 28 4>;
78 interrupt-parent = <&intc>;
79 tx-fifo-depth = <0x40>;
80 rx-fifo-depth = <0x40>;
81 };
82
83 can1: can@e0009000 {
84 compatible = "xlnx,zynq-can-1.0";
85 status = "disabled";
86 clocks = <&clkc 20>, <&clkc 37>;
87 clock-names = "can_clk", "pclk";
88 reg = <0xe0009000 0x1000>;
89 interrupts = <0 51 4>;
90 interrupt-parent = <&intc>;
91 tx-fifo-depth = <0x40>;
92 rx-fifo-depth = <0x40>;
93 };
94
95 gpio0: gpio@e000a000 {
96 compatible = "xlnx,zynq-gpio-1.0";
97 #gpio-cells = <2>;
98 clocks = <&clkc 42>;
99 gpio-controller;
100 interrupt-parent = <&intc>;
101 interrupts = <0 20 4>;
102 reg = <0xe000a000 0x1000>;
103 };
104
Michal Simeka0cb47f2015-07-22 10:28:48 +0200105 i2c0: i2c@e0004000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900106 compatible = "cdns,i2c-r1p10";
107 status = "disabled";
108 clocks = <&clkc 38>;
109 interrupt-parent = <&intc>;
110 interrupts = <0 25 4>;
111 reg = <0xe0004000 0x1000>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 };
115
Michal Simeka0cb47f2015-07-22 10:28:48 +0200116 i2c1: i2c@e0005000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900117 compatible = "cdns,i2c-r1p10";
118 status = "disabled";
119 clocks = <&clkc 39>;
120 interrupt-parent = <&intc>;
121 interrupts = <0 48 4>;
122 reg = <0xe0005000 0x1000>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 };
126
127 intc: interrupt-controller@f8f01000 {
128 compatible = "arm,cortex-a9-gic";
129 #interrupt-cells = <3>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900130 interrupt-controller;
131 reg = <0xF8F01000 0x1000>,
132 <0xF8F00100 0x100>;
133 };
134
Michal Simeka0cb47f2015-07-22 10:28:48 +0200135 L2: cache-controller@f8f02000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900136 compatible = "arm,pl310-cache";
137 reg = <0xF8F02000 0x1000>;
Michal Simekd50cb3d2015-07-22 11:26:08 +0200138 interrupts = <0 2 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900139 arm,data-latency = <3 2 2>;
140 arm,tag-latency = <2 2 2>;
141 cache-unified;
142 cache-level = <2>;
143 };
144
Michal Simekfb1a5062015-07-22 10:32:05 +0200145 mc: memory-controller@f8006000 {
146 compatible = "xlnx,zynq-ddrc-a05";
147 reg = <0xf8006000 0x1000>;
148 };
149
Michal Simeka0cb47f2015-07-22 10:28:48 +0200150 uart0: serial@e0000000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200151 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900152 status = "disabled";
153 clocks = <&clkc 23>, <&clkc 40>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200154 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900155 reg = <0xE0000000 0x1000>;
156 interrupts = <0 27 4>;
157 };
158
Michal Simeka0cb47f2015-07-22 10:28:48 +0200159 uart1: serial@e0001000 {
Michal Simek8a8c46a2015-07-22 10:40:51 +0200160 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900161 status = "disabled";
162 clocks = <&clkc 24>, <&clkc 41>;
Michal Simek8a8c46a2015-07-22 10:40:51 +0200163 clock-names = "uart_clk", "pclk";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900164 reg = <0xE0001000 0x1000>;
165 interrupts = <0 50 4>;
166 };
167
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530168 spi0: spi@e0006000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200169 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530170 reg = <0xe0006000 0x1000>;
171 status = "disabled";
172 interrupt-parent = <&intc>;
173 interrupts = <0 26 4>;
174 clocks = <&clkc 25>, <&clkc 34>;
175 clock-names = "ref_clk", "pclk";
Jagan Tekicdc9dd02015-06-27 00:51:34 +0530176 spi-max-frequency = <166666700>;
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530177 #address-cells = <1>;
178 #size-cells = <0>;
179 };
180
181 spi1: spi@e0007000 {
Michal Simek40b383f2015-07-22 10:47:33 +0200182 compatible = "xlnx,zynq-spi-r1p6";
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530183 reg = <0xe0007000 0x1000>;
184 status = "disabled";
185 interrupt-parent = <&intc>;
186 interrupts = <0 49 4>;
187 clocks = <&clkc 26>, <&clkc 35>;
188 clock-names = "ref_clk", "pclk";
Jagan Tekicdc9dd02015-06-27 00:51:34 +0530189 spi-max-frequency = <166666700>;
Jagan Tekia8a8fc92015-06-27 00:51:33 +0530190 #address-cells = <1>;
191 #size-cells = <0>;
192 };
193
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900194 gem0: ethernet@e000b000 {
Michal Simek7e163362015-07-22 10:51:16 +0200195 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200196 reg = <0xe000b000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900197 status = "disabled";
198 interrupts = <0 22 4>;
199 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
200 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200201 #address-cells = <1>;
202 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900203 };
204
205 gem1: ethernet@e000c000 {
Michal Simek7e163362015-07-22 10:51:16 +0200206 compatible = "cdns,zynq-gem", "cdns,gem";
Michal Simek08305fe2015-07-22 10:50:02 +0200207 reg = <0xe000c000 0x1000>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900208 status = "disabled";
209 interrupts = <0 45 4>;
210 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
211 clock-names = "pclk", "hclk", "tx_clk";
Michal Simek5ee236a2015-07-22 11:03:36 +0200212 #address-cells = <1>;
213 #size-cells = <0>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900214 };
215
Michal Simeka0cb47f2015-07-22 10:28:48 +0200216 sdhci0: sdhci@e0100000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900217 compatible = "arasan,sdhci-8.9a";
218 status = "disabled";
219 clock-names = "clk_xin", "clk_ahb";
220 clocks = <&clkc 21>, <&clkc 32>;
221 interrupt-parent = <&intc>;
222 interrupts = <0 24 4>;
223 reg = <0xe0100000 0x1000>;
224 } ;
225
Michal Simeka0cb47f2015-07-22 10:28:48 +0200226 sdhci1: sdhci@e0101000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900227 compatible = "arasan,sdhci-8.9a";
228 status = "disabled";
229 clock-names = "clk_xin", "clk_ahb";
230 clocks = <&clkc 22>, <&clkc 33>;
231 interrupt-parent = <&intc>;
232 interrupts = <0 47 4>;
233 reg = <0xe0101000 0x1000>;
234 } ;
235
236 slcr: slcr@f8000000 {
237 #address-cells = <1>;
238 #size-cells = <1>;
Michal Simeke913ce22015-07-22 11:07:49 +0200239 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900240 reg = <0xF8000000 0x1000>;
241 ranges;
242 clkc: clkc@100 {
243 #clock-cells = <1>;
244 compatible = "xlnx,ps7-clkc";
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900245 fclk-enable = <0>;
246 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
247 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
248 "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
249 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
250 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
251 "dma", "usb0_aper", "usb1_aper", "gem0_aper",
252 "gem1_aper", "sdio0_aper", "sdio1_aper",
253 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
254 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
255 "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
256 "dbg_trc", "dbg_apb";
257 reg = <0x100 0x100>;
258 };
Michal Simeke913ce22015-07-22 11:07:49 +0200259
260 pinctrl0: pinctrl@700 {
261 compatible = "xlnx,pinctrl-zynq";
262 reg = <0x700 0x200>;
263 syscon = <&slcr>;
264 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900265 };
266
Michal Simekfb1a5062015-07-22 10:32:05 +0200267 dmac_s: dmac@f8003000 {
268 compatible = "arm,pl330", "arm,primecell";
269 reg = <0xf8003000 0x1000>;
270 interrupt-parent = <&intc>;
271 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
272 "dma4", "dma5", "dma6", "dma7";
273 interrupts = <0 13 4>,
274 <0 14 4>, <0 15 4>,
275 <0 16 4>, <0 17 4>,
276 <0 40 4>, <0 41 4>,
277 <0 42 4>, <0 43 4>;
278 #dma-cells = <1>;
279 #dma-channels = <8>;
280 #dma-requests = <4>;
281 clocks = <&clkc 27>;
282 clock-names = "apb_pclk";
283 };
284
285 devcfg: devcfg@f8007000 {
286 compatible = "xlnx,zynq-devcfg-1.0";
287 reg = <0xf8007000 0x100>;
288 };
289
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900290 global_timer: timer@f8f00200 {
291 compatible = "arm,cortex-a9-global-timer";
292 reg = <0xf8f00200 0x20>;
293 interrupts = <1 11 0x301>;
294 interrupt-parent = <&intc>;
295 clocks = <&clkc 4>;
296 };
297
Michal Simeka0cb47f2015-07-22 10:28:48 +0200298 ttc0: timer@f8001000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900299 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200300 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900301 compatible = "cdns,ttc";
302 clocks = <&clkc 6>;
303 reg = <0xF8001000 0x1000>;
304 };
305
Michal Simeka0cb47f2015-07-22 10:28:48 +0200306 ttc1: timer@f8002000 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900307 interrupt-parent = <&intc>;
Michal Simekb346bd12015-07-22 10:57:51 +0200308 interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900309 compatible = "cdns,ttc";
310 clocks = <&clkc 6>;
311 reg = <0xF8002000 0x1000>;
312 };
Michal Simekfb1a5062015-07-22 10:32:05 +0200313
Michal Simeka0cb47f2015-07-22 10:28:48 +0200314 scutimer: timer@f8f00600 {
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900315 interrupt-parent = <&intc>;
316 interrupts = < 1 13 0x301 >;
317 compatible = "arm,cortex-a9-twd-timer";
318 reg = < 0xf8f00600 0x20 >;
319 clocks = <&clkc 4>;
320 } ;
Michal Simekfb1a5062015-07-22 10:32:05 +0200321
322 usb0: usb@e0002000 {
323 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
324 status = "disabled";
325 clocks = <&clkc 28>;
326 interrupt-parent = <&intc>;
327 interrupts = <0 21 4>;
328 reg = <0xe0002000 0x1000>;
329 phy_type = "ulpi";
330 };
331
332 usb1: usb@e0003000 {
333 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
334 status = "disabled";
335 clocks = <&clkc 29>;
336 interrupt-parent = <&intc>;
337 interrupts = <0 44 4>;
338 reg = <0xe0003000 0x1000>;
339 phy_type = "ulpi";
340 };
341
342 watchdog0: watchdog@f8005000 {
343 clocks = <&clkc 45>;
344 compatible = "cdns,wdt-r1p2";
345 interrupt-parent = <&intc>;
346 interrupts = <0 9 1>;
347 reg = <0xf8005000 0x1000>;
348 timeout-sec = <10>;
349 };
Masahiro Yamada580a54c2014-05-15 20:37:53 +0900350 };
Jagannadha Sutradharudu Tekif8f36c52014-01-09 01:48:26 +0530351};