Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <i2c.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <asm/arch/immap_ls102xa.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/fsl_serdes.h> |
Minghuan Lian | da41902 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 13 | #include <asm/pcie_layerscape.h> |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 14 | #include <mmc.h> |
| 15 | #include <fsl_esdhc.h> |
| 16 | #include <fsl_ifc.h> |
Ruchika Gupta | 4ba4a09 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 17 | #include <fsl_sec.h> |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 18 | #include <spl.h> |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 19 | |
| 20 | #include "../common/qixis.h" |
| 21 | #include "ls1021aqds_qixis.h" |
Zhao Qiang | 63e75fd | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 22 | #ifdef CONFIG_U_QE |
| 23 | #include "../../../drivers/qe/qe.h" |
| 24 | #endif |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
| 28 | enum { |
| 29 | MUX_TYPE_SD_PCI4, |
| 30 | MUX_TYPE_SD_PC_SA_SG_SG, |
| 31 | MUX_TYPE_SD_PC_SA_PC_SG, |
| 32 | MUX_TYPE_SD_PC_SG_SG, |
| 33 | }; |
| 34 | |
| 35 | int checkboard(void) |
| 36 | { |
Alison Wang | d612f0a | 2014-12-09 17:38:02 +0800 | [diff] [blame^] | 37 | #ifndef CONFIG_QSPI_BOOT |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 38 | char buf[64]; |
Alison Wang | d612f0a | 2014-12-09 17:38:02 +0800 | [diff] [blame^] | 39 | #endif |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 40 | #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 41 | u8 sw; |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 42 | #endif |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 43 | |
| 44 | puts("Board: LS1021AQDS\n"); |
| 45 | |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 46 | #ifdef CONFIG_SD_BOOT |
| 47 | puts("SD\n"); |
| 48 | #elif CONFIG_QSPI_BOOT |
| 49 | puts("QSPI\n"); |
| 50 | #else |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 51 | sw = QIXIS_READ(brdcfg[0]); |
| 52 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
| 53 | |
| 54 | if (sw < 0x8) |
| 55 | printf("vBank: %d\n", sw); |
| 56 | else if (sw == 0x8) |
| 57 | puts("PromJet\n"); |
| 58 | else if (sw == 0x9) |
| 59 | puts("NAND\n"); |
| 60 | else if (sw == 0x15) |
| 61 | printf("IFCCard\n"); |
| 62 | else |
| 63 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 64 | #endif |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 65 | |
Alison Wang | d612f0a | 2014-12-09 17:38:02 +0800 | [diff] [blame^] | 66 | #ifndef CONFIG_QSPI_BOOT |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 67 | printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", |
| 68 | QIXIS_READ(id), QIXIS_READ(arch)); |
| 69 | |
| 70 | printf("FPGA: v%d (%s), build %d\n", |
| 71 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
| 72 | (int)qixis_read_minor()); |
Alison Wang | d612f0a | 2014-12-09 17:38:02 +0800 | [diff] [blame^] | 73 | #endif |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 74 | |
| 75 | return 0; |
| 76 | } |
| 77 | |
| 78 | unsigned long get_board_sys_clk(void) |
| 79 | { |
| 80 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
| 81 | |
| 82 | switch (sysclk_conf & 0x0f) { |
| 83 | case QIXIS_SYSCLK_64: |
| 84 | return 64000000; |
| 85 | case QIXIS_SYSCLK_83: |
| 86 | return 83333333; |
| 87 | case QIXIS_SYSCLK_100: |
| 88 | return 100000000; |
| 89 | case QIXIS_SYSCLK_125: |
| 90 | return 125000000; |
| 91 | case QIXIS_SYSCLK_133: |
| 92 | return 133333333; |
| 93 | case QIXIS_SYSCLK_150: |
| 94 | return 150000000; |
| 95 | case QIXIS_SYSCLK_160: |
| 96 | return 160000000; |
| 97 | case QIXIS_SYSCLK_166: |
| 98 | return 166666666; |
| 99 | } |
| 100 | return 66666666; |
| 101 | } |
| 102 | |
| 103 | unsigned long get_board_ddr_clk(void) |
| 104 | { |
| 105 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
| 106 | |
| 107 | switch ((ddrclk_conf & 0x30) >> 4) { |
| 108 | case QIXIS_DDRCLK_100: |
| 109 | return 100000000; |
| 110 | case QIXIS_DDRCLK_125: |
| 111 | return 125000000; |
| 112 | case QIXIS_DDRCLK_133: |
| 113 | return 133333333; |
| 114 | } |
| 115 | return 66666666; |
| 116 | } |
| 117 | |
Chenhui Zhao | afff137 | 2014-11-06 10:51:59 +0800 | [diff] [blame] | 118 | int select_i2c_ch_pca9547(u8 ch) |
| 119 | { |
| 120 | int ret; |
| 121 | |
| 122 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
| 123 | if (ret) { |
| 124 | puts("PCA: failed to select proper channel\n"); |
| 125 | return ret; |
| 126 | } |
| 127 | |
| 128 | return 0; |
| 129 | } |
| 130 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 131 | int dram_init(void) |
| 132 | { |
Chenhui Zhao | afff137 | 2014-11-06 10:51:59 +0800 | [diff] [blame] | 133 | /* |
| 134 | * When resuming from deep sleep, the I2C channel may not be |
| 135 | * in the default channel. So, switch to the default channel |
| 136 | * before accessing DDR SPD. |
| 137 | */ |
| 138 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 139 | gd->ram_size = initdram(0); |
| 140 | |
| 141 | return 0; |
| 142 | } |
| 143 | |
| 144 | #ifdef CONFIG_FSL_ESDHC |
| 145 | struct fsl_esdhc_cfg esdhc_cfg[1] = { |
| 146 | {CONFIG_SYS_FSL_ESDHC_ADDR}, |
| 147 | }; |
| 148 | |
| 149 | int board_mmc_init(bd_t *bis) |
| 150 | { |
| 151 | esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); |
| 152 | |
| 153 | return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); |
| 154 | } |
| 155 | #endif |
| 156 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 157 | int board_early_init_f(void) |
| 158 | { |
| 159 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 160 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
| 161 | |
| 162 | #ifdef CONFIG_TSEC_ENET |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 163 | out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); |
Alison Wang | 0ab1723 | 2014-10-17 15:26:36 +0800 | [diff] [blame] | 164 | out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 165 | #endif |
| 166 | |
| 167 | #ifdef CONFIG_FSL_IFC |
| 168 | init_early_memctl_regs(); |
| 169 | #endif |
| 170 | |
Alison Wang | d612f0a | 2014-12-09 17:38:02 +0800 | [diff] [blame^] | 171 | #ifdef CONFIG_FSL_QSPI |
| 172 | out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); |
| 173 | #endif |
| 174 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 175 | /* Workaround for the issue that DDR could not respond to |
| 176 | * barrier transaction which is generated by executing DSB/ISB |
| 177 | * instruction. Set CCI-400 control override register to |
| 178 | * terminate the barrier transaction. After DDR is initialized, |
| 179 | * allow barrier transaction to DDR again */ |
| 180 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); |
| 181 | |
| 182 | return 0; |
| 183 | } |
| 184 | |
Alison Wang | 86949c2 | 2014-12-03 15:00:47 +0800 | [diff] [blame] | 185 | #ifdef CONFIG_SPL_BUILD |
| 186 | void board_init_f(ulong dummy) |
| 187 | { |
| 188 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
| 189 | |
| 190 | /* Set global data pointer */ |
| 191 | gd = &gdata; |
| 192 | |
| 193 | /* Clear the BSS */ |
| 194 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 195 | |
| 196 | #ifdef CONFIG_FSL_IFC |
| 197 | init_early_memctl_regs(); |
| 198 | #endif |
| 199 | |
| 200 | get_clocks(); |
| 201 | |
| 202 | preloader_console_init(); |
| 203 | |
| 204 | #ifdef CONFIG_SPL_I2C_SUPPORT |
| 205 | i2c_init_all(); |
| 206 | #endif |
| 207 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); |
| 208 | |
| 209 | dram_init(); |
| 210 | |
| 211 | board_init_r(NULL, 0); |
| 212 | } |
| 213 | #endif |
| 214 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 215 | int config_board_mux(int ctrl_type) |
| 216 | { |
| 217 | u8 reg12; |
| 218 | |
| 219 | reg12 = QIXIS_READ(brdcfg[12]); |
| 220 | |
| 221 | switch (ctrl_type) { |
| 222 | case MUX_TYPE_SD_PCI4: |
| 223 | reg12 = 0x38; |
| 224 | break; |
| 225 | case MUX_TYPE_SD_PC_SA_SG_SG: |
| 226 | reg12 = 0x01; |
| 227 | break; |
| 228 | case MUX_TYPE_SD_PC_SA_PC_SG: |
| 229 | reg12 = 0x01; |
| 230 | break; |
| 231 | case MUX_TYPE_SD_PC_SG_SG: |
| 232 | reg12 = 0x21; |
| 233 | break; |
| 234 | default: |
| 235 | printf("Wrong mux interface type\n"); |
| 236 | return -1; |
| 237 | } |
| 238 | |
| 239 | QIXIS_WRITE(brdcfg[12], reg12); |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | int config_serdes_mux(void) |
| 245 | { |
| 246 | struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 247 | u32 cfg; |
| 248 | |
| 249 | cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; |
| 250 | cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; |
| 251 | |
| 252 | switch (cfg) { |
| 253 | case 0x0: |
| 254 | config_board_mux(MUX_TYPE_SD_PCI4); |
| 255 | break; |
| 256 | case 0x30: |
| 257 | config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); |
| 258 | break; |
| 259 | case 0x60: |
| 260 | config_board_mux(MUX_TYPE_SD_PC_SG_SG); |
| 261 | break; |
| 262 | case 0x70: |
| 263 | config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); |
| 264 | break; |
| 265 | default: |
| 266 | printf("SRDS1 prtcl:0x%x\n", cfg); |
| 267 | break; |
| 268 | } |
| 269 | |
| 270 | return 0; |
| 271 | } |
| 272 | |
Ruchika Gupta | 4ba4a09 | 2014-10-15 11:39:06 +0530 | [diff] [blame] | 273 | #if defined(CONFIG_MISC_INIT_R) |
| 274 | int misc_init_r(void) |
| 275 | { |
| 276 | #ifdef CONFIG_FSL_CAAM |
| 277 | return sec_init(); |
| 278 | #endif |
| 279 | } |
| 280 | #endif |
| 281 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 282 | int board_init(void) |
| 283 | { |
| 284 | struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; |
| 285 | |
| 286 | /* Set CCI-400 control override register to |
| 287 | * enable barrier transaction */ |
| 288 | out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); |
Jason Jin | 644bc7e | 2014-10-17 15:26:32 +0800 | [diff] [blame] | 289 | /* |
| 290 | * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register |
| 291 | * All transactions are treated as non-shareable |
| 292 | */ |
| 293 | out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE); |
| 294 | out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); |
| 295 | out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 296 | |
| 297 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
| 298 | |
| 299 | #ifndef CONFIG_SYS_FSL_NO_SERDES |
| 300 | fsl_serdes_init(); |
| 301 | config_serdes_mux(); |
| 302 | #endif |
Zhao Qiang | 63e75fd | 2014-09-26 16:25:32 +0800 | [diff] [blame] | 303 | |
| 304 | #ifdef CONFIG_U_QE |
| 305 | u_qe_init(); |
| 306 | #endif |
| 307 | |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 308 | return 0; |
| 309 | } |
| 310 | |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 311 | int ft_board_setup(void *blob, bd_t *bd) |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 312 | { |
| 313 | ft_cpu_setup(blob, bd); |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 314 | |
Minghuan Lian | da41902 | 2014-10-31 13:43:44 +0800 | [diff] [blame] | 315 | #ifdef CONFIG_PCIE_LAYERSCAPE |
| 316 | ft_pcie_setup(blob, bd); |
| 317 | #endif |
| 318 | |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 319 | return 0; |
Wang Huan | 550e3dc | 2014-09-05 13:52:44 +0800 | [diff] [blame] | 320 | } |
| 321 | |
| 322 | u8 flash_read8(void *addr) |
| 323 | { |
| 324 | return __raw_readb(addr + 1); |
| 325 | } |
| 326 | |
| 327 | void flash_write16(u16 val, void *addr) |
| 328 | { |
| 329 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
| 330 | |
| 331 | __raw_writew(shftval, addr); |
| 332 | } |
| 333 | |
| 334 | u16 flash_read16(void *addr) |
| 335 | { |
| 336 | u16 val = __raw_readw(addr); |
| 337 | |
| 338 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
| 339 | } |