Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2014 Google, Inc |
| 4 | * (C) Copyright 2008 |
| 5 | * Graeme Russ, graeme.russ@gmail.com. |
| 6 | * |
| 7 | * Some portions from coreboot src/mainboard/google/link/romstage.c |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 8 | * and src/cpu/intel/model_206ax/bootblock.c |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 9 | * Copyright (C) 2007-2010 coresystems GmbH |
| 10 | * Copyright (C) 2011 Google Inc. |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 11 | */ |
| 12 | |
Tom Rini | d678a59 | 2024-05-18 20:20:43 -0600 | [diff] [blame^] | 13 | #include <common.h> |
Simon Glass | 30c7c43 | 2019-11-14 12:57:34 -0700 | [diff] [blame] | 14 | #include <cpu_func.h> |
Simon Glass | aad78d2 | 2015-03-05 12:25:33 -0700 | [diff] [blame] | 15 | #include <dm.h> |
Simon Glass | 2b60515 | 2014-11-12 22:42:15 -0700 | [diff] [blame] | 16 | #include <errno.h> |
Simon Glass | 7fe32b3 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 17 | #include <event.h> |
Simon Glass | 2b60515 | 2014-11-12 22:42:15 -0700 | [diff] [blame] | 18 | #include <fdtdec.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 19 | #include <init.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 20 | #include <log.h> |
Simon Glass | 858361b | 2016-01-17 16:11:13 -0700 | [diff] [blame] | 21 | #include <pch.h> |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 22 | #include <asm/cpu.h> |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 23 | #include <asm/cpu_common.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 24 | #include <asm/global_data.h> |
Simon Glass | 06d336c | 2016-03-11 22:06:55 -0700 | [diff] [blame] | 25 | #include <asm/intel_regs.h> |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 26 | #include <asm/io.h> |
Simon Glass | 3eafce0 | 2014-11-12 22:42:27 -0700 | [diff] [blame] | 27 | #include <asm/lapic.h> |
Simon Glass | 7e4a6ae | 2016-03-16 07:44:36 -0600 | [diff] [blame] | 28 | #include <asm/lpc_common.h> |
Simon Glass | 9e66506 | 2016-03-11 22:06:54 -0700 | [diff] [blame] | 29 | #include <asm/microcode.h> |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 30 | #include <asm/msr.h> |
| 31 | #include <asm/mtrr.h> |
Simon Glass | 6e5b12b | 2014-11-12 22:42:13 -0700 | [diff] [blame] | 32 | #include <asm/pci.h> |
Simon Glass | 70a09c6 | 2014-11-12 22:42:10 -0700 | [diff] [blame] | 33 | #include <asm/post.h> |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 34 | #include <asm/processor.h> |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 35 | #include <asm/arch/model_206ax.h> |
Simon Glass | 2b60515 | 2014-11-12 22:42:15 -0700 | [diff] [blame] | 36 | #include <asm/arch/pch.h> |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 37 | #include <asm/arch/sandybridge.h> |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 38 | |
| 39 | DECLARE_GLOBAL_DATA_PTR; |
| 40 | |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 41 | static int set_flex_ratio_to_tdp_nominal(void) |
| 42 | { |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 43 | /* Minimum CPU revision for configurable TDP support */ |
| 44 | if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) |
| 45 | return -EINVAL; |
| 46 | |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 47 | return cpu_set_flex_ratio_to_tdp_nominal(); |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 48 | } |
| 49 | |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 50 | int arch_cpu_init(void) |
| 51 | { |
Simon Glass | 161d2e4 | 2015-03-05 12:25:17 -0700 | [diff] [blame] | 52 | post_code(POST_CPU_INIT); |
Simon Glass | 161d2e4 | 2015-03-05 12:25:17 -0700 | [diff] [blame] | 53 | |
| 54 | return x86_cpu_init_f(); |
| 55 | } |
| 56 | |
Simon Glass | f72d0d4 | 2023-08-21 21:16:56 -0600 | [diff] [blame] | 57 | static int ivybridge_cpu_init(void) |
Simon Glass | 161d2e4 | 2015-03-05 12:25:17 -0700 | [diff] [blame] | 58 | { |
Simon Glass | 6e5b12b | 2014-11-12 22:42:13 -0700 | [diff] [blame] | 59 | struct pci_controller *hose; |
Simon Glass | 4acc83d | 2016-01-17 16:11:10 -0700 | [diff] [blame] | 60 | struct udevice *bus, *dev; |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 61 | int ret; |
| 62 | |
Simon Glass | aad78d2 | 2015-03-05 12:25:33 -0700 | [diff] [blame] | 63 | post_code(0x70); |
| 64 | ret = uclass_get_device(UCLASS_PCI, 0, &bus); |
| 65 | post_code(0x71); |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 66 | if (ret) |
| 67 | return ret; |
Simon Glass | aad78d2 | 2015-03-05 12:25:33 -0700 | [diff] [blame] | 68 | post_code(0x72); |
| 69 | hose = dev_get_uclass_priv(bus); |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 70 | |
Simon Glass | aad78d2 | 2015-03-05 12:25:33 -0700 | [diff] [blame] | 71 | /* TODO(sjg@chromium.org): Get rid of gd->hose */ |
| 72 | gd->hose = hose; |
Simon Glass | 6e5b12b | 2014-11-12 22:42:13 -0700 | [diff] [blame] | 73 | |
Simon Glass | 3f603cb | 2016-02-11 13:23:26 -0700 | [diff] [blame] | 74 | ret = uclass_first_device_err(UCLASS_LPC, &dev); |
| 75 | if (ret) |
| 76 | return ret; |
Simon Glass | 4acc83d | 2016-01-17 16:11:10 -0700 | [diff] [blame] | 77 | |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 78 | /* |
| 79 | * We should do as little as possible before the serial console is |
| 80 | * up. Perhaps this should move to later. Our next lot of init |
Simon Glass | 76d1d02 | 2017-03-28 10:27:30 -0600 | [diff] [blame] | 81 | * happens in checkcpu() when we have a console |
Simon Glass | f5fbbe9 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 82 | */ |
| 83 | ret = set_flex_ratio_to_tdp_nominal(); |
| 84 | if (ret) |
| 85 | return ret; |
| 86 | |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 87 | return 0; |
| 88 | } |
Simon Glass | f72d0d4 | 2023-08-21 21:16:56 -0600 | [diff] [blame] | 89 | EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, ivybridge_cpu_init); |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 90 | |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 91 | #define PCH_EHCI0_TEMP_BAR0 0xe8000000 |
| 92 | #define PCH_EHCI1_TEMP_BAR0 0xe8000400 |
| 93 | #define PCH_XHCI_TEMP_BAR0 0xe8001000 |
| 94 | |
| 95 | /* |
| 96 | * Setup USB controller MMIO BAR to prevent the reference code from |
| 97 | * resetting the controller. |
| 98 | * |
| 99 | * The BAR will be re-assigned during device enumeration so these are only |
| 100 | * temporary. |
| 101 | * |
| 102 | * This is used to speed up the resume path. |
| 103 | */ |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 104 | static void enable_usb_bar(struct udevice *bus) |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 105 | { |
| 106 | pci_dev_t usb0 = PCH_EHCI1_DEV; |
| 107 | pci_dev_t usb1 = PCH_EHCI2_DEV; |
| 108 | pci_dev_t usb3 = PCH_XHCI_DEV; |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 109 | ulong cmd; |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 110 | |
| 111 | /* USB Controller 1 */ |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 112 | pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0, |
| 113 | PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32); |
| 114 | pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 115 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 116 | pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 117 | |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 118 | /* USB Controller 2 */ |
| 119 | pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0, |
| 120 | PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32); |
| 121 | pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 122 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 123 | pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 124 | |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 125 | /* USB3 Controller 1 */ |
| 126 | pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0, |
| 127 | PCH_XHCI_TEMP_BAR0, PCI_SIZE_32); |
| 128 | pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 129 | cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 130 | pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Simon Glass | 76d1d02 | 2017-03-28 10:27:30 -0600 | [diff] [blame] | 133 | int checkcpu(void) |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 134 | { |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 135 | enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; |
Simon Glass | f633efa | 2016-01-17 16:11:19 -0700 | [diff] [blame] | 136 | struct udevice *dev, *lpc; |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 137 | uint32_t pm1_cnt; |
| 138 | uint16_t pm1_sts; |
Simon Glass | 94060ff | 2014-11-12 22:42:20 -0700 | [diff] [blame] | 139 | int ret; |
| 140 | |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 141 | /* TODO: cmos_post_init() */ |
| 142 | if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) { |
| 143 | debug("soft reset detected\n"); |
| 144 | boot_mode = PEI_BOOT_SOFT_RESET; |
| 145 | |
| 146 | /* System is not happy after keyboard reset... */ |
| 147 | debug("Issuing CF9 warm reset\n"); |
Harald Seiler | 35b65dd | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 148 | reset_cpu(); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 149 | } |
| 150 | |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 151 | ret = cpu_common_init(); |
Simon Glass | 4cc00f0 | 2016-07-25 18:58:59 -0600 | [diff] [blame] | 152 | if (ret) { |
| 153 | debug("%s: cpu_common_init() failed\n", __func__); |
Simon Glass | 858361b | 2016-01-17 16:11:13 -0700 | [diff] [blame] | 154 | return ret; |
Simon Glass | 4cc00f0 | 2016-07-25 18:58:59 -0600 | [diff] [blame] | 155 | } |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 156 | |
| 157 | /* Check PM1_STS[15] to see if we are waking from Sx */ |
| 158 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 159 | |
| 160 | /* Read PM1_CNT[12:10] to determine which Sx state */ |
| 161 | pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); |
| 162 | |
| 163 | if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 164 | debug("Resume from S3 detected, but disabled.\n"); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 165 | } else { |
| 166 | /* |
| 167 | * TODO: An indication of life might be possible here (e.g. |
| 168 | * keyboard light) |
| 169 | */ |
| 170 | } |
| 171 | post_code(POST_EARLY_INIT); |
| 172 | |
| 173 | /* Enable SPD ROMs and DDR-III DRAM */ |
Simon Glass | 3f603cb | 2016-02-11 13:23:26 -0700 | [diff] [blame] | 174 | ret = uclass_first_device_err(UCLASS_I2C, &dev); |
Simon Glass | 8d8f3ac | 2017-01-16 07:03:38 -0700 | [diff] [blame] | 175 | if (ret) { |
| 176 | debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret); |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 177 | return ret; |
Simon Glass | 8d8f3ac | 2017-01-16 07:03:38 -0700 | [diff] [blame] | 178 | } |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 179 | |
| 180 | /* Prepare USB controller early in S3 resume */ |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 181 | if (boot_mode == PEI_BOOT_RESUME) { |
| 182 | uclass_first_device(UCLASS_LPC, &lpc); |
Simon Glass | 5213f28 | 2016-01-17 16:11:46 -0700 | [diff] [blame] | 183 | enable_usb_bar(pci_get_controller(lpc->parent)); |
Simon Glass | 50dd3da | 2016-03-11 22:06:58 -0700 | [diff] [blame] | 184 | } |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 185 | |
| 186 | gd->arch.pei_boot_mode = boot_mode; |
| 187 | |
Simon Glass | 76d1d02 | 2017-03-28 10:27:30 -0600 | [diff] [blame] | 188 | return 0; |
| 189 | } |
| 190 | |
| 191 | int print_cpuinfo(void) |
| 192 | { |
| 193 | char processor_name[CPU_MAX_NAME_LEN]; |
| 194 | const char *name; |
| 195 | |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 196 | /* Print processor name */ |
| 197 | name = cpu_get_name(processor_name); |
| 198 | printf("CPU: %s\n", name); |
| 199 | |
Simon Glass | 8e0df06 | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 200 | post_code(POST_CPU_INFO); |
| 201 | |
Simon Glass | 8ef0757 | 2014-11-12 22:42:07 -0700 | [diff] [blame] | 202 | return 0; |
| 203 | } |
Simon Glass | 7b95252 | 2015-10-18 19:51:27 -0600 | [diff] [blame] | 204 | |
| 205 | void board_debug_uart_init(void) |
| 206 | { |
| 207 | /* This enables the debug UART */ |
Simon Glass | a827ba9 | 2019-08-31 21:23:18 -0600 | [diff] [blame] | 208 | pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16); |
Simon Glass | 7b95252 | 2015-10-18 19:51:27 -0600 | [diff] [blame] | 209 | } |