blob: 8e0755423a9673137e60c0c9a4cb270e4c89dbff [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01002/*-
3 * Copyright (c) 2007-2008, Juniper Networks, Inc.
Remy Böhmerc0d722f2008-12-13 22:51:58 +01004 * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01005 * All rights reserved.
Michael Trimarchiaaf098c2008-11-28 13:20:46 +01006 */
7
8#ifndef USB_EHCI_H
9#define USB_EHCI_H
10
Chris Packham4eaf7f52018-10-04 20:03:53 +130011#include <stdbool.h>
Marek Vasutb9596552013-07-10 03:16:31 +020012#include <usb.h>
Marek Vasutb43cdf92018-08-08 14:29:55 +020013#include <generic-phy.h>
Marek Vasutb9596552013-07-10 03:16:31 +020014
Bin Meng99c22552017-07-19 21:50:05 +080015/* Section 2.2.3 - N_PORTS */
16#define MAX_HC_PORTS 15
Remy Böhmerc0d722f2008-12-13 22:51:58 +010017
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010018/*
19 * Register Space.
20 */
21struct ehci_hccr {
michaeldb632992008-12-10 17:55:19 +010022 uint32_t cr_capbase;
23#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
24#define HC_VERSION(p) (((p) >> 16) & 0xffff)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010025 uint32_t cr_hcsparams;
Remy Böhmerc0d722f2008-12-13 22:51:58 +010026#define HCS_PPC(p) ((p) & (1 << 4))
27#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
michael51ab1422008-12-11 13:43:55 +010028#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010029 uint32_t cr_hccparams;
30 uint8_t cr_hcsp_portrt[8];
Jason Kridner69716c12011-04-20 08:54:16 -050031} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010032
33struct ehci_hcor {
34 uint32_t or_usbcmd;
michael51ab1422008-12-11 13:43:55 +010035#define CMD_PARK (1 << 11) /* enable "park" */
36#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
michael51ab1422008-12-11 13:43:55 +010037#define CMD_LRESET (1 << 7) /* partial reset */
Masahiro Yamadac02bf452014-11-05 23:11:10 +090038#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
39#define CMD_ASE (1 << 5) /* async schedule enable */
michael51ab1422008-12-11 13:43:55 +010040#define CMD_PSE (1 << 4) /* periodic schedule enable */
41#define CMD_RESET (1 << 1) /* reset HC not bus */
42#define CMD_RUN (1 << 0) /* start/stop HC */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010043 uint32_t or_usbsts;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020044#define STS_ASS (1 << 15)
Patrick Georgi8f62ca62013-03-06 14:08:31 +000045#define STS_PSS (1 << 14)
michael51ab1422008-12-11 13:43:55 +010046#define STS_HALT (1 << 12)
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010047 uint32_t or_usbintr;
Damien Dusha29c6fbe2010-10-14 15:27:06 +020048#define INTR_UE (1 << 0) /* USB interrupt enable */
49#define INTR_UEE (1 << 1) /* USB error interrupt enable */
50#define INTR_PCE (1 << 2) /* Port change detect enable */
51#define INTR_SEE (1 << 4) /* system error enable */
52#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010053 uint32_t or_frindex;
54 uint32_t or_ctrldssegment;
55 uint32_t or_periodiclistbase;
56 uint32_t or_asynclistaddr;
Simon Glass9ab4ce22012-02-27 10:52:47 +000057 uint32_t _reserved_0_;
58 uint32_t or_burstsize;
59 uint32_t or_txfilltuning;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020060#define TXFIFO_THRESH_MASK (0x3f << 16)
Simon Glass9ab4ce22012-02-27 10:52:47 +000061#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
62 uint32_t _reserved_1_[6];
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010063 uint32_t or_configflag;
michael51ab1422008-12-11 13:43:55 +010064#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
Bin Meng99c22552017-07-19 21:50:05 +080065 uint32_t or_portsc[MAX_HC_PORTS];
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +020066#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
67#define PORTSC_PSPD_FS 0x0
68#define PORTSC_PSPD_LS 0x1
69#define PORTSC_PSPD_HS 0x2
Chris Packham4eaf7f52018-10-04 20:03:53 +130070#define PORTSC_FSL_PFSC BIT(24) /* PFSC bit to disable HS chirping */
71
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010072 uint32_t or_systune;
Jason Kridner69716c12011-04-20 08:54:16 -050073} __attribute__ ((packed, aligned(4)));
Michael Trimarchiaaf098c2008-11-28 13:20:46 +010074
michael51ab1422008-12-11 13:43:55 +010075#define USBMODE 0x68 /* USB Device mode */
76#define USBMODE_SDIS (1 << 3) /* Stream disable */
77#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
78#define USBMODE_CM_HC (3 << 0) /* host controller mode */
79#define USBMODE_CM_IDLE (0 << 0) /* idle state */
80
michaeldb632992008-12-10 17:55:19 +010081/* Interface descriptor */
82struct usb_linux_interface_descriptor {
83 unsigned char bLength;
84 unsigned char bDescriptorType;
85 unsigned char bInterfaceNumber;
86 unsigned char bAlternateSetting;
87 unsigned char bNumEndpoints;
88 unsigned char bInterfaceClass;
89 unsigned char bInterfaceSubClass;
90 unsigned char bInterfaceProtocol;
91 unsigned char iInterface;
92} __attribute__ ((packed));
93
94/* Configuration descriptor information.. */
95struct usb_linux_config_descriptor {
96 unsigned char bLength;
97 unsigned char bDescriptorType;
98 unsigned short wTotalLength;
99 unsigned char bNumInterfaces;
100 unsigned char bConfigurationValue;
101 unsigned char iConfiguration;
102 unsigned char bmAttributes;
103 unsigned char MaxPower;
104} __attribute__ ((packed));
105
106#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
Alexey Brodkin9829ce22017-11-17 16:26:30 +0300107#define ehci_readl(x) be32_to_cpu(__raw_readl(x))
108#define ehci_writel(a, b) __raw_writel(cpu_to_be32(b), a)
michaeldb632992008-12-10 17:55:19 +0100109#else
Alexey Brodkin9829ce22017-11-17 16:26:30 +0300110#define ehci_readl(x) readl(x)
111#define ehci_writel(a, b) writel(b, a)
michaeldb632992008-12-10 17:55:19 +0100112#endif
113
114#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
115#define hc32_to_cpu(x) be32_to_cpu((x))
116#define cpu_to_hc32(x) cpu_to_be32((x))
117#else
118#define hc32_to_cpu(x) le32_to_cpu((x))
119#define cpu_to_hc32(x) cpu_to_le32((x))
120#endif
121
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100122#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
123#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
124#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
125#define EHCI_PS_PO (1 << 13) /* RW port owner */
126#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
127#define EHCI_PS_LS (3 << 10) /* RO line status */
128#define EHCI_PS_PR (1 << 8) /* RW port reset */
129#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
130#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
131#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
132#define EHCI_PS_OCA (1 << 4) /* RO over current active */
133#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
134#define EHCI_PS_PE (1 << 2) /* RW port enable */
135#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
136#define EHCI_PS_CS (1 << 0) /* RO connect status */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100137#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
138
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100139#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100140
141/*
142 * Schedule Interface Space.
143 *
144 * IMPORTANT: Software must ensure that no interface data structure
145 * reachable by the EHCI host controller spans a 4K page boundary!
146 *
147 * Periodic transfers (i.e. isochronous and interrupt transfers) are
148 * not supported.
149 */
150
151/* Queue Element Transfer Descriptor (qTD). */
152struct qTD {
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200153 /* this part defined by EHCI spec */
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200154 uint32_t qt_next; /* see EHCI 3.5.1 */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100155#define QT_NEXT_TERMINATE 1
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200156 uint32_t qt_altnext; /* see EHCI 3.5.2 */
157 uint32_t qt_token; /* see EHCI 3.5.3 */
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200158#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
159#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
160#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
161#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
162#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
163#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
164#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
165#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
166#define QT_TOKEN_PID_OUT 0x0
167#define QT_TOKEN_PID_IN 0x1
168#define QT_TOKEN_PID_SETUP 0x2
169#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
170#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
171#define QT_TOKEN_STATUS_ACTIVE 0x80
172#define QT_TOKEN_STATUS_HALTED 0x40
173#define QT_TOKEN_STATUS_DATBUFERR 0x20
174#define QT_TOKEN_STATUS_BABBLEDET 0x10
175#define QT_TOKEN_STATUS_XACTERR 0x08
176#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
177#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
178#define QT_TOKEN_STATUS_PERR 0x01
Benoît Thébaudeaucdeb9162012-07-19 22:16:38 +0200179#define QT_BUFFER_CNT 5
180 uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
181 uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
Wolfgang Denk3ed16072010-10-19 16:13:15 +0200182 /* pad struct for 32 byte alignment */
183 uint32_t unused[3];
Wolfgang Denk8b675fe2010-10-20 21:08:17 +0200184};
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100185
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200186#define EHCI_PAGE_SIZE 4096
187
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100188/* Queue Head (QH). */
189struct QH {
190 uint32_t qh_link;
191#define QH_LINK_TERMINATE 1
192#define QH_LINK_TYPE_ITD 0
193#define QH_LINK_TYPE_QH 2
194#define QH_LINK_TYPE_SITD 4
195#define QH_LINK_TYPE_FSTN 6
196 uint32_t qh_endpt1;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200197#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
198#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
199#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
200#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
201#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
202#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
203#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
204#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
205#define QH_ENDPT1_EPS_FS 0x0
206#define QH_ENDPT1_EPS_LS 0x1
207#define QH_ENDPT1_EPS_HS 0x2
208#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
209#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
210#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100211 uint32_t qh_endpt2;
Benoît Thébaudeau14eb79b2012-08-10 18:22:11 +0200212#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
213#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
214#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
215#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
216#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100217 uint32_t qh_curtd;
218 struct qTD qh_overlay;
Stefan Roesedaa2daf2009-01-21 17:12:19 +0100219 /*
220 * Add dummy fill value to make the size of this struct
221 * aligned to 32 bytes
222 */
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000223 union {
Vincent Palatin61755c72013-03-06 14:08:32 +0000224 uint32_t fill[4];
Patrick Georgi8f62ca62013-03-06 14:08:31 +0000225 void *buffer;
226 };
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100227};
228
Simon Glass7372b5b2015-03-25 12:22:26 -0600229/* Tweak flags for EHCI, used to control operation */
230enum {
231 /* don't use or_configflag in init */
232 EHCI_TWEAK_NO_INIT_CF = 1 << 0,
233};
234
Simon Glassdeb85082015-03-25 12:22:27 -0600235struct ehci_ctrl;
236
237struct ehci_ops {
238 void (*set_usb_mode)(struct ehci_ctrl *ctrl);
239 int (*get_port_speed)(struct ehci_ctrl *ctrl, uint32_t reg);
240 void (*powerup_fixup)(struct ehci_ctrl *ctrl, uint32_t *status_reg,
241 uint32_t *reg);
242 uint32_t *(*get_portsc_register)(struct ehci_ctrl *ctrl, int port);
Mateusz Kulikowski3f9f8a52016-03-31 23:12:17 +0200243 int (*init_after_reset)(struct ehci_ctrl *ctrl);
Simon Glassdeb85082015-03-25 12:22:27 -0600244};
245
Marek Vasutb9596552013-07-10 03:16:31 +0200246struct ehci_ctrl {
Stephen Warren49b4c5c2015-08-20 17:38:05 -0600247 enum usb_init_type init;
Marek Vasutb9596552013-07-10 03:16:31 +0200248 struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
249 struct ehci_hcor *hcor;
250 int rootdev;
251 uint16_t portreset;
252 struct QH qh_list __aligned(USB_DMA_MINALIGN);
253 struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
254 uint32_t *periodic_list;
Hans de Goede36b73102014-09-20 16:51:25 +0200255 int periodic_schedules;
Marek Vasutb9596552013-07-10 03:16:31 +0200256 int ntds;
Chris Packham4eaf7f52018-10-04 20:03:53 +1300257 bool has_fsl_erratum_a005275; /* Freescale HS silicon quirk */
Marek Vasut31232de2020-04-06 14:29:44 +0200258 bool async_locked;
Simon Glassdeb85082015-03-25 12:22:27 -0600259 struct ehci_ops ops;
Simon Glassc4a31412015-03-25 12:22:19 -0600260 void *priv; /* client's private data */
Marek Vasutb9596552013-07-10 03:16:31 +0200261};
262
Simon Glassc4a31412015-03-25 12:22:19 -0600263/**
Simon Glassdeb85082015-03-25 12:22:27 -0600264 * ehci_set_controller_info() - Set up private data for the controller
Simon Glassc4a31412015-03-25 12:22:19 -0600265 *
266 * This function can be called in ehci_hcd_init() to tell the EHCI layer
267 * about the controller's private data pointer. Then in the above functions
Simon Glassdeb85082015-03-25 12:22:27 -0600268 * this can be accessed given the struct ehci_ctrl pointer. Also special
269 * EHCI operation methods can be provided if required
Simon Glassc4a31412015-03-25 12:22:19 -0600270 *
271 * @index: Controller number to set
272 * @priv: Controller pointer
Simon Glassdeb85082015-03-25 12:22:27 -0600273 * @ops: Controller operations, or NULL to use default
Simon Glassc4a31412015-03-25 12:22:19 -0600274 */
Simon Glassdeb85082015-03-25 12:22:27 -0600275void ehci_set_controller_priv(int index, void *priv,
276 const struct ehci_ops *ops);
Simon Glassc4a31412015-03-25 12:22:19 -0600277
278/**
279 * ehci_get_controller_priv() - Get controller private data
280 *
281 * @index Controller number to get
282 * @return controller pointer for this index
283 */
284void *ehci_get_controller_priv(int index);
285
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100286/* Low level init functions */
Troy Kisky127efc42013-10-10 15:27:57 -0700287int ehci_hcd_init(int index, enum usb_init_type init,
288 struct ehci_hccr **hccr, struct ehci_hcor **hcor);
Lucas Stach676ae062012-09-26 00:14:35 +0200289int ehci_hcd_stop(int index);
Remy Böhmerc0d722f2008-12-13 22:51:58 +0100290
Simon Glass46b01792015-03-25 12:22:29 -0600291int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
292 struct ehci_hcor *hcor, const struct ehci_ops *ops,
293 uint tweaks, enum usb_init_type init);
294int ehci_deregister(struct udevice *dev);
295extern struct dm_usb_ops ehci_usb_ops;
296
Marek Vasutb43cdf92018-08-08 14:29:55 +0200297/* EHCI PHY functions */
298int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index);
299int ehci_shutdown_phy(struct udevice *dev, struct phy *phy);
300
Simon Glasscd93d622020-05-10 11:40:13 -0600301#include <linux/bitops.h>
Michael Trimarchiaaf098c2008-11-28 13:20:46 +0100302#endif /* USB_EHCI_H */