Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 1 | if ARCH_SOCFPGA |
| 2 | |
Simon Glass | 77d2f7f | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 3 | config SPL_LIBCOMMON_SUPPORT |
| 4 | default y |
| 5 | |
Simon Glass | 1646eba | 2016-09-12 23:18:42 -0600 | [diff] [blame] | 6 | config SPL_LIBDISK_SUPPORT |
| 7 | default y |
| 8 | |
Simon Glass | cc4288e | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y |
| 11 | |
Simon Glass | 1fdf7c6 | 2016-09-12 23:18:44 -0600 | [diff] [blame] | 12 | config SPL_MMC_SUPPORT |
| 13 | default y if DM_MMC |
| 14 | |
Simon Glass | d6b9bd8 | 2016-09-12 23:18:48 -0600 | [diff] [blame^] | 15 | config SPL_NAND_SUPPORT |
| 16 | default y if SPL_NAND_DENALI |
| 17 | |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 18 | config TARGET_SOCFPGA_ARRIA5 |
| 19 | bool |
Dinh Nguyen | ed77aeb | 2015-12-02 13:31:25 -0600 | [diff] [blame] | 20 | select TARGET_SOCFPGA_GEN5 |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 21 | |
| 22 | config TARGET_SOCFPGA_CYCLONE5 |
| 23 | bool |
Dinh Nguyen | ed77aeb | 2015-12-02 13:31:25 -0600 | [diff] [blame] | 24 | select TARGET_SOCFPGA_GEN5 |
| 25 | |
| 26 | config TARGET_SOCFPGA_GEN5 |
| 27 | bool |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 28 | |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 29 | choice |
| 30 | prompt "Altera SOCFPGA board select" |
Joe Hershberger | a26cd04 | 2015-05-12 14:46:23 -0500 | [diff] [blame] | 31 | optional |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 32 | |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 33 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 34 | bool "Altera SOCFPGA SoCDK (Arria V)" |
| 35 | select TARGET_SOCFPGA_ARRIA5 |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 36 | |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 37 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 38 | bool "Altera SOCFPGA SoCDK (Cyclone V)" |
| 39 | select TARGET_SOCFPGA_CYCLONE5 |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 40 | |
Marek Vasut | d88995a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 41 | config TARGET_SOCFPGA_DENX_MCVEVK |
| 42 | bool "DENX MCVEVK (Cyclone V)" |
| 43 | select TARGET_SOCFPGA_CYCLONE5 |
| 44 | |
Marek Vasut | 856b30d | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 45 | config TARGET_SOCFPGA_EBV_SOCRATES |
| 46 | bool "EBV SoCrates (Cyclone V)" |
| 47 | select TARGET_SOCFPGA_CYCLONE5 |
| 48 | |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 49 | config TARGET_SOCFPGA_IS1 |
| 50 | bool "IS1 (Cyclone V)" |
| 51 | select TARGET_SOCFPGA_CYCLONE5 |
| 52 | |
Marek Vasut | 569a191 | 2015-12-01 18:09:52 +0100 | [diff] [blame] | 53 | config TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 54 | bool "samtec VIN|ING FPGA (Cyclone V)" |
| 55 | select TARGET_SOCFPGA_CYCLONE5 |
| 56 | |
Marek Vasut | cf0a8da | 2016-06-08 02:57:05 +0200 | [diff] [blame] | 57 | config TARGET_SOCFPGA_SR1500 |
| 58 | bool "SR1500 (Cyclone V)" |
| 59 | select TARGET_SOCFPGA_CYCLONE5 |
| 60 | |
Dinh Nguyen | 55c7a76 | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 61 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 62 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" |
| 63 | select TARGET_SOCFPGA_CYCLONE5 |
| 64 | |
Marek Vasut | 952caa2 | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 65 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 66 | bool "Terasic SoCkit (Cyclone V)" |
| 67 | select TARGET_SOCFPGA_CYCLONE5 |
| 68 | |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 69 | endchoice |
| 70 | |
| 71 | config SYS_BOARD |
Marek Vasut | f089240 | 2015-08-10 21:24:53 +0200 | [diff] [blame] | 72 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 73 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Dinh Nguyen | 55c7a76 | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 74 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 75 | default "is1" if TARGET_SOCFPGA_IS1 |
Marek Vasut | d88995a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 76 | default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
Marek Vasut | 952caa2 | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 77 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Marek Vasut | 856b30d | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 78 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
Stefan Roese | ae9996c | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 79 | default "sr1500" if TARGET_SOCFPGA_SR1500 |
Marek Vasut | 569a191 | 2015-12-01 18:09:52 +0100 | [diff] [blame] | 80 | default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 81 | |
| 82 | config SYS_VENDOR |
Marek Vasut | cd9b731 | 2015-08-02 21:57:57 +0200 | [diff] [blame] | 83 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 84 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Marek Vasut | d88995a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 85 | default "denx" if TARGET_SOCFPGA_DENX_MCVEVK |
Marek Vasut | 856b30d | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 86 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
Marek Vasut | 569a191 | 2015-12-01 18:09:52 +0100 | [diff] [blame] | 87 | default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
Dinh Nguyen | 55c7a76 | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 88 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Marek Vasut | 952caa2 | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 89 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 90 | |
| 91 | config SYS_SOC |
| 92 | default "socfpga" |
| 93 | |
| 94 | config SYS_CONFIG_NAME |
Dinh Nguyen | 3cbc7b8 | 2015-09-22 17:01:32 -0500 | [diff] [blame] | 95 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 96 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK |
Dinh Nguyen | 55c7a76 | 2015-09-01 17:41:52 -0500 | [diff] [blame] | 97 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
Pavel Machek | 35546f6 | 2016-06-07 12:37:23 +0200 | [diff] [blame] | 98 | default "socfpga_is1" if TARGET_SOCFPGA_IS1 |
Marek Vasut | d88995a | 2015-08-03 01:37:28 +0200 | [diff] [blame] | 99 | default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
Marek Vasut | 952caa2 | 2015-06-21 17:28:53 +0200 | [diff] [blame] | 100 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
Marek Vasut | 856b30d | 2015-11-23 17:06:27 +0100 | [diff] [blame] | 101 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
Stefan Roese | ae9996c | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 102 | default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |
Marek Vasut | 569a191 | 2015-12-01 18:09:52 +0100 | [diff] [blame] | 103 | default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
Masahiro Yamada | 7865f4b | 2015-04-21 20:38:20 +0900 | [diff] [blame] | 104 | |
| 105 | endif |