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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d6eaaae3d3066efadab3899e3f66ee8db85368b2 / . / board / ti / am57xx / mux_data.h
blob: 51df977817e03b17af7daa17b4346724ba31402a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600[diff] [blame]2/*
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 *
5 * Author: Felipe Balbi <balbi@ti.com>
6 *
7 * Based on board/ti/dra7xx/evm.c
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600[diff] [blame]8 */
9#ifndef _MUX_DATA_BEAGLE_X15_H_
10#define _MUX_DATA_BEAGLE_X15_H_
11
12#include <asm/arch/mux_dra7xx.h>
13
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]14const struct pad_conf_entry core_padconf_array_essential_x15[] = {
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]15 {GPMC_AD0, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */
16 {GPMC_AD1, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */
17 {GPMC_AD2, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */
18 {GPMC_AD3, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */
19 {GPMC_AD4, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */
20 {GPMC_AD5, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */
21 {GPMC_AD6, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */
22 {GPMC_AD7, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */
23 {GPMC_AD8, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */
24 {GPMC_AD9, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */
25 {GPMC_AD10, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */
26 {GPMC_AD11, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */
27 {GPMC_AD12, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */
28 {GPMC_AD13, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */
29 {GPMC_AD14, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */
30 {GPMC_AD15, (M2 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]31 {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */
32 {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */
33 {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */
34 {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */
35 {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */
36 {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */
37 {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */
38 {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */
39 {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */
40 {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */
41 {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */
42 {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */
43 {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */
44 {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */
45 {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */
46 {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */
47 {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */
48 {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */
49 {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */
50 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
51 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
52 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
53 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
54 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
55 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
56 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
57 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
58 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
59 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
60 {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
61 {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]62 {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_cs3.vin3a_clk0 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]63 {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */
64 {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
65 {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
66 {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
67 {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
68 {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]69 {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
70 {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]71 {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
72 {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
73 {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
74 {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */
75 {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */
76 {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */
77 {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */
78 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
79 {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */
80 {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */
81 {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */
82 {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */
83 {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */
84 {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]85 {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */
86 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
87 {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
88 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]89 {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.pr1_uart0_cts_n */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]90 {VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]91 {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d0.pr1_uart0_rxd */
92 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
93 {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d2.uart10_rxd */
94 {VIN2A_D3, (M8 | PIN_OUTPUT)}, /* vin2a_d3.uart10_txd */
95 {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d4.uart10_ctsn */
96 {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.uart10_rtsn */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]97 {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
98 {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
99 {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
100 {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]101 {VIN2A_D10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]102 {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]103 {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
104 {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
105 {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
106 {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
107 {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
108 {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
109 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
110 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
111 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
112 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
113 {VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
114 {VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]115 {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]116 {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
117 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]118 {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]119 {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
120 {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]121 {RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
122 {RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
123 {RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
124 {RGMII0_TXD2, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
125 {RGMII0_TXD1, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
126 {RGMII0_TXD0, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
127 {RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
128 {RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
129 {RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
130 {RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
131 {RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
132 {RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]133 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
134 {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]135 {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
136 {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
137 {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]138 {XREF_CLK0, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]139 {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */
140 {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]141 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]142 {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]143 {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_fsx.i2c3_scl */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]144 {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
145 {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]146 {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
147 {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]148 {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
149 {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
150 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
151 {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
152 {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
153 {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]154 {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */
155 {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */
156 {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr10.gpio5_12 */
157 {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
158 {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
159 {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
160 {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
161 {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]162 {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]163 {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
164 {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
165 {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]166 {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]167 {MCASP4_FSX, (M3 | PIN_OUTPUT)}, /* mcasp4_fsx.uart8_txd */
168 {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]169 {MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
170 {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]171 {MCASP5_FSX, (M3 | PIN_OUTPUT)}, /* mcasp5_fsx.uart9_txd */
172 {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]173 {MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
Sekhar Nori411278b2017-02-08 18:43:59 +0530[diff] [blame]174 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]175 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
176 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
177 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
178 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
179 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]180 {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]181 {GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
182 {GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
Sekhar Nori411278b2017-02-08 18:43:59 +0530[diff] [blame]183 {MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]184 {MMC3_CMD, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_cmd.mmc3_cmd */
185 {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat0.mmc3_dat0 */
186 {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
187 {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */
188 {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]189 {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat4.mmc3_dat4 */
190 {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat5.mmc3_dat5 */
191 {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat6.mmc3_dat6 */
192 {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat7.mmc3_dat7 */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]193 {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
194 {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
195 {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]196 {SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */
197 {SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]198 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen32651e42018-06-08 12:51:19 +0300[diff] [blame]199 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]200 {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]201 {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */
202 {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */
203 {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
204 {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
205 {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
206 {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
207 {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]208 {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
209 {UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */
210 {UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */
211 {UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */
212 {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]213 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]214 {I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
215 {I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
216 {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
217 {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
218 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
219 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
220 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
221 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
222 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
223 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
224 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]225 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]226 {TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */
227 {TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */
228 {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
229 {RTCK, (M0 | PIN_OUTPUT)}, /* rtck.rtck */
230 {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
231 {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
232 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
233 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
234};
235
236const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]237 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
238 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
239 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
240 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
241 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
242 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
243 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
244 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
245 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
246 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
247 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
248 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
249 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
250 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
251 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
252 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
253 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
254 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
255 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
256 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
257 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
258 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
259 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
260 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
261 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
262 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
263 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
264 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
265 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]266};
267
268const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
269 {VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]270 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
271 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
272 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
273 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
274 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
275 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
276 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
277 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
278 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
279 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
280 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
281 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
282 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
283 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
284 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
285 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
286 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
287 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
288 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
289 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
290 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
291 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
292 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
293 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
294 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
295 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
296 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
297 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600[diff] [blame]298};
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]299
Lokesh Vutla443b0df2017-12-29 11:47:55 +0530[diff] [blame]300const struct pad_conf_entry core_padconf_array_essential_am574x_idk[] = {
301 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
302 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
303 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
304 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
305 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
306 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
307 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
308 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
309 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
310 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
311 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
312 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
313 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
314 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
315 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
316 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
317 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
318 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
319 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
320 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
321 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
322 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
323 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
324 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
325 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
326 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
327 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
328 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
329 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
330 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
331 {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
332 {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
333 {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
334 {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
335 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
336 {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
337 {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
338 {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
339 {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
340 {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
341 {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
342 {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
343 {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
344 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
345 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
346 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
347 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
348 {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
349 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
350 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
351 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
352 {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
353 {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
354 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
355 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
356 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
357 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
358 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
359 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
360 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
361 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
362 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
363 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
364 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
365 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
366 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
367 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
368 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
369 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
370 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
371 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
372 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
373 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
374 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
375 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
376 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
377 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
378 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
379 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
380 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
381 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
382 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
383 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
384 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
385 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
386 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
387 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
388 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
389 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
390 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
391 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
392 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
393 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
394 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
395 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
396 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
397 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
398 {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
399 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
400 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
401 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
402 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
403 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
404 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
405 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
406 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
407 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
408 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
409 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
410 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
411 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
412 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
413 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
414 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
415 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
416 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
417 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
418 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
419 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
420 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
421 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
422 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
423 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
424 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
425 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
426 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
427 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
428 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
429 {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
430 {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
431 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
432 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
433 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
434 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
435 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
436 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
437 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
438 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
439 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
440 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
441 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
442 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
443 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
444 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
445 {MCASP2_AXR4, (M14 | PIN_INPUT)}, /* mcasp2_axr4.gpio1_4 */
446 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
447 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
448 {MCASP2_AXR7, (M14 | PIN_INPUT)}, /* mcasp2_axr7.gpio1_5 */
449 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
450 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
451 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
452 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
453 {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
454 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
455 {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
456 {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
457 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
458 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
459 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
460 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
461 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
462 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
463 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
464 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
465 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
466 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
467 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
468 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
469 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
470 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
471 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
472 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
473 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
474 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
475 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
476 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
477 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
478 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
479 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
480 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
481 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
482 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
483 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen32651e42018-06-08 12:51:19 +0300[diff] [blame]484 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutla443b0df2017-12-29 11:47:55 +0530[diff] [blame]485 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
486 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
487 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
488 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
489 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
490 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
491 {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
492 {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
493 {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
494 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
495 {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
496 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
497 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
498 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
499 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
500 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
501 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
502 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
503 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
504 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
505 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
506 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
507 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
508 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
509 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
510 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
511 {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
512 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
513 {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
514 {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
515 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
516 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
517 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
518};
519
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]520const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]521 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin4b_d0 */
522 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin4b_d1 */
523 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin4b_d2 */
524 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin4b_d3 */
525 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin4b_d4 */
526 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin4b_d5 */
527 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin4b_d6 */
528 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin4b_d7 */
529 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin4b_hsync1 */
530 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin4b_vsync1 */
531 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin4b_clk1 */
532 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin4b_de1 */
533 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin4b_fld1 */
534 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
535 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
536 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
537 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
538 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
539 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]540 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
541 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
542 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
543 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]544 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]545 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
546 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
547 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
548 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
549 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]550 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
551 {VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
552 {VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
553 {VIN1A_D7, (M14 | PIN_OUTPUT)}, /* vin1a_d7.gpio3_11 */
554 {VIN1A_D8, (M14 | PIN_OUTPUT)}, /* vin1a_d8.gpio3_12 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]555 {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]556 {VIN1A_D12, (M14 | PIN_INPUT)}, /* vin1a_d12.gpio3_16 */
557 {VIN1A_D13, (M14 | PIN_OUTPUT)}, /* vin1a_d13.gpio3_17 */
558 {VIN1A_D14, (M14 | PIN_OUTPUT)}, /* vin1a_d14.gpio3_18 */
559 {VIN1A_D15, (M14 | PIN_OUTPUT)}, /* vin1a_d15.gpio3_19 */
560 {VIN1A_D17, (M14 | PIN_OUTPUT)}, /* vin1a_d17.gpio3_21 */
561 {VIN1A_D18, (M14 | PIN_OUTPUT_PULLDOWN)}, /* vin1a_d18.gpio3_22 */
562 {VIN1A_D19, (M14 | PIN_OUTPUT_PULLUP)}, /* vin1a_d19.gpio3_23 */
563 {VIN1A_D22, (M14 | PIN_INPUT)}, /* vin1a_d22.gpio3_26 */
564 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
565 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
566 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]567 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]568 {VIN2A_VSYNC0, (M14 | PIN_INPUT)}, /* vin2a_vsync0.gpio4_0 */
569 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
570 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
571 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
572 {VIN2A_D3, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_edc_latch0_in */
573 {VIN2A_D4, (M11 | PIN_OUTPUT)}, /* vin2a_d4.pr1_edc_sync0_out */
574 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
575 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
576 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
577 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
578 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
579 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
580 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
581 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
582 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]583 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]584 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]585 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
586 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
587 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
588 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]589 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
590 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]591 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]592 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
593 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
594 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
595 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
596 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
597 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
598 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
599 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
600 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
601 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
602 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
603 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
604 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
605 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
606 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
607 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
608 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
609 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
610 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
611 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
612 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
613 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
614 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
615 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
616 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
617 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
618 {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
619 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]620 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
621 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
622 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
623 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
624 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
625 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]626 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
627 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
628 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
629 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
630 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
631 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]632 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
633 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]634 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
635 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
636 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]637 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
638 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]639 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
640 {XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
641 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]642 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]643 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
644 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]645 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
646 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]647 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
648 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
649 {MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
650 {MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
651 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
652 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]653 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
654 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
655 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
656 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
657 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
658 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
659 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
660 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]661 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]662 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
663 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
664 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]665 {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
666 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
667 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
668 {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]669 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]670 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
671 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
672 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]673 {MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
674 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]675 {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]676 {MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
677 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
678 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]679 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
680 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
681 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
682 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
683 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
684 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
685 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]686 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]687 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
688 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
689 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
690 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
691 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]692 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
693 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
694 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
695 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
696 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
697 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]698 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
699 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
700 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
701 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
702 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]703 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
Tomi Valkeinen32651e42018-06-08 12:51:19 +0300[diff] [blame]704 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]705 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
706 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
707 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
708 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]709 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
710 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]711 {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
712 {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]713 {UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
714 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
715 {UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
716 {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
717 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
718 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
719 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
720 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
721 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
722 {WAKEUP1, (M0 | PIN_INPUT)}, /* Wakeup1.Wakeup1 */
723 {WAKEUP2, (M0 | PIN_INPUT)}, /* Wakeup2.Wakeup2 */
724 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
725 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
726 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]727 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]728 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]729 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]730 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
731 {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]732 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]733 {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
734 {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]735 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]736 {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]737 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]738};
739
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]740const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]741 {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin1b_d0 */
742 {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin1b_d1 */
743 {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin1b_d2 */
744 {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin1b_d3 */
745 {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin1b_d4 */
746 {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin1b_d5 */
747 {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin1b_d6 */
748 {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin1b_d7 */
749 {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin1b_hsync1 */
750 {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin1b_vsync1 */
751 {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin1b_clk1 */
752 {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin1b_de1 */
753 {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin1b_fld1 */
754 {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
755 {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
756 {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
757 {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
758 {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
759 {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]760 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
761 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
762 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
763 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
764 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
765 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
766 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
767 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
768 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
769 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]770 {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */
771 {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
772 {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */
773 {GPMC_CLK, (M14 | PIN_INPUT)}, /* gpmc_clk.gpio2_22 */
774 {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)}, /* gpmc_advn_ale.gpio2_23 */
775 {GPMC_OEN_REN, (M14 | PIN_OUTPUT)}, /* gpmc_oen_ren.gpio2_24 */
776 {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */
777 {GPMC_BEN0, (M14 | PIN_OUTPUT)}, /* gpmc_ben0.gpio2_26 */
778 {GPMC_BEN1, (M14 | PIN_OUTPUT)}, /* gpmc_ben1.gpio2_27 */
779 {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]780 {VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
781 {VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
782 {VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
783 {VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]784 {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)}, /* vin2a_vsync0.gpio4_0 */
785 {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
786 {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
787 {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
788 {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
789 {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
790 {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
791 {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
792 {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
793 {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
794 {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
795 {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]796 {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]797 {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]798 {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
799 {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
800 {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
801 {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]802 {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
803 {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
804 {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
805 {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* uart3_rxd.gpio5_18 */
806 {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */
807 {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
808 {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
809 {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
810 {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
811 {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
812 {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]813 {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]814 {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
815 {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
816 {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
817 {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
818 {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
819 {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
820 {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
821 {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
822 {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
823 {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
824 {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
825 {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
826 {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
827 {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */
828 {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
829 {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
830 {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
831 {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
832 {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
833 {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
834 {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
835 {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]836 {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]837 {MCASP1_AXR5, (M14 | PIN_INPUT)}, /* mcasp1_axr5.gpio5_7 */
838 {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
839 {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
840 {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
841 {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
842 {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
843 {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
844 {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
845 {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
846 {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
847 {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
848 {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
849 {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
850 {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
851 {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
852 {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
853 {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
854 {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
855 {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
856 {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
857 {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
858 {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
859 {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
860 {MCASP4_ACLKX, (M2 | PIN_OUTPUT)}, /* mcasp4_aclkx.spi3_sclk */
861 {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
862 {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
863 {MCASP5_AXR0, (M4 | PIN_INPUT)}, /* mcasp5_axr0.uart3_rxd */
864 {MCASP5_AXR1, (M4 | PIN_OUTPUT)}, /* mcasp5_axr1.uart3_txd */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]865 {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
866 {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
867 {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
868 {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
869 {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
870 {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]871 {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
872 {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
873 {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
874 {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
875 {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
876 {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
877 {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
878 {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
879 {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]880 {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]881 {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
882 {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
883 {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
884 {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
885 {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
886 {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
887 {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
888 {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
889 {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
890 {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
891 {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
892 {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
893 {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
894 {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
895 {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]896 {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
897 {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]898 {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
899 {UART1_CTSN, (M14 | PIN_OUTPUT)}, /* uart1_ctsn.gpio7_24 */
900 {UART1_RTSN, (M14 | PIN_OUTPUT)}, /* uart1_rtsn.gpio7_25 */
901 {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
902 {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
903 {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
904 {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
905 {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
906 {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
907 {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
908 {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]909 {TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
910 {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]911 {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]912 {TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]913 {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
914 {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
915 {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
916 {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
917 {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
918 {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]919};
920
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]921const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
922 /* PR1 MII0 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]923 {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d8.pr1_mii_mt0_clk */
924 {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d9.pr1_mii0_txd3 */
925 {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */
926 {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */
927 {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */
928 {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */
929 {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d14.pr1_mii_mr0_clk */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]930 {VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]931 {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.pr1_mii0_rxd3 */
932 {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.pr1_mii0_rxd2 */
933 {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.pr1_mii0_rxd1 */
934 {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.pr1_mii0_rxd0 */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]935 {VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]936 {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.pr1_mii0_rxlink */
937 {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.pr1_mii0_col */
938 {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.pr1_mii0_crs */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]939
940 /* PR1 MII1 */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]941 {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */
942 {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d4.pr1_mii1_txd1 */
943 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.pr1_mii1_txd0 */
944 {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d6.pr1_mii_mt1_clk */
945 {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d7.pr1_mii1_txen */
946 {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d8.pr1_mii1_txd3 */
947 {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d9.pr1_mii1_txd2 */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]948 {VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]949 {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d0.pr1_mii1_rxlink */
950 {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */
951 {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d2.pr1_mii_mr1_clk */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]952 {VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]953 {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */
954 {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */
955 {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */
956 {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]957};
958
959const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]960 {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
961 {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
962 {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
963 {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
964 {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
965 {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
966 {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
967 {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
968 {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
969 {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
970 {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
971 {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
972 {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
973 {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
974 {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
975 {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
976 {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
977 {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
978 {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
979 {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
980 {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
981 {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
982 {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
983 {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
984 {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
985 {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
986 {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
987 {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
988
989 {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpi1 */
990 {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
991 {UART2_RXD, (M0 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
992 {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
993 {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
Roger Quadros37611052017-03-13 15:04:28 +0200[diff] [blame]994};
995
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]996const struct pad_conf_entry early_padconf[] = {
997 {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */
998 {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */
999 {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */
1000 {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */
1001};
1002
Caleb Robeyd6eaaae2020-01-02 08:17:25 -0600[diff] [blame^]1003#ifdef CONFIG_SUPPORT_EMMC_BOOT
1004const struct pad_conf_entry emmc_padconf[] = {
1005 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* K7: gpmc_a19.mmc2_dat4 */
1006 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* M7: gpmc_a20.mmc2_dat5 */
1007 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* J5: gpmc_a21.mmc2_dat6 */
1008 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* K6: gpmc_a22.mmc2_dat7 */
1009 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* J7: gpmc_a23.mmc2_clk */
1010 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* J4: gpmc_a24.mmc2_dat0 */
1011 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* J6: gpmc_a25.mmc2_dat1 */
1012 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* H4: gpmc_a26.mmc2_dat2 */
1013 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* H5: gpmc_a27.mmc2_dat3 */
1014 {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* H6: gpmc_cs1.mmc2_cmd */
1015 {MCASP1_AXR5, (M14 | PIN_OUTPUT_PULLUP)}, /* F13: eMMC_RSTn (missing on schematic): mcasp1_axr5.gpio5_7 */
1016};
1017#endif
1018
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1019#ifdef CONFIG_IODELAY_RECALIBRATION
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]1020const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1021 {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */
1022 {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */
1023 {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */
1024 {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */
1025 {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */
1026 {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */
1027 {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */
1028 {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */
1029 {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */
1030 {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */
1031 {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */
1032 {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */
1033 {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */
1034 {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */
1035 {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */
1036 {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */
1037 {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */
1038 {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */
1039 {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */
1040 {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */
1041 {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */
1042 {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */
1043 {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */
1044 {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */
1045 {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */
1046 {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
1047 {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
1048 {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]1049 {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
1050 {0x0678, 406, 0}, /* CFG_MMC3_CLK_IN */
1051 {0x0680, 659, 0}, /* CFG_MMC3_CLK_OUT */
1052 {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
1053 {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
1054 {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
1055 {0x0690, 130, 0}, /* CFG_MMC3_DAT0_IN */
1056 {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
1057 {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
1058 {0x069C, 169, 0}, /* CFG_MMC3_DAT1_IN */
1059 {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
1060 {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
1061 {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
1062 {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
1063 {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
1064 {0x06B4, 457, 0}, /* CFG_MMC3_DAT3_IN */
1065 {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
1066 {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
1067 {0x06C0, 702, 0}, /* CFG_MMC3_DAT4_IN */
1068 {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
1069 {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
1070 {0x06CC, 738, 0}, /* CFG_MMC3_DAT5_IN */
1071 {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
1072 {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
1073 {0x06D8, 856, 0}, /* CFG_MMC3_DAT6_IN */
1074 {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
1075 {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
1076 {0x06E4, 610, 0}, /* CFG_MMC3_DAT7_IN */
1077 {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
1078 {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1079 {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
1080 {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
1081 {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
1082 {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */
1083 {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */
1084 {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */
1085 {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */
Nishanth Menon5d43e162016-11-25 11:14:21 +0530[diff] [blame]1086 {0x074C, 201, 60}, /* CFG_RGMII0_TXCTL_OUT */
1087 {0x0758, 229, 120}, /* CFG_RGMII0_TXD0_OUT */
1088 {0x0764, 141, 0}, /* CFG_RGMII0_TXD1_OUT */
1089 {0x0770, 495, 120}, /* CFG_RGMII0_TXD2_OUT */
1090 {0x077C, 660, 120}, /* CFG_RGMII0_TXD3_OUT */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1091 {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */
1092 {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */
1093 {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
1094 {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
1095 {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]1096 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1097 {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
1098 {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
1099 {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
1100 {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */
1101 {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */
1102 {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */
1103};
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]1104
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]1105const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
1106 {0x0114, 2519, 702}, /* CFG_GPMC_A0_IN */
1107 {0x0120, 2435, 411}, /* CFG_GPMC_A10_IN */
1108 {0x012C, 2379, 755}, /* CFG_GPMC_A11_IN */
1109 {0x0198, 2384, 778}, /* CFG_GPMC_A1_IN */
1110 {0x0204, 2499, 1127}, /* CFG_GPMC_A2_IN */
1111 {0x0210, 2455, 1181}, /* CFG_GPMC_A3_IN */
1112 {0x021C, 2486, 1039}, /* CFG_GPMC_A4_IN */
1113 {0x0228, 2456, 938}, /* CFG_GPMC_A5_IN */
1114 {0x0234, 2463, 573}, /* CFG_GPMC_A6_IN */
1115 {0x0240, 2608, 783}, /* CFG_GPMC_A7_IN */
1116 {0x024C, 2430, 656}, /* CFG_GPMC_A8_IN */
1117 {0x0258, 2465, 850}, /* CFG_GPMC_A9_IN */
1118 {0x0264, 2316, 301}, /* CFG_GPMC_AD0_IN */
1119 {0x0270, 2324, 406}, /* CFG_GPMC_AD10_IN */
1120 {0x027C, 2278, 352}, /* CFG_GPMC_AD11_IN */
1121 {0x0288, 2297, 160}, /* CFG_GPMC_AD12_IN */
1122 {0x0294, 2278, 108}, /* CFG_GPMC_AD13_IN */
1123 {0x02A0, 2035, 0}, /* CFG_GPMC_AD14_IN */
1124 {0x02AC, 2279, 378}, /* CFG_GPMC_AD15_IN */
1125 {0x02B8, 2440, 70}, /* CFG_GPMC_AD1_IN */
1126 {0x02C4, 2404, 446}, /* CFG_GPMC_AD2_IN */
1127 {0x02D0, 2343, 212}, /* CFG_GPMC_AD3_IN */
1128 {0x02DC, 2355, 322}, /* CFG_GPMC_AD4_IN */
1129 {0x02E8, 2337, 192}, /* CFG_GPMC_AD5_IN */
1130 {0x02F4, 2270, 314}, /* CFG_GPMC_AD6_IN */
1131 {0x0300, 2339, 259}, /* CFG_GPMC_AD7_IN */
1132 {0x030C, 2308, 577}, /* CFG_GPMC_AD8_IN */
1133 {0x0318, 2334, 166}, /* CFG_GPMC_AD9_IN */
1134 {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
1135 {0x0678, 0, 386}, /* CFG_MMC3_CLK_IN */
1136 {0x0680, 605, 0}, /* CFG_MMC3_CLK_OUT */
1137 {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
1138 {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
1139 {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
1140 {0x0690, 171, 0}, /* CFG_MMC3_DAT0_IN */
1141 {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
1142 {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
1143 {0x069C, 221, 0}, /* CFG_MMC3_DAT1_IN */
1144 {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
1145 {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
1146 {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
1147 {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
1148 {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
1149 {0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */
1150 {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
1151 {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]1152 {0x06C0, 792, 0}, /* CFG_MMC3_DAT4_IN */
1153 {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
1154 {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
1155 {0x06CC, 782, 0}, /* CFG_MMC3_DAT5_IN */
1156 {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
1157 {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
1158 {0x06D8, 942, 0}, /* CFG_MMC3_DAT6_IN */
1159 {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
1160 {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
1161 {0x06E4, 636, 0}, /* CFG_MMC3_DAT7_IN */
1162 {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
1163 {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]1164 {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
1165 {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
1166 {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
1167 {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
1168 {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
1169 {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
1170 {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
1171 {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
1172 {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
1173 {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
1174 {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
1175 {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
1176 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1177 {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
1178 {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
1179 {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
1180 {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
1181 {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
1182 {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
1183 {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
1184 {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
1185 {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
1186 {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
1187 {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
Lokesh Vutlad9e14672017-06-05 14:48:17 +0530[diff] [blame]1188 {0x0B9C, 0, 706}, /* CFG_VOUT1_CLK_OUT */
1189 {0x0BA8, 2313, 0}, /* CFG_VOUT1_D0_OUT */
1190 {0x0BB4, 2199, 0}, /* CFG_VOUT1_D10_OUT */
1191 {0x0BC0, 2266, 0}, /* CFG_VOUT1_D11_OUT */
1192 {0x0BCC, 3159, 0}, /* CFG_VOUT1_D12_OUT */
1193 {0x0BD8, 2100, 0}, /* CFG_VOUT1_D13_OUT */
1194 {0x0BE4, 2229, 0}, /* CFG_VOUT1_D14_OUT */
1195 {0x0BF0, 2202, 0}, /* CFG_VOUT1_D15_OUT */
1196 {0x0BFC, 2084, 0}, /* CFG_VOUT1_D16_OUT */
1197 {0x0C08, 2195, 0}, /* CFG_VOUT1_D17_OUT */
1198 {0x0C14, 2342, 0}, /* CFG_VOUT1_D18_OUT */
1199 {0x0C20, 2463, 0}, /* CFG_VOUT1_D19_OUT */
1200 {0x0C2C, 2439, 0}, /* CFG_VOUT1_D1_OUT */
1201 {0x0C38, 2304, 0}, /* CFG_VOUT1_D20_OUT */
1202 {0x0C44, 2103, 0}, /* CFG_VOUT1_D21_OUT */
1203 {0x0C50, 2145, 0}, /* CFG_VOUT1_D22_OUT */
1204 {0x0C5C, 1932, 0}, /* CFG_VOUT1_D23_OUT */
1205 {0x0C68, 2200, 0}, /* CFG_VOUT1_D2_OUT */
1206 {0x0C74, 2355, 0}, /* CFG_VOUT1_D3_OUT */
1207 {0x0C80, 3215, 0}, /* CFG_VOUT1_D4_OUT */
1208 {0x0C8C, 2314, 0}, /* CFG_VOUT1_D5_OUT */
1209 {0x0C98, 2238, 0}, /* CFG_VOUT1_D6_OUT */
1210 {0x0CA4, 2381, 0}, /* CFG_VOUT1_D7_OUT */
1211 {0x0CB0, 2138, 0}, /* CFG_VOUT1_D8_OUT */
1212 {0x0CBC, 2383, 0}, /* CFG_VOUT1_D9_OUT */
1213 {0x0CC8, 1984, 0}, /* CFG_VOUT1_DE_OUT */
1214 {0x0CE0, 1947, 0}, /* CFG_VOUT1_HSYNC_OUT */
1215 {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */
Nishanth Menon89a38952016-11-25 11:14:22 +0530[diff] [blame]1216};
1217
Lokesh Vutla443b0df2017-12-29 11:47:55 +0530[diff] [blame]1218const struct iodelay_cfg_entry iodelay_cfg_array_am574x_idk[] = {
1219 {0x0114, 2199, 621}, /* CFG_GPMC_A0_IN */
1220 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1221 {0x012C, 2133, 859}, /* CFG_GPMC_A11_IN */
1222 {0x0138, 2258, 562}, /* CFG_GPMC_A12_IN */
1223 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1224 {0x0150, 2149, 1052}, /* CFG_GPMC_A14_IN */
1225 {0x015C, 2121, 997}, /* CFG_GPMC_A15_IN */
1226 {0x0168, 2159, 1134}, /* CFG_GPMC_A16_IN */
1227 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1228 {0x0174, 2135, 1085}, /* CFG_GPMC_A17_IN */
1229 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1230 {0x0198, 1989, 612}, /* CFG_GPMC_A1_IN */
1231 {0x0204, 2218, 912}, /* CFG_GPMC_A2_IN */
1232 {0x0210, 2168, 963}, /* CFG_GPMC_A3_IN */
1233 {0x021C, 2196, 813}, /* CFG_GPMC_A4_IN */
1234 {0x0228, 2082, 782}, /* CFG_GPMC_A5_IN */
1235 {0x0234, 2098, 407}, /* CFG_GPMC_A6_IN */
1236 {0x0240, 2343, 585}, /* CFG_GPMC_A7_IN */
1237 {0x024C, 2030, 685}, /* CFG_GPMC_A8_IN */
1238 {0x0258, 2116, 832}, /* CFG_GPMC_A9_IN */
1239 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1240 {0x0590, 1000, 3900}, /* CFG_MCASP5_ACLKX_OUT */
1241 {0x05AC, 1000, 3800}, /* CFG_MCASP5_FSX_IN */
1242 {0x06F0, 451, 0}, /* CFG_RGMII0_RXC_IN */
1243 {0x06FC, 127, 1571}, /* CFG_RGMII0_RXCTL_IN */
1244 {0x0708, 165, 1178}, /* CFG_RGMII0_RXD0_IN */
1245 {0x0714, 136, 1302}, /* CFG_RGMII0_RXD1_IN */
1246 {0x0720, 0, 1520}, /* CFG_RGMII0_RXD2_IN */
1247 {0x072C, 28, 1690}, /* CFG_RGMII0_RXD3_IN */
1248 {0x0740, 121, 0}, /* CFG_RGMII0_TXC_OUT */
1249 {0x074C, 60, 0}, /* CFG_RGMII0_TXCTL_OUT */
1250 {0x0758, 153, 0}, /* CFG_RGMII0_TXD0_OUT */
1251 {0x0764, 35, 0}, /* CFG_RGMII0_TXD1_OUT */
1252 {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
1253 {0x077C, 172, 0}, /* CFG_RGMII0_TXD3_OUT */
1254 {0x0A70, 147, 0}, /* CFG_VIN2A_D12_OUT */
1255 {0x0A7C, 110, 0}, /* CFG_VIN2A_D13_OUT */
1256 {0x0A88, 18, 0}, /* CFG_VIN2A_D14_OUT */
1257 {0x0A94, 82, 0}, /* CFG_VIN2A_D15_OUT */
1258 {0x0AA0, 33, 0}, /* CFG_VIN2A_D16_OUT */
1259 {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
1260 {0x0AB0, 417, 0}, /* CFG_VIN2A_D18_IN */
1261 {0x0ABC, 156, 843}, /* CFG_VIN2A_D19_IN */
1262 {0x0AD4, 223, 1413}, /* CFG_VIN2A_D20_IN */
1263 {0x0AE0, 169, 1415}, /* CFG_VIN2A_D21_IN */
1264 {0x0AEC, 43, 1150}, /* CFG_VIN2A_D22_IN */
1265 {0x0AF8, 0, 1210}, /* CFG_VIN2A_D23_IN */
1266 {0x0B30, 0, 200}, /* CFG_VIN2A_D5_OUT */
1267 {0x0B9C, 1281, 497}, /* CFG_VOUT1_CLK_OUT */
1268 {0x0BA8, 379, 0}, /* CFG_VOUT1_D0_OUT */
1269 {0x0BB4, 441, 0}, /* CFG_VOUT1_D10_OUT */
1270 {0x0BC0, 461, 0}, /* CFG_VOUT1_D11_OUT */
1271 {0x0BCC, 1189, 0}, /* CFG_VOUT1_D12_OUT */
1272 {0x0BD8, 312, 0}, /* CFG_VOUT1_D13_OUT */
1273 {0x0BE4, 298, 0}, /* CFG_VOUT1_D14_OUT */
1274 {0x0BF0, 284, 0}, /* CFG_VOUT1_D15_OUT */
1275 {0x0BFC, 152, 0}, /* CFG_VOUT1_D16_OUT */
1276 {0x0C08, 216, 0}, /* CFG_VOUT1_D17_OUT */
1277 {0x0C14, 408, 0}, /* CFG_VOUT1_D18_OUT */
1278 {0x0C20, 519, 0}, /* CFG_VOUT1_D19_OUT */
1279 {0x0C2C, 475, 0}, /* CFG_VOUT1_D1_OUT */
1280 {0x0C38, 316, 0}, /* CFG_VOUT1_D20_OUT */
1281 {0x0C44, 59, 0}, /* CFG_VOUT1_D21_OUT */
1282 {0x0C50, 221, 0}, /* CFG_VOUT1_D22_OUT */
1283 {0x0C5C, 96, 0}, /* CFG_VOUT1_D23_OUT */
1284 {0x0C68, 264, 0}, /* CFG_VOUT1_D2_OUT */
1285 {0x0C74, 421, 0}, /* CFG_VOUT1_D3_OUT */
1286 {0x0C80, 1257, 0}, /* CFG_VOUT1_D4_OUT */
1287 {0x0C8C, 432, 0}, /* CFG_VOUT1_D5_OUT */
1288 {0x0C98, 436, 0}, /* CFG_VOUT1_D6_OUT */
1289 {0x0CA4, 440, 0}, /* CFG_VOUT1_D7_OUT */
1290 {0x0CB0, 81, 100}, /* CFG_VOUT1_D8_OUT */
1291 {0x0CBC, 471, 0}, /* CFG_VOUT1_D9_OUT */
1292 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1293 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1294 {0x0CEC, 815, 0}, /* CFG_VOUT1_VSYNC_OUT */
1295};
1296
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]1297const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]1298 {0x0114, 1861, 901}, /* CFG_GPMC_A0_IN */
1299 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1300 {0x012C, 1783, 1178}, /* CFG_GPMC_A11_IN */
1301 {0x0138, 1903, 853}, /* CFG_GPMC_A12_IN */
1302 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1303 {0x0150, 2575, 966}, /* CFG_GPMC_A14_IN */
1304 {0x015C, 2503, 889}, /* CFG_GPMC_A15_IN */
1305 {0x0168, 2528, 1007}, /* CFG_GPMC_A16_IN */
1306 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1307 {0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
1308 {0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
1309 {0x0198, 1652, 891}, /* CFG_GPMC_A1_IN */
1310 {0x0204, 1888, 1212}, /* CFG_GPMC_A2_IN */
1311 {0x0210, 1839, 1274}, /* CFG_GPMC_A3_IN */
1312 {0x021C, 1868, 1113}, /* CFG_GPMC_A4_IN */
1313 {0x0228, 1757, 1079}, /* CFG_GPMC_A5_IN */
1314 {0x0234, 1800, 670}, /* CFG_GPMC_A6_IN */
1315 {0x0240, 1967, 898}, /* CFG_GPMC_A7_IN */
1316 {0x024C, 1731, 959}, /* CFG_GPMC_A8_IN */
1317 {0x0258, 1766, 1150}, /* CFG_GPMC_A9_IN */
1318 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1319 {0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */
1320 {0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]1321 {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
1322 {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
1323 {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
1324 {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
1325 {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
1326 {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
1327 {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
1328 {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
1329 {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
1330 {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
1331 {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
1332 {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
1333 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1334 {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
1335 {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
1336 {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
1337 {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
1338 {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
1339 {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
1340 {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
1341 {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
1342 {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
1343 {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
1344 {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
Lokesh Vutlac887bef2016-11-25 11:14:23 +0530[diff] [blame]1345 {0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
Lokesh Vutlae79d2dc2017-06-05 14:48:15 +0530[diff] [blame]1346 {0x0B9C, 1126, 751}, /* CFG_VOUT1_CLK_OUT */
1347 {0x0BA8, 395, 0}, /* CFG_VOUT1_D0_OUT */
1348 {0x0BB4, 282, 0}, /* CFG_VOUT1_D10_OUT */
1349 {0x0BC0, 348, 0}, /* CFG_VOUT1_D11_OUT */
1350 {0x0BCC, 1240, 0}, /* CFG_VOUT1_D12_OUT */
1351 {0x0BD8, 182, 0}, /* CFG_VOUT1_D13_OUT */
1352 {0x0BE4, 311, 0}, /* CFG_VOUT1_D14_OUT */
1353 {0x0BF0, 285, 0}, /* CFG_VOUT1_D15_OUT */
1354 {0x0BFC, 166, 0}, /* CFG_VOUT1_D16_OUT */
1355 {0x0C08, 278, 0}, /* CFG_VOUT1_D17_OUT */
1356 {0x0C14, 425, 0}, /* CFG_VOUT1_D18_OUT */
1357 {0x0C20, 516, 0}, /* CFG_VOUT1_D19_OUT */
1358 {0x0C2C, 521, 0}, /* CFG_VOUT1_D1_OUT */
1359 {0x0C38, 386, 0}, /* CFG_VOUT1_D20_OUT */
1360 {0x0C44, 111, 0}, /* CFG_VOUT1_D21_OUT */
1361 {0x0C50, 227, 0}, /* CFG_VOUT1_D22_OUT */
1362 {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */
1363 {0x0C68, 282, 0}, /* CFG_VOUT1_D2_OUT */
1364 {0x0C74, 438, 0}, /* CFG_VOUT1_D3_OUT */
1365 {0x0C80, 1298, 0}, /* CFG_VOUT1_D4_OUT */
1366 {0x0C8C, 397, 0}, /* CFG_VOUT1_D5_OUT */
1367 {0x0C98, 321, 0}, /* CFG_VOUT1_D6_OUT */
1368 {0x0CA4, 155, 309}, /* CFG_VOUT1_D7_OUT */
1369 {0x0CB0, 212, 0}, /* CFG_VOUT1_D8_OUT */
1370 {0x0CBC, 466, 0}, /* CFG_VOUT1_D9_OUT */
1371 {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
1372 {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
1373 {0x0CEC, 139, 701}, /* CFG_VOUT1_VSYNC_OUT */
Steve Kipiszc020d352016-04-08 17:01:29 -0500[diff] [blame]1374};
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]1375
1376const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]1377 {0x0114, 1873, 702}, /* CFG_GPMC_A0_IN */
1378 {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
1379 {0x012C, 1851, 1011}, /* CFG_GPMC_A11_IN */
1380 {0x0138, 2009, 601}, /* CFG_GPMC_A12_IN */
1381 {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
1382 {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
1383 {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
1384 {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
1385 {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
1386 {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
1387 {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
1388 {0x0198, 1629, 772}, /* CFG_GPMC_A1_IN */
1389 {0x0204, 1734, 898}, /* CFG_GPMC_A2_IN */
1390 {0x0210, 1757, 1076}, /* CFG_GPMC_A3_IN */
1391 {0x021C, 1794, 893}, /* CFG_GPMC_A4_IN */
1392 {0x0228, 1726, 853}, /* CFG_GPMC_A5_IN */
1393 {0x0234, 1792, 612}, /* CFG_GPMC_A6_IN */
1394 {0x0240, 2117, 610}, /* CFG_GPMC_A7_IN */
1395 {0x024C, 1758, 653}, /* CFG_GPMC_A8_IN */
1396 {0x0258, 1705, 899}, /* CFG_GPMC_A9_IN */
1397 {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
1398 {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
1399 {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
1400 {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
1401 {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
1402 {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
1403 {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
1404 {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
1405 {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
1406 {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
1407 {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
1408 {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
1409 {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
1410 {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
1411 {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
1412 {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
1413 {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
1414 {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
1415 {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
1416 {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
1417 {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
1418 {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
1419 {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
1420 {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
1421 {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
Steve Kipisz4d8397c2016-11-25 11:14:24 +0530[diff] [blame]1422};
1423
Lokesh Vutla2d7e9e92017-06-05 14:48:16 +0530[diff] [blame]1424const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
1425 {0x0588, 2100, 1959}, /* CFG_MCASP5_ACLKX_IN */
1426 {0x05AC, 2100, 1780}, /* CFG_MCASP5_FSX_IN */
1427 {0x0B30, 0, 400}, /* CFG_VIN2A_D5_OUT */
1428};
Lokesh Vutla8f6c80b2015-06-04 16:42:42 +0530[diff] [blame]1429#endif
Felipe Balbi1e4ad742014-11-10 14:02:44 -0600[diff] [blame]1430#endif /* _MUX_DATA_BEAGLE_X15_H_ */